JPH0991992A - Semiconductor memory device - Google Patents

Abstract

(57) Abstract: A semiconductor memory device reduces a chip occupation rate by a Hugh program circuit for replacing a defective portion with a redundant configuration. A plurality of respective memory mats have a plurality of redundant data lines, and a first fuse program circuit (FA0 to FA19) for setting a defective column address to be replaced by the redundant data lines for each memory mat. Are shared by the selection signals (RS0, RS1) of the plurality of redundant data lines. Which redundant data line selection signal reflects the address programmed in the first fuse program circuit depends on the second fuse program circuit (FR0).
00 to FR019, FR100 to FR119).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundant structure for relieving a partial defect,
In particular, the present invention relates to a technique for reducing the chip occupation rate of a Hugh program circuit for replacing a defective portion with a redundant configuration, and for example, a technique effectively applied to a DRAM (Dynamic Random Access Memory) or a synchronous DRAM.

[0002]

2. Description of the Related Art In a semiconductor memory device, as the degree of integration is increased and the chip area is increased, defects due to various causes are highly likely to occur, leading to a decrease in yield.
As a means for solving this problem, a technique for relieving a defective memory cell portion has been indispensable conventionally.
In this technique, in addition to regular memory cells, a spare memory cell is provided in advance, and when a defective memory cell that does not operate normally is found in the inspection process, the spare memory cell is not operated normally. It is used instead of a memory cell.

As a technique for replacing a defective memory cell with a spare memory cell, the address of the defective memory cell is set in the fuse program circuit, and the access address is compared with the address of the set defective memory cell. It is possible to employ a technique of internally replacing the access address with the address of the spare memory cell when the two match. At this time, such address replacement can be performed on the output of the address buffer. By replacing the address of the output of the address buffer, the area occupied by the chip of the fuse program circuit can be made small. However, in that case, even if the memory cell array is divided into a plurality of memory mats,
Since the address replacement is performed in the same manner in all the memory mats, high relief efficiency cannot be realized unless a defect occurs at the same address in each memory mat.

Therefore, the present inventor provides a spare data line for repair (also referred to as a redundant data line) for each memory mat, and programs a repaired address of the redundant data line in the fuse program circuit for each memory mat. , And examined improving the relief efficiency. That is, a fuse program circuit is provided for programming, for each memory mat, in which memory mat, for each predecode signal of the address signal used for selecting the data line, it is used for selecting the redundant data line. The designated predecode signal is used as a selection signal for the spare data line. Therefore, the fuse program circuit is required for each selection signal of the spare data line.

[0005]

However, since the number of predecode signals is larger than the number of bits of the internal complementary address signal, the number of program fuses required is roughly the product of the number of memory mats and the number of predecode signals. It has been clarified by the present inventor that, even if the relief efficiency is improved, the chip occupation area of the fuse program circuit is inevitably increased. In particular, a DRAM that realizes a large storage capacity,
In a synchronous DRAM, a flash memory as an electrically rewritable non-volatile semiconductor memory device, and the like, it is possible to improve the relief efficiency and reduce the chip occupancy rate of the circuit for relief to contribute to the increase of the storage capacity. Needed to be able to.

It is an object of the present invention to provide a semiconductor memory device capable of reducing the chip occupation rate by a Hugh program circuit for replacing a defective portion with a redundant configuration and improving the relief efficiency for the defect. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the semiconductor memory device is provided with a plurality of memory mats each having a matrix arrangement of a plurality of memory cells whose select terminals are connected to word lines and whose data terminals are connected to data lines. A predetermined memory mat is selected from among the memory mats, memory cells included in the selected memory mat are accessible from the outside, and each of the memory mats has a normal data line to be a relief target when there is a defect. A relief circuit (RDD) is provided which includes a plurality of redundant data lines for replacing defective normal data lines and which can specify the normal data lines to be replaced by the redundant data lines in units of memory mats. As shown in FIG. 1, the relief circuit includes a predecode signal (CP0 to C) of an address signal used for selecting a data line.
P19) based on the redundant data line selection signal (RS0,
A plurality of logic means (LOG0, LO) for commonly generating RS1) for each memory mat (MAT0 to MAT7).
G1) and for each predecode signal of the address signals (Y0 to Y7) used for selecting the data line, which memory mat is used to replace the redundant data line is programmed and programmed in memory mat units. The first fuse program circuit (FA to FA) whose output is set to the first state in response to the selected state of the memory mat.
19) and a second fuse program circuit (FR000 to FR019, FR100 to FR11) in which it is programmed which redundant data line selection signal reflects the state programmed in the first fuse program circuit.
9), and information transmission by placing the output of the first fuse program circuit arranged in the transmission path of the predecode signal to the respective logic means in the first state and selected by the second fuse program circuit. First transfer gate means (T000 to T019, T1) that are controlled to be possible
00-T119).

According to the above means, each of the plurality of memory mats (MAT0 to MAT7) has a plurality of redundant data lines, and the defective column address to be replaced by the redundant data lines is set for each memory mat. The first fuse program circuits (FA0 to FA19) are shared by the selection signal (RS0, RS1) system of the plurality of redundant data lines. The first fuse program circuit includes a number of predecode signals (CP0 to CP19) and a memory mat (M
A number of fuses (F20) equal to the product of the number of AT0-MAT7) is required. Which redundancy data line selection signal system should be used to rescue the address programmed in the first fuse program circuit (FA0 to FA19) depends on the second fuse program circuit (FR000 to FR019).
And FR100-FR119) programmed state. The second fuse program circuit includes a total of twice as many fuses (F21) as the number of predecode signals (CP0 to CP19). Therefore, it becomes possible to reduce the required number of fuses as compared with the case where the first fuse program circuit is provided for each selection signal system of the redundant data line to configure the relief circuit.

According to another mode in which the number of fuses can be further reduced, the relief circuit (RDD) has a predecode signal (CP0 to CP19) of an address signal used for selecting a data line, as illustrated in FIG. ), A logic means (LOG0, LOG1) for commonly generating a redundant data line selection signal for each memory mat, and which memory mat is used for each predecode signal of an address signal used for selecting the data line. In the first fuse program circuit (F), the memory fuse is programmed to be used for replacement with the redundant data line and the output is brought to the first state in response to the selected state of the programmed memory mat.
A to FA19) and a second fuse program circuit (FR000 to FR007, FR100 to F) for programming which redundant data line selection signal reflects the state programmed in the first fuse program circuit.
R107) and a portion of the predecode signal to the logic means, the output of the first fuse program circuit being placed in the transmission path of the predecode signal being in the first state and being selected by the second fuse program circuit. First transfer gate means (T000 to T00) that is controlled to be capable of transmission.
7, T100 to T107), and the output of the first fuse program circuit placed in the transmission path of the remaining predecode signal to the logic means is controlled to be capable of transmitting information by setting the output of the first fuse program circuit to the first state. Second transfer gate means (T008 to T019, T108 to T119) are provided. The first transfer gate means corresponds to the predecode signal of the lower address of the address signal for selecting the data line.

Means for reducing the number of fuses are as follows:
Second fuse circuit (FR000 to FR007, FR1
00-FR107) as a part of transfer gate means (T000
.About.T007, T100 to T107). Since the number of the second fuse circuits is reduced as compared with the above means, the chip occupation area by the fuse is further reduced. At this time, the transfer gate means forming a pair with the second fuse circuit is made to correspond to the predecode signal of the lower address of the data line selecting address signal. Considering that defects usually tend to be concentrated in a specific part of the chip, even if the second fuse circuit is provided only in the lower address, the relief efficiency is prevented from being significantly reduced. It

When the repair circuit selects a redundant data line, a normal data line selection signal is commonly applied to a plurality of memory mats based on the predecode signal in order to prevent selection of the normal data line. A gate means is provided in the input path of the column address decoder (CDEC) to be formed,
The relief circuit controls all predecode signals supplied to the column address decoder to a non-selection level according to a state where a redundant data line is selected (GE).
Is supplied to the gate means.

[0014]

FIG. 2 is an overall block diagram of a DRAM according to an embodiment of the present invention. Although not particularly limited, the DRAM 1 shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The DRAM 1 has eight memory mats MAT0 to MAT7. In each of the memory mats (MAT0 to MAT7), a dynamic type memory cell having a selection terminal connected to a word line and a data input / output terminal connected to a data line is arranged in a matrix. The data lines of the memory mats MAT0 and MAT1 adjacent to each other are coupled through a pair of data line separation switch circuits SH0 and SH1, and a sense amplifier / precharge circuit SA / PCa is provided between the data line separation switch circuits SH0 and SH1. , And a column switch circuit CSWa is arranged. Similarly, for the other memory mats MAT2 to MAT7, the data line separation switch circuits SH2 to SH7, the sense amplifier,
Precharge circuits SA · PCb to SA · PCd and column switch circuits CSWb to CSWd are arranged. The respective column switch circuits CSWa to CSWd are coupled to the data input / output buffer DBUF via main amplifiers AMPa to AMPd.

The selection of the word line in each of the memory mats MAT0 to MAT7 is performed by a row address decoder (also referred to as a row decoder) RDEC provided in each memory mat.
This is performed by decoding output of L and RDECR. The selection of the data line is performed by a column address decoder (also referred to as a column decoder) CDEC common to the eight memory mats MAT0 to MAT7. The address signal is externally supplied in the address multiplex format, and the row address signal is taken into the row address buffer RABUF and converted into an internal complementary row address signal. The column address signal is taken into the column address buffer CABUF and converted into an internal complementary column address signal.

The controller CONT uses the row address strobe signal RASB as an external access control signal.
The column address strobe signal CASB, the write enable signal WEB and the like are received. The row address strobe signal RASB indicates chip selection according to its active level and also informs that the row address signal is fixed. The column address strobe signal CASB indicates that the column address signal is determined by its active level. Write enable signal WE
Indicates the write operation by its active level,
A read operation is instructed by the inactive level. Although not shown, the DRAM of the present embodiment performs a stored information refresh operation in a CBR (CAS Before RAS) refresh operation mode, which is not particularly limited. Incidentally, among various control signals inside the DRAM 1, the controller CONT generates a control signal whose source is not clearly indicated.

According to this embodiment, the row address signal is X
11 bits from 0 to X10, column address signal from Y0
It is 8 bits of Y7. Although not particularly limited, data input / output is in 1-bit units. X8 to X10 are regarded as signals instructing which one of the memory mats MAT0 to MAT7 is selected, X0 to X7 are regarded as signals instructing the word line to be selected in the memory mat, and Y0 to X0.
Y7 is regarded as a signal indicating a data line to be selected.

Internal complementary address signals corresponding to X8 to X10 are supplied to the controller CONT. The controller CONT, based on the internal complementary address signal corresponding to X8, switches the data line segment switch circuits SH0, SH2.
The control signal φSHL for SH4 and SH6 is generated, and the control signal φSHR for the data line segment switch circuits SH1, SH3, SH5 and SH7 is generated. In the chip non-selection period, both control signals φSHL and φSHR are both set to a high level, and the left and right data line segment switch circuits are controlled to be in a conductive state, and a precharge circuit (precharge circuit) which is operated in the chip non-selection period (precharge -The potential of the left and right data lines is set to a desired level for the read operation by the precharge operation (included in the sense amplifier circuit). In the chip selection period, one of the control signals φSHL and φSHR is set to the high level according to the logical value of X8. Controller CON
T controls any one of the control signals φAMPa to φAMPd to a selection level based on the internal complementary address signals corresponding to X9 and X10, thereby activating any one of the main amplifiers AMPa to AMPd. To do. As a result, one memory mat that operates by interfacing with the data buffer DBUF is selected.

The internal complementary address signals corresponding to X0 to X7 are supplied to row decoders RDECL and RDECR. The row decoder RDECL is activated and controlled by the control signal φDL, and the row decoder RDECR is activated and controlled by the control signal φDR. Controller CO
NT generates the control signals φDL and φDR based on the internal complementary address signal corresponding to X8. Both control signals φDL and φDR are set to the low level during the chip non-selection period, and the left and right row decoders RDECL and RD are set.
Control ECR to inactive state. In the chip selection period, one of the control signals φDL and φDR is set to the high level according to the logical value of X8, and the row decoder RDECL or RDECR is activated. The activated row decoder RDECL or RDECR decodes the internal complementary address signals corresponding to X0 to X7 and performs a word line selecting operation.

The internal complementary address signals corresponding to Y0 to Y7 are supplied to the predecoder PDEC, and the decoded output thereof is received by the column decoder CDEC, so that the column decoder CDEC receives the data line selection signals corresponding to Y0 to Y7. TS0 to TS256 are generated. The data line selection signals TS0 to TS256 are used for each memory mat M.
Column switch circuits CSWa-CS of AT0-MAT7
Commonly supplied to Wd.

Therefore, in one memory mat selected by X8 to X10, among memory cells whose selection terminals are coupled to the word lines selected at X0 to X7, Y0 is selected.
The memory cell whose data input / output terminal is connected to the data line selected by Y7 is connected to the data buffer DBUF via the main amplifier. In parallel with this, in the other three memory mats in which the word line selection operation is performed, the stored information of the memory cell whose selection terminal is coupled to the selected word line is refreshed.

Each of the memory mats MAT0 to MAT7 includes a normal array portion to be relieved when there is a defect, and a redundant array portion for relieving the defective normal array portion. In this embodiment, a redundant configuration of a column system will be described. In this embodiment, the regular array portion is a portion corresponding to the column selection signals TS0 to TS256. The redundant array portion is a portion corresponding to the redundant column selection signals RS0 to RS1. Although the details will be described later, the redundancy column selection signals RS0 to RS1 are generated by the relief circuit RDD which receives the output of the predecoder PDEC and the like.

FIG. 3 shows a circuit configuration of the DTL1 portion of FIG. 2 as an example of the normal array portion. DL00,
DL00B is included in the memory mat MAT0, DL1
Reference numerals 0 and DL10B are normal complementary data lines included in the memory mat MAT1 as representatives. In reality, there are 256 pairs of regular complementary data lines in the regular array portion of each memory mat. PCAa is a precharge circuit and SAa sense amplifier, and is included in the sense amplifier / precharge circuit SA / PCa. The memory mat MAT0 and the memory mat MAT1 share the precharge circuit PCa, the sense amplifier SAa, and the column switch circuit CSWa. For example, memory mat M
The complementary data lines DL00 and DL00B of AT0 and the complementary data lines DL10 and BL10B of the memory mat MAT1 share the precharge circuit PCa, the sense amplifier SAa, and the column switch CSa, and these shared circuits are the data line separation switch circuit SH0. Through the complementary data lines BL00, DL00B via
Further, the shared circuits can be selectively connected and separated from the complementary data lines DL10 and DL10B via the data line separation switch circuit SH1. Although not described in detail, the other complementary data lines also share the precharge circuit PCa, the sense amplifier SAa, and the column switch circuit CSWa on the left and right sides. The data line separation switch circuit SH0 is an N channel type MO switch-controlled by a control signal φSHL.
The data line separation switch circuit SH1 is composed of S transistors Q6 and Q6, and an N-channel MOS transistor Q7, which is switch-controlled by a control signal φSHR.
It is composed of Q7.

In FIG. 3, WLm and WLn are word lines in the representative memory mats MAT0 and MAT1. The memory cell MC is a one-transistor type composed of an n-channel MOS selection transistor Q1 and a storage capacitor C. The gate of the transistor Q1 is connected to a word line, and the source / drain of the transistor Q1 is connected to one complementary data line. The other electrode of the storage capacitor receives the cell plate potential.

The precharge circuit PCa is an n-channel type equalize MOS transistor Q which is switch-controlled by a control signal φPC as illustrated in FIG.
2. Precharge MOS transistors Q3 and Q4. Precharge MOS transistor Q3
The control signal φPC is set to a high level during the chip non-selection period to supply the precharge potential (eg, the potential Vdd / 2 which is ½ of the power supply voltage) to the input node of the corresponding sense amplifier SAa. The equalizing MOS transistor Q2 balances the potential difference between the input nodes of the corresponding sense amplifiers SAa when the control signal φPCa is set to the high level.

As shown in FIG. 3, the sense amplifier SAa is a CM including MOS transistors Q10 and Q11.
It has a CMOS inverter composed of an OS inverter and MOS transistors Q12 and Q13, and is configured in a static latch form in which one input is cross-coupled to the other output. The operating power supply (ground potential Vss, power supply potential Vdd) of the sense amplifier SAa is controlled to be in the ON state by the control signal φSA being set to the high level during the chip selection period.
And a p-channel MOS transistor Q15.

The column switch CSWa selectively complements the complementary data lines DL00, DL00B or DL10, DL10B connected by the data line separation switch circuit SH0 or SH1 as illustrated in FIG.
It is constituted by n-channel type MOS transistors Q16 and Q17 which are electrically connected to Da and CDaB. The transistor is switch-controlled by the column selection signal TS0. The complementary common data lines CDa and CDaB are coupled to the main amplifier AMPa.

FIG. 4 shows a circuit configuration of the DTL2 portion of FIG. 2 as an example of the redundant array portion. RDL0
0 and RDL00B are included in the memory mat MAT0 and R
DL10 and RDL10B are redundant complementary data lines, which are included in the memory mat MAT1 and are typically shown. In reality, there are two pairs of redundant complementary data lines in the redundant array portion of each memory mat. As described with reference to FIG. 3, the MOS transistors Q16 and Q17 forming the column switch circuit CSWa of the normal array portion are switch-controlled by the corresponding column selection signals TS0 to TS256. In the redundant array part, the column switch CSW
a is a complementary data line R connected by the data line separation switch circuit SH0 or SH1 as illustrated in FIG.
DL00, RDL00B or RDL10, RDL10B
Are selectively connected to complementary common data lines CDa and CDaB for n-channel MOS transistors Q18 and Q19.
Composed of The transistors Q18 and Q19
Are switch-controlled by the redundant column selection signals RS0 and RS1. Since other configurations are similar to those of FIG. 3, the same circuit elements are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 5 is a block diagram focusing on the column system of the DRAM 1 of this embodiment. In FIG. 5, the predecoder PDEC is a decoding unit PDEC1 of Y0 to Y2,
The decoding unit PDEC2 for Y3 to Y5 and the decoding unit PDEC3 for Y6 and Y7 are provided. CP0 to CP7 are decode outputs of the decode unit PDEC1, CP8 to CP15 are decode outputs of the decode unit PDEC2, CP16 to CP
Reference numeral 19 denotes a decode output of the decoding unit PDEC3, which are supplied to the relief circuit RDD and the column decoder CDEC. When the internal complementary address signals of the column address signals Y0 to Y7 are supplied to the predecoder PDEC, any one of the decode signals CP0 to CP7, any one of the decode signals CP8 to CP15, and the decode signal CP16. One of CP19 to CP19 is set to a selection level such as a high level. G1 to G3 are gate circuits arranged between the output of the predecoder PDEC and the input of the column decoder CDEC. Gate circuit G
When the control signal GE is deactivated, all the outputs of 1 to G3 are forced to the non-selected level regardless of the decode outputs CP0 to CP19 of the predecoder PDEC. The control signal GE is activated in response to the redundant column selection signal RS0 or RS1 being set to the selection level, thereby suppressing the column selection operation in the normal array portion by the column selection signals TS0 to TS256.

FIG. 1 shows an example block diagram of the relief circuit RDD. The relief circuit RDD replaces the normal data line to be replaced by the redundant data line with the memory mats MAT0 to MAT0 to MAT0.
It is possible to specify in MAT7 units. T000 to T019 shown in FIG. 1 are the predecode signals CP0.
To CP19 are provided in one-to-one correspondence with the corresponding predecode signals, and the output of each of the transfer gate circuits T000 to T019 is the logic circuit L.
The logical sum is taken in OG0, and thereby the redundant column selection signal RS0 is generated. Similarly, transfer gate circuits T100 to T119 are provided in a one-to-one correspondence with the predecode signals CP0 to CP19, and the logic circuit LOG1 takes the logical sum of the outputs of these transfer gate circuits T100 to T119, whereby the aforementioned The redundant column selection signal RS1 is generated. The transfer gate circuits T000 to T
The transfer control for 019 and T100 to T119 is performed by the first fuse program circuits FA0 to FA19 and the second fuse program circuits FR000 to FR019, FR10.
It is controlled by the programmed states of 0-FR119.

FIG. 6 partially shows the detailed circuit example of FIG. The transfer gate circuits T000 and T illustrated in FIG.
Reference numeral 100 denotes a CMOS (complementary type M) switch-controlled by the output of the clocked inverter 10 and an inverted signal of the output.
OS) The transfer gate 11 includes the CMOS
When the transfer gate 11 is turned on, the corresponding predecode signal CP0 is output to the logic circuit LOG.
0, transmitted to LOG1.

The logic circuit LOG0 inverts the output of the 3-input NAND gate 12 by the inverter 13 to generate the redundancy selection signal RS0. Similarly, the logic circuit LOG
1 is the inverter 1 that outputs the output of the 3-input NAND gate 14.
It is inverted at 5 to generate the redundancy selection signal RS1. The outputs of the transfer gate circuits T000 to T019 are Y0 to Y2.
The ones corresponding to the predecode signals CP0 to CP7 of the system are wired-OR coupled, and those corresponding to the predecode signals CP8 to CP15 of the Y3 to Y5 system are wired OR coupled, and the predecode signal CP1 of the Y6 to Y7 system.
6 to CP19 are wired-OR coupled, and the wired-OR coupled signals are applied to the inputs of the NAND gates 12 and 14, respectively. An N-channel type discharge MOS transistor Q23 is provided at each input of the NAND gates 12 and 14, and this transistor Q23 is switched by a control signal RE which is set to a low level when the relief circuit RDD repairs a defect. Controlled. Therefore, when the relief circuit does not perform the relief, the redundancy selection signals RS0 and RS1 are forced to the low level which is the non-selection level.

The first fuse program circuit FA0
.About.FA19 are provided corresponding to predecode signals CP0 to CP19. For each predecode signals CP0 to CP19, which memory mat is used to replace the redundant data line is programmed and programmed in memory mat units. The memory mat has mat selection signals M0 to M7.
The output is set to a first state, for example, a high level in response to the state selected in. The mat selection signals M0 to M7 are X8 to
The controller CONT generates based on X10.

Specifically, like the first fuse program circuit FA0 illustrated in FIG. 6, the mat select signal M0 is selected.
Eight pairs of series circuits of a P-channel type MOS transistor Q20 and a fuse F20 which are switch-controlled by the inversion signal of M7 to M7 are provided between the input A1 of the inverter 20 and the power supply terminal Vdd, and The input A1 is coupled to the ground terminal Vss via an N-channel type discharge MOS transistor Q21 which is switch-controlled by the control signal RB. Q22 is the inverter 2
0 output is received by the gate electrode and the source electrode is the ground terminal V
The drain electrode is coupled to the input of the inverter INV1 at ss and is an N-channel MOS transistor for clamping. Other first fuse program circuit FP
M1 to FPM19 are similarly configured. The control signal R
B is set to the high level in the chip non-selection period, and the input node A1 of the inverter 20 is initialized to the low level. The control signal RB is set to the low level in synchronization with the chip selection, so that the discharge MOS transistor Q21 is cut off. Mat selection signals M0 to M7
Is set to a high level (selection level) according to the logical values of X8 to X10. The MOS transistor Q20, whose gate receives the inverted signal of the mat selection signal set to the selection level, is turned on.
Fuse F20 connected in series with S transistor Q20
Is disconnected, the node A1 is set to the high level, and if the fuse F20 connected in series to the MOS transistor Q20 is disconnected, the node A1 maintains the low level.

The second fuse program circuit FR0
00 to FR019 and FR100 to FR119 are provided corresponding to the transfer gate circuits T000 to T119 and T100 to T119, and whether or not to enable the clocked inverter 10 of the corresponding transfer gate circuit is determined by the fuse F21. The circuit to be programmed. That is, the output and input of the inverter 16 are output as the control signal of the clocked inverter 10, and the control signal R (control signal RB is output between the input of the inverter 16 and the power supply terminal Vdd).
P-channel type M that is switch-controlled by
The OS transistor Q24 and the fuse F21 are arranged in series. The input of the inverter 16 is clamped by an N-channel MOS transistor Q25 whose gate receives the output. The input of the inverter 16 is selectively discharged by the N-channel MOS transistor Q26 whose gate receives the control signal INT. The control signal INT is set to a high level when the DRAM 1 is initialized. Second fuse program circuit FR00
0 to FR019 and FR100 to FR119 are fuses F
When the input of the inverter 16 is set to the high level by setting 21 to the non-disconnected state, the clocked inverter 1
The output of 0 is controlled to a high output impedance state. When the input of the inverter 16 is at the low level, the clocked inverter 10 is controlled so that the output operation is possible. Therefore, when the output of the first fuse program circuit FA0 is set to the high level, the second fuse program circuit F0
If the fuse F21 of R000 is cut, the predecode signal CP0 is transmitted to the logic circuit LOG0. If the fuse F21 of the second fuse program circuit FR100 is cut, the predecode signal CP0 is sent to the logic circuit L.
It is transmitted to OG1.

Next, the operation of the relief circuit will be described. In setting the address to be relieved, the first fuse program circuit FA0 is set according to the column address (Y0 to Y7) to be relieved and the memory block to be relieved.
The fuse F20 of FA19 is cut. That is,
In setting the column address to be relieved, the predecode signal that the column address (Y0 to Y7) to be relieved from the first fuse program circuits FA0 to FA19 is predecoded to the selected level. The three first fuse program circuits corresponding to (CP0 to CP19) are the targets of fuse programming. Then, in each of the three first fuse program circuits, the foods F20 corresponding to the selection signal of the memory block to be relieved is to be cut. For example,
As illustrated in FIG. 7, in the memory mat MAT0, Y0-Y2 system address = 0, Y3-Y5 system address =
0, Y6 to Y7 system address = 0 as a repair target (repair target column address is simplified in FIG.
000 "), the first fuse program circuit FA
0, FA8, and FA16 mat select signal M0
The fuse F20 corresponding to is to be cut. Figure 7
In the figure, the cut point of the fuse is indicated by X mark. Which redundancy data line selected by the redundancy selection signal RS0 or RS1 repairs the address to be repaired, which is programmed by cutting the fuse, is determined by the programming state of the second fuse programming circuit. For example, in the case of repairing with RS0 system redundancy, the second fuse program circuits FR000, F000 corresponding to the first fuse program circuits FA0, FA8, and FA16 whose fuses have been blown to set the repair address are used.
The fuse F21 of R008 and FR016 is blown.
In this manner, when the state where the column address "000" to be relieved in the memory mat MAT0 is relieved by the RS0 redundant data line is set in the first and second fuse program circuits, it corresponds to the set state. Access, the predecode signals CP0, CP8, CP16, which are set to the selection level (high level) at that time, are supplied to the NAND gate 12 through the transfer gate circuits T000, T008, T016, and thereby the redundant selection signal R.
S0 is set to a selection level such as a high level. The states of the nodes A1 to A3 in FIG. 6 at that time are shown in FIG. Further, when the same column address is repaired by RS1 redundancy, the first fuse program circuit FA is blown for the purpose of setting the repair address.
The fuses F21 of the second fuse program circuits FR100, FR108, FR116 corresponding to 0, FA8, and FA16 are blown. Thus, the column address “000” to be relieved in the memory mat MAT0
When the state in which the RS1 system redundant data line is relieved is set in the first and second fuse program circuits, if there is an access corresponding to the set state, the selection level (high level) is set at that time. Predecode signal C
P0, CP8, CP16 are transfer gate circuits T100, T
It is supplied to the NAND gate 14 via 108 and T116, and thereby the redundant selection signal RS1 is set to a selection level such as a high level.

When the redundancy selection signal RS0 or RS1 is selected, the control signal GE is activated, whereby the gates G1 to G3 do not select all the predecode signals supplied from the predecoder PDEC to the column decoder CDEC. Force level and suppress selection of regular data lines. If the control signal GE is supplied to the predecoder PDEC and the same control is performed, the gates G1 to G3 are unnecessary.
However, in that case, the time from when all the outputs of the predecoder PDEC are deselected to when the state is reflected in the output of the column decoder CDEC becomes longer than that of the embodiment.

A specific example of the relief program will be further described with reference to FIG. The repair target column address illustrated in FIG. 7 is the address “0” in the memory mat MAT0.
00 "(Y0-Y2 system address = 0, Y3-Y5 system address = 0, Y6-Y7 system address = 0), address" 001 "in the memory mat M0 (Y0-Y2 system address = 1, Y3-Y5 system address) = 0, Y6 to Y7 system address = 0), address "37" in the memory mat M3
0 "(Y0 to Y2 system address = 0, Y3 to Y5 system address = 7, Y6 to Y7 system address = 3). At this time, RS0 system redundant data is used to repair the address" 000 "in the memory mat MAT0. Since the lines are allocated, the RS1 system redundant data line is allocated to the relief of the address "001" in the memory mat M0, and the R is used to the relief of the address "370" in the memory mat M3.
The S0 system redundant data line is assigned.

According to the above embodiment, each memory mat MA
T0 to MAT7 have redundant data lines of RS0 system and RS1 system, and a first fuse program circuit FA for setting a defective column address to be replaced by the redundant data line.
0 to FA19 are shared by the RS0 system and the RS1 system. In the first fuse program circuits FA0 to FA19, a number of fuses (20 × 8 = 160 according to the present embodiment) equal to the product of the number of predecode signals CP0 to CP19 and the number of memory mats MAT0 to MAT7. F20 is included. First fuse program circuits FA0-FA1
Whether the address programmed in 9 is repaired by the RS0 system or the RS1 system is determined by the program states of the second fuse program circuits FR000 to FR019 and FR100 to FR119. Second fuse program circuits FR000-FR019 and FR100-
The FR119 has a total of predecode signals CP0 to CP1.
Twice the number 9 (20 × 2 = 40 according to the present embodiment)
Book) fuse F21 is included. Therefore, a total of 1
By using 60 fuses, redundant data lines of RS0 system and RS1 system can be assigned to defective column addresses for each memory mat. First for RS0 and RS1 systems
In the case of a configuration in which the fuse program circuits FA0 to FA19 are provided to allocate redundant data lines of RS0 system and RS1 system to defective column addresses for each memory mat,
Even if the fuse program circuits FR000 to FR019 and FR100 to FR119 are unnecessary, 320 fuses F20 are required as a whole. For example, in a semiconductor integrated circuit with a wiring pitch of 0.5 μm, the width of a fuse that can be blown by a laser is 2 to 6 μm.
m, and the fuse pitch is 7 to 11 μm. Therefore, in comparison with this, the relief circuit RDD of the present embodiment can significantly reduce the chip occupied area by the fuse while maintaining high relief efficiency.

FIG. 9 shows another example of the relief circuit RDD. Compared to FIG. 1, the relief circuit RDD shown in the figure corresponds to the transfer gate circuits T000 to T007 and T100 to T107 and corresponds to the second fuse circuits FR000 to FR00.
7, the difference is that FR100 to FR107 are provided.
The transfer gate circuits T008 to T019 and T108 to T119 not provided with the second fuse circuit have a circuit configuration in which the clocked inverter 10 in FIG. 6 is replaced by an inverter. Other circuit configurations are shown in FIGS.
The configuration is the same as that described above. In the configuration of FIG. 9, the number of second fuse circuits is made smaller than that of FIG.
This is excellent in that the area occupied by the chip by the fuse F21 can be further reduced. On the one hand, the selection of RS0 and RS1 systems is limited in that they are only enabled for Y0 to Y2 addresses. Even in that case, the second fuse circuit is provided corresponding to the lower address Y0 to Y2, and considering that the occurrence of defects usually tends to be concentrated at a specific portion of the chip, the lower address is considered. Even if the second fuse circuit is provided only in the above, the relief efficiency is prevented from being significantly reduced. For example, the relief shown in FIG. 7 can be applied to the configuration shown in FIG. In the configuration of FIG. 9, different relief addresses cannot be set for the Y3 to Y7 addresses. Such a remedy mode is a mode in which defects are omnipresent on the chip, which hardly occurs in practice.

FIG. 10 shows an embodiment of a data processing system using the DRAM 1 according to the above embodiment. The data processing system 40 includes a CPU (central processing unit) 4
1, a DRAM controller 42, an SRAM (static random access memory) 43, a ROM (read only memory) 44, a peripheral device control unit 45, and a display control device 46 are connected to a system bus 50. The DRAM controller 42 is interfaced with the CPU 41, supplies an access address for the DRAM 1 by address multiplexing, and generates a row address strobe signal, a column address strobe signal, etc. based on an access control signal from the CPU 41. The SRAM 43 is used as a work area of the CPU 41 or a temporary data storage area, and although not particularly limited, the parity control unit 47 performs a parity check on the stored data. The ROM 44 holds the operation program of the CPU 41 and the like. An external storage device 48 such as a magnetic storage device and a keyboard 49 are externally attached to the peripheral device control unit 45. The display control unit 46 includes a video RAM (VRAM) 51,
Drawing control of a display image on the video RAM 51 and control of displaying drawn data on the display 52 are performed. Since the area occupied by the fuse or the relief circuit circuit occupying most of the chip is reduced in the DRAM 1 of the above-described embodiment, the storage capacity per chip is increased accordingly, or a small package can be adopted. There is. Therefore, on the data processing system 40, the DRAM
1 can be reduced in mounting area, or a large number of DRAMs 1 can be mounted in a limited mountable area, so that the data processing system can be downsized or the mounting memory can be easily increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist thereof. No.

For example, in the above embodiment, the DRAM having the data input / output bit number of 1 bit is taken as an example, but the parallel data input / output bit number may be 4 bits or 8 bits. For example, when the number of parallel data input / output bits is 8 bits, one column selection signal TS0 to TS256 selects eight pairs of complementary data lines. Each of the redundant column selection signals RS0 and RS1 selects eight pairs of redundant complementary data lines. Further, the number of memory mats shared by one column decoder is not limited to eight, but four or one.
It may be six or the like. Further, the DRAM can be configured by including a plurality of pairs of mat configurations shown in FIG. From the viewpoint of reducing the chip occupation area by the relief circuit RDD,
The larger the memory mat structure, the larger the chip occupation area reduction rate. For example, it can be applied to a DRAM having a storage capacity of 16 Mbits or more to obtain a large reduction rate. Further, although the description of the word line relief is omitted in the above-mentioned embodiment, the present invention does not prevent including the configuration for the word line relief.

In the above description, the invention made mainly by the present inventor is the field of application which is the background of the invention.
However, the present invention is not limited to this, and is not limited to a synchronous DRAM that can be accessed at high speed in synchronization with an external clock signal, and an SRAM having a different storage format. Can be widely applied to electrically rewritable ROM such as flash memory.

[0045]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of memory mats (MA
T0 to MAT7) have a plurality of redundant data lines, and the first fuse program circuit (FA0 to FA19) for setting a defective column address to be replaced by the redundant data lines for each memory mat has a plurality of redundant data lines. The line selection signals (RS0, RS1) are commonly used. Therefore, it becomes possible to reduce the required number of fuses as compared with the case where the first fuse program circuit is provided for each selection signal system of the redundant data line to configure the relief circuit.

Second fuse circuit (FR000 to FR0)
No. 07, FR100 to FR107) corresponding to some of the transfer gate means (T000 to T007, T100 to T107), the number of second fuse circuits is reduced, so that the chip occupation area by the fuse is further reduced. can do. At this time, the transfer gate means forming a pair with the second fuse circuit is made to correspond to the predecode signal of the lower address of the data line selecting address signal. Considering that defects usually tend to be concentrated in a specific part of the chip, even if the second fuse circuit is provided only in the lower address, the relief efficiency is prevented from being significantly reduced. It

As described above, it is possible to reduce the chip occupancy rate of the Hugh program circuit for replacing the defective portion with the redundant configuration and improve the efficiency of repairing the defect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a relief circuit included in a DRAM according to an embodiment of the present invention.

FIG. 2 is an overall block diagram of a DRAM according to an embodiment of the present invention.

3 is a circuit diagram showing a DTL1 portion of FIG. 2 as an example of a normal array portion of a memory mat.

FIG. 4 is a circuit diagram showing a DTL2 portion of FIG. 2 as an example of a redundant array portion of a memory mat.

5 is a block diagram focusing on a column system of the DRAM shown in FIG.

FIG. 6 is a circuit diagram showing a part of FIG. 1 in detail.

7 is an explanatory diagram showing a specific example of a fuse program in the DRAM of FIG.

FIG. 8 is a diagram illustrating each node A1 to A3 of FIG. 6 when the redundancy selection signal RS0 is set to a selection level such as a high level.
6 is a timing chart showing the state of FIG.

FIG. 9 is a block diagram showing another example of a relief circuit.

10 is a block diagram of an embodiment of a data processing system using the DRAM shown in FIG.

[Explanation of symbols]

1 DRAM MAT0 to MAT7 Memory mats DL00, DL00B Complementary data lines DL10, DL10B Redundant complementary data lines SH0 to SH7 Separation circuit CSWa to CSWd Column switch circuit TS0 to TS256 Column selection signal RS0, RS1 Redundancy column selection signal CDEC column decoder PDEC predecoder CP0 to CP19 Predecode signal RDD Relief circuit G1 to G3 Gate circuit GE Gate control signal FA0 to FA19 First fuse program circuit F20 Fuse T000 to T019, T100 to T119 Transfer gate circuit FR000 to FR019, FR100 to FR119 Second fuse Program circuit F21 Fuse LOG0, LOG1 Logic circuit M0 to M7 Mat selection signal 40 Data processing system 41 Central processing 50 system bus

Claims (4)

[Claims] 1. A plurality of memory mats, each of which has a matrix arrangement of a plurality of memory cells whose selection terminals are connected to word lines and whose data terminals are connected to data lines, are provided. In a semiconductor memory device in which a memory mat is selected and memory cells included in the selected memory mat are accessible from the outside, each of the memory mats has a normal data line to be a relief target when there is a defect. A repair circuit that includes a plurality of redundant data lines for replacing defective normal data lines, and that can specify a normal data line to be replaced by the redundant data line in units of memory mats; A redundant data line selection signal is generated in common for each memory mat based on the predecode signal of the address signal used to select the data line. A plurality of logic units to be used, and for each predecode signal of the address signal used to select the data line, which memory mat is used to replace the redundant data line is programmed and programmed for each memory mat. The first output is set to the first state in response to the selected state of the memory mat.
Fuse program circuit, a second fuse program circuit in which it is programmed which redundant data line selection signal reflects the state programmed in the first fuse program circuit, and a precharge to each of the logic means. First transfer gate means which is arranged in the transmission path of the decode signal and which is controlled by the second fuse program circuit so that the output of the first fuse program circuit is brought into the first state and selected by the second fuse program circuit so that information can be transmitted. A semiconductor memory device comprising: 2. A plurality of memory mats having a matrix arrangement of a plurality of memory cells whose select terminals are connected to word lines and whose data terminals are connected to data lines. In a semiconductor memory device in which a memory mat is selected and memory cells included in the selected memory mat are accessible from the outside, each of the memory mats has a normal data line to be a relief target when there is a defect. A repair circuit that includes a plurality of redundant data lines for replacing defective normal data lines, and that can specify a normal data line to be replaced by the redundant data line in units of memory mats; A redundant data line selection signal is generated in common for each memory mat based on the predecode signal of the address signal used to select the data line. A memory programmed and programmed in units of memory mats for each of the plurality of logic means and for which pre-decode signal of the address signal used for selecting the data line, which memory mat is used to replace the redundant data line. A first fuse program circuit whose output is brought to a first state in response to a state in which a mat is selected, and a state programmed in the first fuse program circuit is reflected in a selection signal of which redundant data line. And a second fuse program circuit for programming, and an output of the first fuse program circuit placed in a transmission path of a part of the predecode signal to each of the logic means and set to a first state. Two
Of the first fuse program circuit arranged in the transmission path of the remaining predecode signal to the respective logic means and the first transfer gate means controlled to be capable of transmitting information by being selected by the fuse program circuit of A semiconductor memory device, comprising: a second transfer gate means which is controlled so that information can be transmitted by setting an output to a first state. 3. A column address decoder for commonly forming a selection signal of a normal data line in the plurality of memory mats on the basis of the predecode signal to the plurality of memory mats, and an input of the column address decoder. Gate means is provided in the path, and the relief circuit supplies to the gate means a control signal for controlling all predecode signals supplied to the column address decoder to a non-selection level according to a state in which a redundant data line is selected. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises: 4. A semiconductor memory device according to claim 1, a data processing device for controlling access to the semiconductor memory device, and a bus connecting the semiconductor memory device and the data processing device. A data processing system comprising: