JPH0997902A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a short-circuit between a wiring and a connection wire due to misalignment in photoengraving by a method wherein a second wiring is formed via an interlayer insulation film on a first etching stopper film formed so as to cover an upper face and a side face of a first wiring, and a second etching stopper film is formed so as to cover an upper portion and a side face of the second wiring. SOLUTION: A first wiring 3 is formed on a semiconductor substrate 1 having a semiconductor area 1a being a source/drain area. An upper face and a side face of the first wiring 3 are formed so as to be covered with a first etching stopper film 5, and a second wiring 7 is formed via an interlayer insulation film 6 on the first etching stopper film 5. An upper portion and a side face of the second wiring 7 are covered to form a second etching stopper film 12. Thus, it is possible to prevent a short-circuit between a wiring and a contact 10a due to misalignment in photoengraving.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a DRAM (DYNA
MIC RANDOM ACCESS MEMORY) and other technologies related to fine processing of semiconductor devices.

[0002]

2. Description of the Related Art As semiconductor devices such as DRAMs have become highly integrated, miniaturization has progressed, and in the process of manufacturing semiconductor devices,
In particular, the misalignment of superposition in photoengraving causes a short circuit of the wiring, which is a problem. Therefore, a self-alignment process technology capable of forming elements in a self-aligned manner has been used. One example of the self-alignment process technique is the formation of a self-aligned contact, and this technique is used for the first wiring located at the lowermost layer among the wirings formed on the semiconductor substrate. Further, as an example of a document showing this technique, there is JP-A-4-14226.

[0003]

There are the following problems as problems of the conventional self-aligned contact technique. For example, FIG. 22 shows a cross section in the process of manufacturing a semiconductor device, and in FIG. 22, reference numeral 1 denotes a semiconductor region 1 on the surface which is, for example, a source / drain region.
a semiconductor substrate having a, 2 is a silicon oxide film formed on the surface of the semiconductor substrate 1, and an insulating film 3 is, for example, a gate oxide film, and 3 is, for example, a polycrystalline silicon layer 3a and a tungsten silicon layer laminated thereon. A first wiring 3b, which is a word line (gate electrode), 4 is a side wall made of an insulating film such as a silicon oxide film formed on the side surface of the first wiring 3, and 5a is a first wiring. 3, an etching stopper film made of a silicon nitride film laminated on the side wall 4 and the upper surface of the semiconductor substrate 1, 6 is a first interlayer insulating film made of a silicon oxide film laminated on the etching stopper film 5a, Reference numeral 7 denotes a second wiring composed of, for example, a polycrystalline silicon layer 7a and a tungsten silicon layer 7b laminated thereon, and 8 denotes a second wiring 7 and a first interlayer insulating film. Shows a second interlayer insulating film stacked thereon. From the upper surface of the second interlayer insulating film 8 to the semiconductor region 1a of the semiconductor substrate 1 between wirings in which at least two or more first wirings 3 and second wirings 7 are formed close to each other.
A resist pattern 9 serving as an etching mask is formed by photolithography when forming a contact hole that comes into contact with.

When a contact hole is formed near the first wiring 3 and the second wiring 7 so as to abut the semiconductor region 1a in the semiconductor substrate 1, as shown in FIG. Of the contact hole 10 by anisotropic etching up to the upper surface of the etching stopper film 5a covering the wiring 3 of FIG. 1, and then etching away the etching stopper film 5a exposed by the opening of the contact hole 10 to open the contact hole. Is completed.
In the step of opening the contact hole, during anisotropic etching up to the upper surface of the etching stopper film 5a,
When the resist pattern 9 serving as an etching mask cannot be formed at a predetermined position due to misalignment of photolithography, a contact hole is formed at an offset from the midpoint between two adjacent wirings as shown in FIG. Therefore, the second wiring 7 is partially removed by etching and is exposed. Therefore, when a contact is formed by embedding a conductive material in this contact hole and the connection with the wiring formed in the layer above the second wiring 7 is performed, the wiring formed in this upper layer becomes the second wiring 7. There was a problem that it caused a malfunction due to a short circuit. The present invention has been made in view of this problem, and is intended to prevent a short circuit between a wiring and a contact due to misalignment of superposition in photoengraving, thereby expanding a margin in a manufacturing process.

[0005]

A semiconductor device according to the present invention includes a first wiring formed on a semiconductor substrate, a first etching stopper film formed to cover at least the first wiring and side surfaces, and the first etching stopper film. The second etching stopper film is formed so as to cover the second wiring formed on the one etching stopper film via the interlayer insulating film, and at least the second wiring and the side surface.

In the semiconductor device according to the present invention, the first wiring formed on the semiconductor substrate, the first etching stopper film formed to cover at least the first wiring and the side surface, and the first etching stopper. A second wiring formed on the film via an interlayer insulating film; and a second etching stopper film formed on the second wiring, wherein the second etching stopper film is the second wiring. It has a wider surface in the horizontal direction than that of the second wiring and is formed so as to protrude from the side surface of the second wiring.

Further, according to the semiconductor device of the present invention, the first wiring formed on the semiconductor substrate, at least the first etching stopper film formed on the first wiring, and the first etching stopper film are formed. It has a second wiring formed via an interlayer insulating film and a second etching stopper film formed on the second wiring, and the first and second etching stopper films are respectively the first The second wiring has a larger surface in the horizontal direction than the second wiring, and is formed so as to protrude from the side surfaces of the first and second wirings.

Further, in the semiconductor device according to the present invention, in addition to the above means, the second etching stopper film is formed thicker than the first etching stopper film.

Further, in the semiconductor device according to the present invention, in addition to the above means, a TEOS layer is formed between the second etching stopper film and the second wiring.

In the semiconductor device according to the present invention, in addition to the above means, the second etching stopper film is made of polycrystalline silicon or amorphous silicon,
An insulating film having the same area as the second etching stopper film is formed between the second wiring and the second etching stopper film.

Further, in addition to the above-mentioned means, the semiconductor device according to the present invention has a first etching stopper film,
Either or both of the second etching stopper films are made of SiN or SiON.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a first wiring on a semiconductor substrate, a step of forming a first etching stopper film so as to cover the first wiring, A step of laminating a first interlayer insulating film on the entire surface of the semiconductor substrate on which the first etching stopper film is formed, and forming a second wiring on the first interlayer insulating film, on the second wiring. A step of forming a second etching stopper film having a surface wider in the horizontal direction than the second wiring and protruding from the side surface of the second wiring, Laminating a second interlayer insulating film on the entire surface, and opening a contact hole that abuts at least the upper surface of the second interlayer insulating film to the upper surface of the first etching stopper film or the upper surface of the semiconductor substrate. In the step of opening the contact hole etching mask formed on the second interlayer insulating film is characterized in that of the same material as the second etching stopper film.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. FIG. 1 is a diagram showing a part of a cross section of a semiconductor device according to the present invention, showing a cross sectional view cut in a direction perpendicular to a direction in which a first wiring 3 extends. FIG.
In the figure, 1 is a semiconductor substrate having a semiconductor region 1 a which becomes, for example, source / drain regions on its surface, 2 is a semiconductor substrate
An insulating film 3 made of a silicon oxide film formed on the surface of, for example, a gate oxide film is, for example, a polycrystalline silicon layer 3a and a tungsten silicon layer 3 laminated thereon.
The first wiring 4a which is made of b and serves as a word line (gate electrode) is a TEOS (TETR) layered on the first wiring 3.
AETHYL ORTHISILICATE) film, 4b is an insulating film 2, a first wiring 3, a sidewall made of an insulating film such as a silicon oxide film attached to the side surface of the TEOS film 4a, and 5 is a T
An etching stopper film made of a silicon nitride film laminated on the EOS film 4a and the sidewalls 4b and on the upper surface of the semiconductor substrate 1, and a first interlayer insulating film 6 made of a silicon oxide film laminated on the etching stopper film 5. , 7
Indicates a second wiring composed of, for example, a polycrystalline silicon layer 7a and a tungsten silicon layer 7b laminated thereon. Reference numeral 11a is a TEOS film laminated on the second wiring 7, 11b is a sidewall made of a silicon oxide film or the like formed on the second wiring 7 and on the side surface of the TEOS film 11a, and 12 is The second etching stopper film 10a made of a silicon nitride film formed so as to cover the TEOS film 11a and the sidewalls 11b is the upper wiring 13 laminated on the second interlayer insulating film 7 and the semiconductor in the semiconductor substrate 1. A contact made of a conductive material for electrically connecting to the region 1a, 8 indicates a second etching stopper film 12 and a second interlayer insulating film laminated on the first interlayer insulating film 6.

Next, the manufacturing process of the semiconductor device shown in FIG. 1 will be described with reference to FIGS. First, as shown in FIG. 2, a semiconductor substrate 1 having a semiconductor region 1a containing a predetermined impurity on one main surface is thermally oxidized to form an insulating film 2 made of a silicon oxide film on one main surface of the semiconductor substrate 1. Form. Next, the polycrystalline silicon film 3a and the tungsten silicon film 3
b and the TEOS film 4a are sequentially laminated using a technique such as CVD and sputtering, and a resist pattern in the shape of the first wiring 3 is formed by photolithography. After that, anisotropic etching is performed using this resist pattern as an etching mask to pattern the TEOS film 4a, and after the resist pattern is removed, the TEOS film 4a is used as an etching mask to form the tungsten silicon film 3b and the polycrystalline silicon film 3a. The insulating film 2 is sequentially etched.
Next, a silicon oxide film is laminated on the entire surface of the semiconductor substrate 1 by the CVD technique, and then anisotropic etching is performed to form the sidewall 4b made of an insulating film.

Thereafter, as shown in FIG. 3, the semiconductor substrate 1
A first etching stopper film 5 made of a silicon nitride film is laminated on the entire surface of the substrate by a CVD technique so as to have a predetermined thickness. Next, a silicon oxide film to be the first interlayer insulating film 6 is laminated. After that, a polycrystalline silicon film 7a to be the second wiring 7, a tungsten silicon film 7b, and T
The EOS films 11a are sequentially stacked. After that, a resist pattern in the shape of the second wiring 7 is formed by photolithography,
Using this resist pattern as an etching mask, TEO
Anisotropic etching is performed on the S film 11a. Next, T
Anisotropic etching is performed using the EOS film 11a as an etching mask to form the second wiring 7 in accordance with the dimensions. Next, an insulating film made of silicon dioxide is laminated on the entire surface by using the CVD technique, anisotropic etching is performed until the interlayer insulating film 6 is exposed, and the film is attached to the side surfaces of the TEOS film 4a and the second wiring 7. The sidewall 11b is formed. Next, as shown in FIG. 4, a silicon nitride film to be the second etching stopper film 12 is formed on the entire surface of the semiconductor substrate 1 so as to be a layer thicker than the first etching stopper film 5 already formed in the lower layer. Stack. Then, the silicon oxide film is partially removed, and the second etching stopper film 12 is formed so as to cover at least the TEOS film 11a and the sidewalls 11b.

Next, as shown in FIG. 5, a second interlayer insulating film 8 made of a silicon oxide film is laminated on the entire surface of the semiconductor substrate 1, and then an etching mask pattern of contact holes is further formed on the upper layer by photolithography. Form 15. The upper portion of the opening of the mask pattern 15 is opened so that a contact hole can be formed between the two first wirings 3 adjacent to each other and between the two second wirings 7 adjacent to each other. ing. However, when the mask pattern 15 is formed by photolithography, if misalignment occurs, as shown in FIG. 5, an opening portion closer to one of the wirings than the middle point of the two wirings is formed. Since the element is formed and the element to be formed is minute, this deviation causes the second wiring 7 or the first wiring 3 to partially overlap vertically below the end of the opening.

Using the mask pattern 15 as an etching mask, the first and second etching stopper films 5 and 12 are formed.
Until the first etching stopper film 5 is exposed under the etching condition in which the selection ratio of the silicon oxide film which is the constituent material of the first and second interlayer insulating films 6 and 8 is high with respect to the silicon nitride film which is the constituent material of Perform anisotropic etching. Next, as shown in FIG. 6, by changing the gas species and the partial pressure in the chamber of the etching apparatus, one of the semiconductor substrate 1 is etched under the etching condition that the etching selection ratio of the silicon nitride film to the silicon oxide film becomes high. Anisotropic etching is performed until the semiconductor region 1a formed on the main surface is exposed to form the contact hole 16. At this time, since the second etching stopper film 12 is formed in a layer thicker than the first etching stopper film 5, the second wiring is formed during the anisotropic etching for forming the contact hole 16. 7 is not exposed, and the contact 10a and the second wiring 7 are short-circuited even when the contact 10a is formed by burying a conductive material in the formed contact hole 16 by sputtering or using a CVD technique. There is no. Next, as shown in FIG. 7, by forming the upper wiring 13 on the second interlayer insulating film 8 and the contact 10a, the semiconductor device shown in FIG. 1 can be obtained.

In the semiconductor device shown in FIG. 1, a second etching stopper film 12 for covering at least the upper surface of the second wiring 7 is laminated on the first wiring 3 as an upper layer of the second wiring 7. By forming the etching stopper film 5 to be thicker than the first etching stopper film 5, the second wiring 7 which has been a problem in the conventional case
Therefore, it is possible to suppress the short circuit of the contact 10a.

Further, as shown in FIG. 7, after depositing the polycrystalline silicon film 7a and the tungsten silicon film 7b forming the first wiring 3, a first etch stopper film 17 made of a silicon nitride film is formed on the upper surface thereof. A resist pattern having the shape of the first wiring 3 is formed on top of the stacked layers, and anisotropic etching is performed using this resist pattern to etch the first etching stopper film 17 and the first wiring according to the dimensions. Form. Further, a silicon nitride film is entirely laminated and then anisotropically etched to form the sidewall 18 on the side surface of the first wiring 3. By thus covering the wiring with the silicon nitride film serving as the etching stopper film, it is possible to prevent the first wiring from being etched when the contact hole is formed.
Further, by forming the first etching stopper film 17 and the sidewall 18 which are protective films of the first wiring 3, it is possible to form a region where the silicon nitride film is not laminated between the adjacent wirings. Therefore, after stacking the second interlayer insulating film 8, it is possible to open the contact hole 16 so as to contact the semiconductor region 1a in the semiconductor substrate 1 by one-time anisotropic etching. In the manufacturing process of the semiconductor device having such a structure, the upper layer film is not laminated with the first etching stopper film 5 laminated on the entire surface. Therefore, the silicon nitride film removing process can be omitted when the contact hole is opened. The second etching stopper film 12 formed on the upper surface and the side surface of the second wiring 7 is hardly etched, and the thickness of the first and second etching stopper films is the same as in the semiconductor device shown in FIG. The contact 10a and the second wiring 7 will not be short-circuited even if they are not formed differently. The second etching stopper film 12 shown in FIG. 7 refers to a silicon nitride film formed on the upper surface and the side surface of the second wiring 7. The method for forming the second etching stopper film 12 is that the first etching stopper film 17 and the sidewall 18 are formed. It is similar to the forming method.

Embodiment 2. Further, as an example of a semiconductor device that suppresses a short circuit between a wiring formed on the semiconductor substrate 1 and a contact, there is a semiconductor device having a structure shown in FIG. The difference between this semiconductor device and the semiconductor device described in the first embodiment is the arrangement and shape of the second etching stopper film 20 formed as the protective film of the second wiring 7, and in the first embodiment, Although the etching stopper film and the sidewall made of the silicon nitride film were formed on the upper surface and the side surface of the second wiring 7, in the present embodiment,
A second etching stopper film 20 is formed on the upper surface of the second wiring 7 via the TEOS film 19 as a layer having a width wider than that of the second wiring 7. The second etching stopper film 20 and the TEOS film 19 are formed. Has a wider surface in the horizontal direction than the second wiring 7, and is formed so as to protrude from the side surface of the second wiring 7. In the semiconductor device having such a structure, after the second interlayer insulating film 8 is laminated, the second interlayer insulating film 8 is formed.
When a contact hole is formed so as to abut the semiconductor region 1a in the semiconductor substrate 1 from the upper surface of the substrate, the etching mask pattern is displaced, and the opening partly overlaps the upper part of the second wiring 7. Also, the second etching stopper film 20 and the TEOS film 19 serve as protective films, and the second interlayer insulating film 8a can be left between the side surface of the contact hole and the second wiring 7. Even after the contact 10a is formed, it is possible to suppress a short circuit between the contact 10a and the second wiring 7 and other wirings.

Next, a process of forming the semiconductor device shown in FIG. 8 will be described. First, as in the first embodiment, as shown in FIG. 2, the first wiring 3 and the TEOS film 4 on the upper surface of the first wiring 3 are formed.
Further, a side wall 4b made of an insulating film such as a silicon oxide film is formed on the side surface of the first wiring 3.
After that, a first etching stopper film 5 made of a silicon nitride film and a first interlayer insulating film 6 made of a silicon oxide film are sequentially laminated on the entire surface of the semiconductor substrate 1. Next, the polycrystalline silicon 7a to be the second wiring 7, the tungsten silicon 7b, the TEOS film 19, and the film to be the second etching stopper film 20 are laminated to a predetermined thickness. The second etching stopper film 20 laminated here is SiN,
By using an antireflection film (ARC) such as SiON or Si ₃ N _4, it is possible to improve the accuracy of photoengraving in the subsequent steps. Thereafter, as shown in FIG. 9, the resist pattern 14 is patterned according to the dimensions of the second etching stopper film 20, and anisotropic etching is performed using the resist pattern 14 as an etching mask.

Next, as shown in FIG. 10, the resist pattern 14 is removed, wet etching or isotropic dry etching is performed, and several hundred Å is etched from the side surface of the second wiring 7 toward the center. The width of the second wiring 7 is adjusted to a predetermined value. After that, the second interlayer insulating film 8 is laminated by using the CVD technique or the like, and the mask pattern 15 which becomes the etching mask pattern of the contact hole is further patterned. This mask pattern 15
11 is used to perform anisotropic etching under the condition that the selection ratio of the silicon oxide film to the silicon nitride film is high.
A contact hole 16 is obtained as shown in FIG. At this time, since the second etching stopper film 20 is formed so as to project to the side closer to the contact hole 16 than the second wiring 7, the side wall of the contact hole 16 and the side surface of the second wiring 7 are formed. The interlayer insulating film 8a is left in between, and the second wiring 7 is not damaged by etching or the like.

Next, as shown in FIG. 12, the first etching stopper film 5 between the bottom surface of the contact hole 16 and the semiconductor region 1a inside the semiconductor substrate 1 is selectively removed, and the surface of the semiconductor substrate 1 is removed. Expose. By the etching at this time, the second etching stopper film 20 on the second wiring 7 is also partially removed by etching when the formation position of the contact hole 16 is deviated, but the second etching stopper film 20 of the second etching stopper film 20 is removed. The lower TEOS film 19 functions as an etching stopper film and protects the second wiring 7. Thereafter, a conductive material such as polycrystalline silicon is embedded in the contact hole 16 to form a contact 10a, and the upper wiring 13 is patterned on the contact 10a, whereby the semiconductor device having the structure shown in FIG. 8 is completed.

In the semiconductor device shown in FIG. 8, it is possible to suppress a short circuit between the second wiring 7 and other wirings and the contact 10a even when misalignment occurs in the photolithography of the etching mask pattern of the contact hole. There is an effect that it becomes possible.

Further, when the first etching stopper film 5 is laminated on the entire surface of the semiconductor substrate 1 and another layer is further laminated on the upper layer, the second etching stopper film 20 is etched by the first etching stopper film 5. By using a material that is difficult to etch during removal, TEOS
It is possible to obtain a semiconductor device having a structure capable of suppressing a short circuit between the contact 10 a and the second wiring 7 without forming the film 19. When the first etching stopper film 5 and the second etching stopper film 20 are made of the same material, the second etching stopper film 20 is formed to be thicker than the first etching stopper film 5, so that the contact hole is formed. To provide a semiconductor device having a structure in which the second wiring 7 is protected by the second etching stopper film 20 even during etching and a short circuit between the contact 10a and the second wiring 7 can be suppressed without forming a TEOS film. Is possible.

Embodiment 3 FIG. Further, as a semiconductor device that suppresses at least a short circuit between the second wiring 7 and the contact 10a, there is a structure shown in FIG. This FIG.
In the semiconductor device shown in FIG. 1, the first and second etching stopper films 22 and 20 formed in the upper layers of the first wiring 3 and the second wiring 7, respectively, are better than the first and second wirings 3 and 7. The first and second etching stopper films 22 and 20 are formed in a state where both ends of the layers are formed to have a width wider than the first and second wirings 3 and 7. There is. Further, a TEOS film 21 is laminated between the first wiring 3 and the first etching stopper film 22, and a TEOS film 19 is laminated between the second wiring 7 and the second etching stopper film 20. .

The difference from the structure of the semiconductor device of the second embodiment is the shape of the first etching stopper film formed on the first wiring 3, and in the second embodiment, as shown in FIG. On the upper surface and the side surface of the first wiring 3,
Although the first etching stopper film 5 is laminated with a predetermined thickness via the S film 4a and the sidewall 4b, the first etching stopper film 22 in this embodiment is the same as that of the second embodiment. The second etching stopper film 20 has the same shape as that of the second etching stopper film 20 and is composed of a layer extending in the horizontal direction.
It is about 00Å, and is formed wide toward the outside. In addition, the first etching stopper film 22 and the second etching stopper film 20 are formed in the same shape.

The method of manufacturing the semiconductor device shown in FIG.
An insulating film 2, a polycrystalline silicon film 3a containing a predetermined impurity, and a film made of a low resistance material such as a tungsten silicon film 3b are sequentially laminated on a semiconductor substrate 1, and then TEO is performed.
An S film 21 and a first etching stopper film 22 made of a silicon nitride film are laminated. Next, the resist pattern is patterned into the shape of the second etching stopper film 22,
Using this pattern as an etching mask, anisotropic etching is performed until the surface of the semiconductor substrate 1 is exposed. Next, the etching mask is removed, and then wet etching or dry isotropic etching is performed to etch the side surface of the first wiring 3 formed to have the same dimensions as the first etching stopper film 22. One etching stopper film 22 and TEOS formed thereunder
A step of several hundred Å is formed in the width of the film 21 and the width of the first wiring 3.

Thereafter, an insulating film such as a silicon oxide film is laminated by using the CVD technique to form a first interlayer insulating film 6,
After that, the second wiring 7, the TEOS film 19 and the second etching stopper film 20 are respectively formed through the same processing steps as those of the second embodiment, and the second interlayer insulating film 8 is laminated. Next, a resist pattern that serves as a mask pattern for contact hole etching is patterned, and then anisotropic etching is performed to form a contact hole that contacts the semiconductor region 1a in the semiconductor substrate 1. At this time, the first and second etching stopper films 22 and 20 are formed on the first and second wirings 3 and 7 even if the contact hole etching mask pattern is formed in a shifted position. Therefore, even when the contact hole is formed, the first or second wiring 3,
Even if the conductive material is buried in the contact hole to form the contact 10a, the short circuit between the contact 10a and the first or second wiring 3, 7 can be suppressed. It is possible. Next, by burying a conductive material in the contact hole, forming the contact 10a, and forming the upper wiring 13 on the contact 10a, the semiconductor device having the structure of FIG. 13 can be obtained.

In the semiconductor device shown in FIG. 13,
As already described, there is an effect that a short circuit between the first and second wirings 3 and 7 and the contact 10a can be suppressed. Further, unlike the first and second embodiments, since the first etching stopper film 5 is not stacked in the contact hole formation region, the contact hole can be opened by one anisotropic etching. The number of steps can be simplified.

Furthermore, in the structure of the semiconductor device shown in FIG. 13, the TEOS films 21 and 19 which are the upper layers of the first and second wirings 3 and 7.
It is also possible to form a semiconductor device having a structure capable of suppressing a short circuit between the wiring and the contact by directly forming the first and second etching stopper films 22 and 20 on the wiring without forming the wiring.

Embodiment 4 FIG. Next, a fourth embodiment of the present invention will be described. In this embodiment, FIG.
As shown in FIG. 5, a BPSG (BORO-PHOSPHO SILICATE GLASS) film or a T-layer is formed on the second wiring 7 of the semiconductor device as a protective film for the second wiring 7 by a CVD technique.
It is characterized in that an EOS film 23, a stopper film 24 for a silicon oxide film made of polycrystalline silicon, amorphous silicon, or the like is formed. In addition, reference numeral 25 indicates a thermal oxide film, and other reference numerals are the same as those already used. The reference numerals indicate the same or corresponding parts.

The method of forming the semiconductor device shown in FIG.
The method is partly the same as the method shown in the first and second embodiments already described, and first, similarly to the case shown in the first and second embodiments, the first wiring 3 and the first etching stopper film 5, the first The inter-layer insulating film 6 is formed. Next, as shown in FIG.
After stacking the polycrystalline silicon film 7a and the tungsten silicon film 7b to be the second wiring 7, a BPSG film or TEO which is a silicon oxide film to be a protective film for the second wiring 7 is further formed.
The S film 23 is stacked to a thickness of 500 to 2000 Å by using the CVD technique, and then a polycrystalline silicon film or an amorphous silicon film to be the stopper 24 for the silicon oxide film is stacked. After that, a resist pattern 26 is formed on a region where the BPSG film or the TEOS film 23 and the silicon oxide film stopper 24 are left as a protective film for the second wiring 7.

Next, reverse taper type etching is performed by using the resist pattern 26 as an etching mask, and the second wiring 7 and the BPSG film or TEOS film 23 serving as a protective film for the second wiring 7 and the silicon oxide film stopper 24. Is formed as shown in FIG. 16, and the resist pattern 26 is removed. The difference between the dimension of the narrowest part of the second wiring 7 formed at this time and the dimension of the widest part of the protection film of the wiring 7 against the silicon oxide film stopper 24 is
At least 100Å or more.

Next, a silicon dioxide film is laminated by the CVD technique to form a second interlayer insulating film 8. afterwards,
As shown in FIG. 17, a resist pattern 27 serving as an etching mask at the time of forming a contact hole is formed, and then anisotropic etching is performed to form the first and second interlayer insulating films 6.
A part of 8 is removed to form a contact hole 28.
After that, the first etching stopper film 5 located on the bottom surface of the contact hole 28 is selectively removed to expose the semiconductor region 1a on one main surface of the semiconductor substrate 1 and the resist pattern 27 is removed.

After that, as shown in FIG. 18, the contact formed by burying the conductive material in the contact hole 28 and the silicon oxide film stopper 24 made of the conductive material are prevented from being electrically connected. Because again
In order to improve the insulating property between the second wiring 7 and the contact 10a, the entire surface of the semiconductor device is thermally oxidized to form the thermal oxide film 25.

Then, as shown in FIG. 19, anisotropic etching is performed on the entire surface to remove the thermal oxide film 25 formed on the bottom surface of the contact hole 28 and the upper surface of the second interlayer insulating film 8 by etching. Next, as shown in FIG. 20, a conductive material is buried in the contact hole 28 by using the CVD technique or the sputtering technique to form the contact 10a. Then, after performing processing such as flattening the upper surface of the second interlayer insulating film 8, the third wiring 13 is patterned to obtain the semiconductor device having the structure shown in FIG.

In the semiconductor device thus formed, a BPSG film or TEO film in which a silicon oxide film contains boron or phosphorus is formed on the second wiring 7 as a wiring protection film.
By forming the S film 23 and the stopper film 24 against the silicon oxide film, the second wiring 7 is etched even if the resist pattern used as the etching mask in forming the contact hole is deviated from a predetermined position. Therefore, the wiring resistance or the like is not affected. In addition, it is possible to improve the insulation margin between the contact 10a and the second wiring 7 by thermally oxidizing the surface in the contact hole.

Embodiment 5 Next, a fifth embodiment will be described. The difference between the present embodiment and the fourth embodiment lies in the manufacturing process, and there is no difference in the structure of the semiconductor device finally obtained. FIG. 21 is a diagram showing the formation of contact holes. Reference numeral 29 is a mask pattern made of the same material as the stopper film for silicon oxide film 24. When the stopper film for silicon oxide film 24 is made of polycrystalline silicon, many mask patterns are formed. It shows a crystalline silicon film.

When the anti-silicon oxide film stopper 24 and the contact hole mask pattern 29 are made of the same polycrystalline silicon, the gas system used for anisotropic etching in forming the contact hole is, for example, A process for obtaining a high selection ratio for polycrystalline silicon is applied like a system in which CO is added to a fluorocarbon gas such as CHF ₃ . As described above,
When the mask pattern 29 is formed using a polycrystalline silicon film and the CHF ₃ + CO process is applied,
The selection ratio with respect to the silicon oxide film forming the second interlayer insulating films 6 and 8 can be 20 or more. Further, the stopper 2 for the silicon oxide film is more effective than the case where the mask pattern for the contact hole etching is simply formed by the resist.
Even if 4 is formed thin, sufficient etching resistance can be obtained. Further, since the stopper film 24 for the silicon oxide film can be formed thin, the step difference on the surface of the semiconductor device can be reduced, and the formation of the upper layer wiring and the like can be facilitated. Further, it is possible to perform etching with better dimensional accuracy than when using a mask pattern made of a resist, and after using a film made of polycrystalline silicon as an etching stopper film, without removing the stopper film, It can also be used as an electrode of a capacitor or the like.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a diagram showing an embodiment of the present invention.

FIG. 5 is a diagram showing an embodiment of the present invention.

FIG. 6 is a diagram showing an embodiment of the present invention.

FIG. 7 is a diagram showing an embodiment of the present invention.

FIG. 8 is a diagram showing an embodiment of the present invention.

FIG. 9 is a diagram showing an embodiment of the present invention.

FIG. 10 is a diagram showing an embodiment of the present invention.

FIG. 11 is a diagram showing an embodiment of the present invention.

FIG. 12 is a diagram showing an embodiment of the present invention.

FIG. 13 is a diagram showing an embodiment of the present invention.

FIG. 14 is a diagram showing an embodiment of the present invention.

FIG. 15 is a diagram showing an embodiment of the present invention.

FIG. 16 is a diagram showing an embodiment of the present invention.

FIG. 17 is a diagram showing an embodiment of the present invention.

FIG. 18 is a diagram showing an embodiment of the present invention.

FIG. 19 is a diagram showing an embodiment of the present invention.

FIG. 20 is a diagram showing one embodiment of the present invention.

FIG. 21 is a diagram showing one embodiment of the present invention.

FIG. 22 is a diagram showing a conventional technique.

FIG. 23 is a diagram showing a conventional technique.

[Explanation of symbols]

1. Semiconductor substrate 2. Insulating film 3. First wiring 4a, 11a.
TEOS films 4b and 11b. Sidewalls 5. First etching stopper film 6. First interlayer insulating film 7. Second wiring 8. Second interlayer insulating film 9. Resist pattern 10a. Contact 12. Second Etching stopper film 13. Upper layer wiring

Claims (8)

[Claims] 1. A first wiring formed on a semiconductor substrate, a first etching stopper film formed to cover at least an upper surface and a side surface of the first wiring, and an interlayer insulating film on the first etching stopper film. A second etching stopper film is formed so as to cover at least the second wiring formed over the second wiring and the side surface of the second wiring. 2. A first wiring formed on a semiconductor substrate, a first etching stopper film formed so as to cover at least an upper surface and a side surface of the first wiring, and an interlayer insulating film on the first etching stopper film. And a second etching stopper film formed on the second wiring, and the second etching stopper film is wider in the horizontal direction than the second wiring. A semiconductor device having a surface and protruding from a side surface of the second wiring. 3. A first wiring formed on a semiconductor substrate, a first etching stopper film formed on at least the first wiring, and formed on the first etching stopper film via an interlayer insulating film. The second wiring formed, the second etching stopper film formed on the second wiring,
The first and second etching stopper films each have a surface wider in the horizontal direction than the first and second wirings, and are formed so as to project from the side surfaces of the first and second wirings. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the second etching stopper film is formed thicker than the first etching stopper film. 5. The semiconductor device according to claim 1, further comprising a TEOS layer formed between the second etching stopper film and the second wiring. 6. The second etching stopper film is made of polycrystalline silicon or amorphous silicon, and an insulating film having the same area as the second etching stopper film is formed between the second wiring and the second etching stopper film. The semiconductor device according to claim 2, wherein the semiconductor device is provided. 7. One or both of the first etching stopper film and the second etching stopper film is S.
7. The semiconductor device according to claim 1, wherein the semiconductor device is made of iN or SiON. 8. A step of forming a first wiring on a semiconductor substrate, a step of forming a first etching stopper film so as to cover the first wiring, and a step of forming the first etching stopper film. A step of stacking a first interlayer insulating film on the entire surface of a semiconductor substrate and forming a second wiring on the first interlayer insulating film, in a horizontal direction above the second wiring on the second wiring. A step of forming a second etching stopper film having a wide surface on the side and protruding from the side surface of the second wiring,
The second interlayer insulating film is laminated on the entire surface of the semiconductor substrate on which the second etching stopper film is formed, and at least contacts the upper surface of the second interlayer insulating film to the upper surface of the first etching stopper film or the upper surface of the semiconductor substrate. Manufacturing a semiconductor device including a step of opening a contact hole, wherein an etching mask formed on the second interlayer insulating film in the step of opening the contact hole is made of the same material as the second etching stopper film. Method.