JPH10104576A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

(57) [Problem] To provide a TFT array configuration in which gate line inversion drive and interlace drive can be used together without deteriorating image quality. SOLUTION: In a TFT array for an active matrix liquid crystal display device in which a TFT and a pixel electrode are provided for each pixel, a pixel electrode connected via a TFT controlled by each gate line is fixed to the gate line. And a liquid crystal display device having means for operating the TFT array by the gate line inversion driving method. Further, a liquid crystal display device for driving the TFT array by an interlace driving method, and a data line driving circuit having a memory for temporarily storing display data in accordance with the fixed period in a data line driving circuit for driving a liquid crystal panel. And a liquid crystal display device having the same.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a structure of a TFT array of an active matrix type liquid crystal display device and a driving method thereof.

[0002]

2. Description of the Related Art Recently, a liquid crystal display device has been used as a display device of a personal computer, a word processor and the like because of its features such as being thin and lightweight, being capable of being driven at a low voltage, and being easily colorized. Have been. Among them, a so-called active matrix type liquid crystal display device employing a thin film transistor (hereinafter abbreviated as “TFT”) as a switching element for each pixel, the deterioration of contrast, response and the like even when the number of pixels is increased. Since it is hard to occur and halftone display is possible, full color TV,
It is most suitable as a display device for OA equipment.

This active matrix type liquid crystal display device has a structure in which a liquid crystal layer is sandwiched between an array substrate (active matrix substrate) and two flat glass substrates called a counter substrate. A color filter corresponding to each pixel and a transparent electrode (counter electrode) are formed on the counter substrate. The array substrate is provided with pixel electrodes composed of transparent electrodes arranged in a matrix and TFTs each having a source electrode connected to each pixel electrode. T
The gate electrode of the FT is connected to an address line wired in the X direction on the array substrate, and the drain electrode is connected to a data line wired in a direction perpendicular to the address line.

In the liquid crystal display device configured as described above,
By applying an address signal and a data signal to the address line and the data line at predetermined timing, a voltage corresponding to the display of each pixel can be applied to each pixel electrode. The orientation of the liquid crystal layer, that is, the light transmittance, can be controlled by the potential difference between the counter electrode and the pixel electrode, thereby enabling arbitrary display. Details of the principle of such a liquid crystal display are described in T.W. P. Brody et al. (IEEE Tra
ns. on Electron. Devices, Vol. ED-20, Nov., 1973,
pp.995-1001).

FIG. 4 is a configuration diagram showing a schematic configuration of a conventional active matrix type liquid crystal display device. In FIG. 4, pixel electrodes 6 corresponding to each pixel are arranged in a matrix of m rows × n columns, and gate lines G1... Data lines D1, D2,..., Dn are provided corresponding to the electrodes. The TFTs 5, 5,... Are arranged at the intersections of the gate lines and the data lines, and are connected to the pixel electrodes 6, 6,. That is, each TFT 5 has its source connected to the corresponding pixel electrode 6, its drain connected to the corresponding data line Di (1 ≦ i ≦ n), and its gate connected to the corresponding gate line Gj (1 ≦ j). ≦ m).

The data lines D1, D2... Dn are controlled by a data line driving circuit 101, and the gate lines G1.
m is controlled by the gate line driving circuit 102. That is, the video signal is transmitted from the data line driving circuit 1 to each data line D
Via i, it is supplied to the drain of each TFT 5. On the other hand, a drive signal for switching each TFT is transmitted from the gate line drive circuit 2 via each gate line Gj to each TFT.
5 is supplied. Then, the TFT whose gate is turned on
5, a video signal is supplied from the drain to the pixel electrode 6 connected to the source via the gate, and the counter electrode 8
(Com) to the liquid crystal layer 7.

In order to apply a predetermined video signal voltage to each of the pixel electrodes 6, the pixel electrodes 6 are driven by a line sequential method. However, at this time, because of the physical properties of the liquid crystal layer 7,
In order to ensure the reliability, it is necessary to drive the liquid crystal layer 7 with an alternating current. That is, for example, each pixel can transmit light when no voltage is applied to the liquid crystal layer 7, and can block light when a positive or negative voltage having a predetermined absolute value is applied. Therefore, AC driving can be performed by inverting the polarity of the video signal voltage for each field. By performing such AC driving, electrical deterioration of the liquid crystal material can be suppressed, and the life can be extended.

However, with the AC drive, flicker,
That is, the screen flickers. In order to minimize the flicker, a driving method such as a data line inversion driving method or a gate line inversion driving method is required. Among these driving methods, the gate line inversion driving method is advantageous in terms of cost because a low-voltage IC can be used for the data line driving circuit, and is used in many liquid crystal display devices. I have.

Therefore, the gate line inversion driving method will be described below.

FIG. 5 is a timing chart showing the drive timing of the gate line inversion driving method. First, as shown in FIG. 1A, the gate lines G1, G2, G3,.
··· is a selection pulse Vgh for sequentially turning on the TFT
Is applied. In synchronization with this, Vdh and Vdl are alternately applied to the data lines D1, D2, D3,... As shown in FIG. That is,
When G1 is on, Vdh (the polarity of the liquid crystal application voltage is positive) is applied to D1, and when G2 is on, Vdl (the polarity of the liquid crystal application voltage is negative) is applied to D2. Is done. Further, in synchronization with this, the common electrode Vcom and Vcom are applied to the counter electrode com as shown in FIG.
h are applied alternately.

As a result, as shown in FIG. 1D, the voltage applied to the liquid crystal layer is VLCh = Vdh-Vcoml (> 0) for the pixels in the row corresponding to the gate line G1.
VLCl in the pixels in the row corresponding to the gate line G2.
= Vdl-Vcomh (<0). That is, the voltage amplitude between the positive voltage VLCh and the negative voltage VLCl applied to the liquid crystal layer is equal to the data line signal voltage Vd and the common electrode voltage Vc.
om. Therefore, the common electrode voltage Vc
If the amplitude of om is set large, the data line signal voltage Vd
, A sufficient voltage can be applied to the liquid crystal layer. That is, the IC used for the data line driving circuit 1
Can be displayed even if is a low output voltage type.

The +/- symbols shown on the display electrode 6 in FIG.
It indicates the polarity of the voltage applied to the liquid crystal layer. In the above-described gate line inversion driving method, the polarity is inverted to +/- every other gate line as shown in the figure. Thereby, the normal 60Hz
It is possible to suppress flicker during non-interlace driving. Note that the voltage polarity of each pixel electrode shown in FIG. 4 is inverted in the next field so that the liquid crystal layer is driven by AC.

As described above, the gate line inversion driving method is employed for suppressing the flicker on the screen while performing the AC driving to ensure the reliability of the liquid crystal layer.

On the other hand, from another viewpoint, there is an interlace driving method as a driving method for reducing the power consumption of the liquid crystal display device. Hereinafter, this interlace driving method will be described.

FIG. 6 is an explanatory diagram for explaining a 3: 1 interlace driving method. The figure shows gate lines G1 to G
8 represents the polarity of the video signal voltage for each field. In the figure, +/- symbols surrounded by a circle indicate that a video signal (+ polarity /-polarity) is written to the pixel electrode on each gate line. Also,
A +/- symbol without a circle indicates a state in which the video signal is held. For example, the gate line G1 is connected to the write state at field numbers 1, 4, 7, 10,.... AC driving is realized by alternately writing the + voltage and the − voltage for each field. Also. The gate line selected by field number 1 is G
1, G4, G7,... Then, a positive voltage and a negative voltage are alternately written for each gate line. That is,
In each field, the number of gate lines to which video signals are written is 1/3 of all gate lines.

In such an interlace driving method, only one-third pixels are written for each field.
The amount of data to be processed by the peripheral drive circuit can be reduced to 1/3. Therefore, there is an advantage that the power consumption of the peripheral driving circuit can be significantly reduced.

[0017]

However, when such an interlace driving method is simply combined with the above-described gate line inversion driving method, interference fringes may be visually recognized on a display screen. The mechanism of the generation of this interference fringe will be specifically described with reference to FIG.

FIG. 6 shows the polarity of the signal voltage for each gate line as described above. The signal voltage is maintained for a certain period of time after being written for each polarity. However, in reality, the signal voltage gradually decreases while being held due to signal leakage. Then, when the polarity is inverted and the next signal voltage is written, that is, when the polarity is inverted from + to-or from-to + in the drawing, the light transmittance of the liquid crystal layer changes. That is, a new video signal voltage is supplied to each pixel on the gate line, and instantaneously changes to a contrast corresponding to the voltage. Then, such a change in the line-shaped contrast for each gate line may be visually recognized as a disturbing stripe on a screen according to the scanning frequency of the gate line.

For example, in FIG. 6, broken lines shown in oblique directions are obtained by connecting the instants at which the signal voltages of the respective gate lines are written at a constant period. That is, the broken line 111
“a” is a connection of the moment when the signal voltage is inverted from − to +. The broken line 111b indicates that the signal voltage is from + to-.
It is a connection of the moments of inversion. When these lines are traced along the field, that is, as time progresses, it can be seen that signal writing occurs by moving three lines upward in the figure every three fields. That is, a change in the line-shaped contrast accompanying the writing of a signal may occur one after another on the display screen as the field progresses, and the frequency may be reduced to a level that can be visually recognized. In such a case, interference fringes appear on the screen. In general, it is considered that such interference fringes can be visually recognized at a frequency lower than 60 Hz in consideration of the afterimage effect of the human eye.

The broken lines 111a and 111b shown in FIG.
This is an example of a cycle in which such interference fringes occur. And
In the drawing, there are also interference fringes having other periods.

As described above, when the interlace driving method, which is advantageous in reducing power consumption, is combined with the gate line inversion driving method, there is a problem that image quality is deteriorated. Therefore, there is a problem that it is difficult to provide a low-cost liquid crystal display device with low power consumption.

The present invention has been made in view of the above circumstances. That is, an object of the present invention is to provide a liquid crystal display device capable of realizing gate line inversion driving by a low-voltage IC and interlace driving capable of low power consumption driving without deteriorating image quality such as interference fringes, and a driving method thereof. Is to provide.

[0023]

That is, a liquid crystal display device according to the present invention has a plurality of rows and columns of pixel electrodes arranged in a matrix in an image display area, and is connected to the pixel electrodes to supply a video signal. A switching element that performs switching of the image display area, a plurality of gate lines that are wired in parallel with the row direction of the image display area, and a plurality of gate lines that control the switching operation of the switching element, and that are wired substantially orthogonal to the gate line. An array substrate having a plurality of data lines for supplying the video signal to the switching element, a counter substrate having electrodes formed to face the array substrate, and between the array substrate and the counter substrate. A liquid crystal display device having a liquid crystal layer sandwiched between the pixel electrodes in two adjacent rows arranged in the image display region in a wiring direction of the gate line. Among them, the switching operation of the switching elements connected to the pixel electrodes alternately positioned at a certain number of pixels in one row and the other row is controlled by the same gate line. It is configured as something.

A data line scanning circuit for supplying the video signal sequentially input for each row of the image display area to each of the data lines; and a memory for storing the video signal. According to the arrangement state of the pixel electrodes connected to the switching elements, the switching of which is controlled by the gate line, by temporarily storing the video signal in the memory, the video signal sequentially input for each row It is configured to include a data line driving circuit adapted to supply a corresponding pixel electrode in the image display area.

In the driving method of the liquid crystal display device according to the present invention, the signal for controlling the switching element is sequentially supplied to each of the plurality of gate lines of the liquid crystal display device, and the control signal for controlling the switching element is supplied. When supplying the video signal to the switching element controlled by the gate line supplied with the signal via the data line, the voltage polarity of the video signal is inverted for each of the plurality of gate lines. Thereby, a predetermined image is displayed.

Further, the writing of the video signal to the pixel electrode of the liquid crystal display device is performed by an interlace driving method with an interlace ratio n: 1 represented by using a predetermined number n (n ≧ 2). It is configured as something.

Further, the predetermined number n is an even number of 4 or more, and in the same field, the voltage polarity of the video signal is alternately inverted for each gate line to which the video signal is written, so that the predetermined number i (i ≧ 0) ) And n,
From the (1 + in) th field to the (i + 1) nth field, the voltage polarity of the video signal corresponding to the gate line to be written at the beginning of the field is alternately inverted for each field, so that the (i + 1) nth field and the (i + 1) nth field [(I
+1) n + 1] fields, the voltage polarity of the video signal corresponding to the gate line written at the beginning of each field is the same.

[0028]

According to the present invention, a TFT for driving a liquid crystal and a pixel electrode are arranged so as to be scattered up and down in a plane with a gate line interposed therebetween, so that occurrence of interference fringes cannot be visually recognized. Can be provided.
Then, the gate line inversion driving method and the interlace driving method can be combined without deteriorating the display quality. That is, in the liquid crystal display device according to the present invention, when rewriting the video signal for each gate line, rewriting is performed not in one continuous row but in two rows. Therefore, the change in contrast at the time of rewriting the video signal is weakened, and interference fringes are suppressed. In the present invention, in order to realize such an arrangement of the pixel electrodes, the pixel electrodes controlled from the gate lines via the TFTs are arranged at positions opposite to each other with respect to the gate lines as an axis.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A and 1B are schematic diagrams showing the arrangement of the liquid crystal display device according to the present invention on an array substrate, and the potential of a pixel electrode at the time of 4: 1 interlace driving. It is a conceptual diagram. In the array substrate shown in FIG. 3A, each pixel is composed of TFTs 5a, 5b,.
The pixel electrodes 6a, 6b,... The data lines D1, D2,... Are connected to the data line driving circuit 1, and the gate lines G1, G2,. Here, each TFT and pixel electrode are connected to gate lines G1, G2,... As shown in FIG.
.. Are arranged alternately on the lower side and the upper side for each pixel with the axis as the axis. Therefore, when the gate line inversion driving method is performed in such a TFT array, the polarity of the liquid crystal driving voltage of each pixel is such that the pixels of positive polarity and negative polarity are arranged in the gate line direction as shown in FIG. They will be arranged alternately. Such an arrangement of the TFTs and the pixel electrodes can be manufactured only by changing a photomask in a photolithography process without changing a conventional manufacturing process.

By arranging the TFTs and the pixel electrodes in this way, the spatial frequency formed by the pixels to which writing is performed simultaneously for each gate line is much higher than in the past. That is, in the conventional configuration as shown in FIG. 4, one row of pixel electrodes along the gate line is written simultaneously. Therefore, the period of the arrangement of the pixels in one continuous row is equal to the horizontal width of the display screen and can be easily recognized. Also, it can be said that the spatial frequency of the array is equal to zero.

However, in the configuration shown in FIG. 1A, pixels to which writing is performed simultaneously for each gate line are alternately arranged above and below the gate line. That is, these pixels are alternately arranged in pixel units, and the arrangement cycle cannot be visually recognized under normal conditions. In other words, it can be seen that the spatial frequency has become higher and has exceeded the spatial resolution of the human eye and has become lower than the visual limit.

As a result, when the gate line inversion driving method including the AC driving method is performed, even if the polarity is inverted for each gate line, a change in the contrast of the entire line is not visually recognized. Therefore, even if the interlace driving method with a high ratio is combined, the interference fringes as described with reference to FIG.

For example, FIG. 1B shows the potential of the pixel electrodes from the gate lines G to G9 in a certain data line at the time of 4: 1 interlace driving. The circle symbol in the figure is T
The timing at which the display signal voltage is written to the pixel electrode via the FT is shown. The visibility of the interference fringes is spatially improved as compared with the rewriting of each odd field of 3: 1 shown in FIG. 6, and the polarities of the pixel electrode potentials arranged in the same row according to the present invention are adjacent to each other in the same row. Since the image is inverted for each pixel, no interference fringe is visually recognized.

As described above, in the liquid crystal display device according to the present invention, unlike the related art, the situation in which pixels of the same polarity are continuously arranged on one line in the gate line direction is eliminated, and the visibility of interference fringes is greatly reduced. Will be done. In particular, if the arrangement is made such that the spatial frequency of the arrangement of the positive electrode and the negative electrode in the gate line direction is high, it is possible to make the interference fringes completely invisible. Accordingly, a gate line inversion driving method that can use a low-voltage driving IC that can reduce the price, and an interlace driving method that can reduce the power consumption,
This can be performed simultaneously without deteriorating the image quality. Moreover, this TFT array has a feature that can be realized without adding a special manufacturing process.

Next, a data line driving circuit of the liquid crystal display device will be described.

FIG. 2 is a schematic diagram showing an example of a data line driving circuit for the TFT array shown in FIG. In FIG. 1, pixel electrodes P (i, j) (where i, j indicate pixel coordinates, i corresponds to the gate line direction, and j corresponds to the data line direction, respectively) and P (i + 1, j + 1)
However, the liquid crystal drive voltage is simultaneously written by the gate line Gi + 1. That is, the gate line simultaneously controls the pixels in the upper and lower two rows. However, usually, the video data supplied from the outside to the liquid crystal display device often includes a video signal of each pixel continuously arranged for each row. Therefore, when such a video signal is supplied to the TFT array having the configuration shown in FIG. 1, the video signal is temporarily stored in the memory for every other data line, and the video signal is supplied to the next gate line. At the same time, it is necessary to supply the video signal stored from the memory at the same time. In the data line driving circuit shown in FIG. 2, latch circuits L1, L2A,... Are arranged as such memories.

The operation of the circuit configuration shown in FIG. That is, the video signal of the i-th row from the data line scanning circuit 11 is applied to each of the data lines D1, D2,.
.., The latch circuits L2B and L4B in FIG. 3 store the video data of the (i-1) th row. Then, the video signal of each pixel on the i-th row newly supplied from the data line driving circuit 11 is stored in the latch circuits L1, L2A, L3, L4A,. When the i-th gate line (not shown) is turned on, each of the latch circuits L1, L2B,
The video signals stored in L3, L4B, L5,... Are converted into analog signals by D / A converters 14, 14,.
Is supplied to each TFT connected to the i-th gate line. That is, (i, 1), (i-1, 2),
A video signal is supplied to each pixel of (i, 3), (i-1, 4), (i, 5),.

Subsequently, the latch circuits L2A, L4A,.
The video signals stored in the latch circuits L
2B, L4B,... And stored again.

Next, from the data line scanning circuit 11, (i +
1) The video signal of the row is applied to each of the latch circuits L1, L2A, L
3, L4A, L5,... And stored. When the (i + 1) -th gate line (not shown) is turned on, the latch circuits L1, L2B, L3, L4B, L
, Are supplied to the respective pixels connected to the gate lines via D / A converters 14, 14,.... That is, when the (i + 1) th gate line is turned on, (i + 1, 1),
(I, 2), (i + 1, 3), (i, 4), (i + 1,
5), a video signal is supplied to each pixel.

More specifically, the pixels on the i-th row of the screen will be described. Each pixel of (i, 1), (i, 3), (i, 5) is turned on when the i-th gate line is turned on. Video signals are respectively written. Also, (i, 2), (i,
In each pixel of 4), a video signal is written when the (i + 1) th gate line is turned on.

As described above, in the data line driving circuit according to the present invention, the video signal sent from the outside for each row is supplied to the pixels on each gate line with a delay according to the arrangement of the TFTs. Can be. Thus, a desired image can be displayed even in the TFT array shown in FIG. Next, a modified example of the liquid crystal display device according to the present invention will be described. FIG. 3 is a schematic configuration diagram illustrating a modification of the liquid crystal display device according to the present invention.

Also in the liquid crystal display device shown in FIG. 3, data lines D1, D2,... Connected to the data line drive circuit 31 and gate line drive circuit 32 are connected to the data line drive circuit 31 in the same manner as shown in FIG. , And connected gate lines G1, G2,... In the vicinity of these intersections, TFTs 5A, 5A,... Or 5B, 5B,.
・ It has. The pixel electrodes 6A, 6A,... Or 6B, 6B,. The pixel TFTs are connected alternately in a three-pixel cycle along the gate line direction. For example, the gate line G3 will be described. From the first column to the third column, the TFTs 5A, 5A,
A and 5A are connected. From the fourth column to the sixth column, the upper side of the gate line, that is, the second row of TFTs 5
B, 5B and 5B are connected. Thus, the upper and lower pixel TFTs are alternately connected to each gate line for every three pixels. This TFT array is suitable for a vertical stripe type color liquid crystal display device. That is, each pixel corresponding to the three primary colors of light, red, green, and blue, is a vertically long pixel having an aspect ratio of 3: 1, and is suitable for a display device that performs one color display with three pixels. is there.

In the arrangement shown in FIG. 3, the spatial frequency of the pixel arrangement where the video signal is simultaneously written for each gate line is
This is 1/3 that of the arrangement shown in FIG. However, it has a much higher spatial frequency than the conventional arrangement as shown in FIG. That is, the change in contrast that occurs when writing a signal for each gate line is equal to or less than the visual limit. Therefore, even when the gate line inversion driving method and the interlace driving method are used together, no interference fringes are visually recognized.

Although not shown, the TFT shown in FIG.
The data line driving circuit for driving the array includes one of the data lines D1 and D2 shown in FIG.
A data line having one latch circuit and a data line having two latch circuits in series are arranged in three cycles.

The present invention is not limited to the above embodiment. As another embodiment of the present invention, for example, along a gate line, at an arbitrary number n,
There is a liquid crystal display device having an arrangement in which pixel TFTs above and below the gate line are alternately connected to the gate line. In addition, the data line driving circuit of the liquid crystal display device having such an arrangement includes a data line having one latch circuit and a data line having two latch circuits as shown by D1 and D2 in FIG. It is configured to be arranged in a cycle.

Further, as another embodiment of the present invention,
One in which the period of the arrangement of the pixel TFTs dispersedly connected above and below the gate electrode is not constant.

[0048]

According to the present invention, it is possible to realize interlace driving capable of driving with low power consumption by gate line inversion driving that can use a low-voltage driving IC, without causing image quality deterioration such as interference fringes. As a result, it has become possible to realize a low-cost liquid crystal display device with low power consumption. Further, a normal image can be displayed by arranging a memory for temporarily storing data in the data line driving circuit in accordance with the period of the positive polarity and the negative polarity of the pixel electrode.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an arrangement on an array substrate of a liquid crystal display device according to the present invention, and a conceptual diagram showing a potential of a pixel electrode at the time of 4: 1 interlace driving.

FIG. 2 is a schematic configuration diagram showing an example of a data line driving circuit for the TFT array shown in FIG.

FIG. 3 is a schematic configuration diagram illustrating a modification of the liquid crystal display device according to the present invention.

FIG. 4 is a configuration diagram showing a schematic configuration of a conventional active matrix type liquid crystal display device.

FIG. 5 is a timing chart illustrating driving timings in a gate line driving method.

FIG. 6 is a conceptual diagram for explaining a 3: 1 interlace driving method.

[Explanation of symbols]

 1, 11, 31, 101 Data line drive circuit 2, 32, 102 Gate line drive circuit G1, G2 Gate line D1, D2 Data line 5, 5A, 5B, 5a, 5b TFT 6, 6A, 6B, 6a, 6b Pixel Electrode 7 Liquid crystal layer 8 Counter electrode 14 DA converter

Claims (5)

[Claims] 1. A pixel electrode arranged in a matrix of a plurality of rows and a plurality of columns in an image display area, a switching element connected to the pixel electrode and switching supply of a video signal, and A plurality of gate lines wired substantially parallel to the row direction and controlling the switching operation of the switching element, and a plurality of data lines wired substantially orthogonal to the gate line and supplying the video signal to the switching element A liquid crystal display device comprising: an array substrate having lines; a counter substrate having electrodes formed to face the array substrate; and a liquid crystal layer sandwiched between the array substrate and the counter substrate. Of the two adjacent rows of pixel electrodes arranged in the wiring direction of the gate line in the image display area, one row and the other row alternate with a fixed number of pixels in a cycle. The liquid crystal display device, wherein the switching operation of the switching element connected to the pixel electrode located at the same position is controlled by the same gate line. 2. A data line scanning circuit for supplying the video signal sequentially input for each row of the image display area to each of the data lines, and a memory for storing the video signal, According to the arrangement state of the pixel electrodes connected to the switching elements, the switching of which is controlled by the gate line, by temporarily storing the video signal in the memory, the video signal sequentially input for each row 2. The liquid crystal display device according to claim 1, further comprising a data line driving circuit configured to supply the data to a corresponding pixel electrode in the image display area. 3. A signal for controlling the switching element is sequentially supplied to each of the plurality of gate lines of the liquid crystal display device according to claim 2, and the signal for controlling is supplied to the gate line. When the video signal is supplied to the switching element controlled by the data line via the data line, a predetermined image is displayed by inverting the voltage polarity of the video signal for each of the plurality of gate lines. The method for driving a liquid crystal display device as described above. 4. The method according to claim 2, wherein the video signal is written to the pixel electrode by a predetermined number n (n ≧ 2).
A method for driving a liquid crystal display device, which is performed by an interlace driving method under the condition of an interlace ratio n: 1 expressed by: 5. The predetermined number n is an even number of 4 or more, and in the same field, the voltage polarity of the video signal is alternately inverted for each gate line to which the video signal is written, and a predetermined number i (i ≧ 0) ) And n,
From the (+ in) field to the (i + 1) n-th field, the voltage polarity of the video signal corresponding to the gate line to be written at the beginning of the field is alternately inverted for each field, and the (i + 1) n-th field and the [( 5. The method according to claim 4, wherein the voltage polarity of the video signal corresponding to the gate line to be written first in each field is the same between the (i + 1) n + 1] fields.