JPH10107086A - Electronic circuit device including semiconductor element - Google Patents
Electronic circuit device including semiconductor elementInfo
- Publication number
- JPH10107086A JPH10107086A JP28141496A JP28141496A JPH10107086A JP H10107086 A JPH10107086 A JP H10107086A JP 28141496 A JP28141496 A JP 28141496A JP 28141496 A JP28141496 A JP 28141496A JP H10107086 A JPH10107086 A JP H10107086A
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- semiconductor element
- protective resin
- circuit board
- metal wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/015—Manufacture or treatment of bond wires
- H10W72/01515—Forming coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【課題】 バンプ電極を有する半導体素子の近傍に設け
られた金属細線のボンディング部分がシリコーンラバー
から成る保護樹脂によって剥離されることがある。
【解決手段】 回路基板３上に配置されたバンプ電極１
を有する半導体素子２の本体部２ａと回路基板３との間
にエポキシ樹脂から成る第１の保護樹脂層５ａを設け
る。半導体素子２の本体部２ａの上面及び金属細線８の
接続部を覆うようにポリイミド樹脂から成る第２の保護
樹脂層６ａを設ける。回路基板３を金属支持板１１の上
に配置し、エポキシ樹脂から成る樹脂封止体１２で被覆
する。第１の保護樹脂層５ａの硬度を第２の保護樹脂層
６ａの硬度よりも大きくする。
(57) Abstract: A bonding portion of a thin metal wire provided near a semiconductor element having a bump electrode may be peeled off by a protective resin made of silicone rubber. SOLUTION: A bump electrode 1 arranged on a circuit board 3 is provided.
A first protective resin layer 5a made of epoxy resin is provided between the main body 2a of the semiconductor element 2 having the above structure and the circuit board 3. A second protective resin layer 6a made of a polyimide resin is provided so as to cover the upper surface of the main body 2a of the semiconductor element 2 and the connection portion of the thin metal wire 8. The circuit board 3 is placed on a metal support plate 11 and covered with a resin sealing body 12 made of epoxy resin. The hardness of the first protective resin layer 5a is set higher than the hardness of the second protective resin layer 6a.
Description
【０００１】[0001]
【産業上の利用分野】本発明はバンプ電極（突起電極）
を有する半導体素子を含む電子回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump electrode (bump electrode).
The present invention relates to an electronic circuit device including a semiconductor element having:
【０００２】[0002]
【従来の技術】図１に示すようにバンプ電極１を備えた
半導体素子２を回路基板３上に搭載した電子回路装置は
公知である。半導体素子２はバンプ電極１を回路基板３
の配線導体４に半田付けすることによって取付けられ、
外部から水分等の異物が侵入することを防止するために
第１及び第２の保護樹脂層５、６によって被覆されてい
る。第１の保護樹脂層５はシリコーンゲルから成り、バ
ンプ電極１を被覆し且つ半導体素子２の本体部２ａの下
面と回路基板３との間を充填するように設けられてい
る。第２の保護樹脂層６はシリコーンラバーから成り、
半導体素子２の本体部２ａの上面及び第１の保護樹脂層
５を被覆すると共に高集積化のために半導体素子２の近
傍に配置された別の回路素子に接続された金属細線８の
接続部分も被覆するように形成されている。回路基板３
は上面に金属細線接続用の配線導体９を有し、下面に金
属層１０を有する。なお、半導体素子２の下面を含めて
全体を被覆するようにシリコーンラバーから成る第２の
保護樹脂層６を設けないのは、半導体素子２の下面にシ
リコーンラバーを注入すると、シリコーンラバーは比較
的大きな弾性率を有するために半導体素子２を上方に持
ち上げてバンプ電極１を破断するおそれがあるためであ
る。また、半導体素子２の上面も含めて全体を被覆する
ようにシリコーンゲルから成る第１の保護樹脂層５を設
けないのは、シリコーンゲルはシリコーンラバーに比べ
て粘度が十分に小さいため、シリコーンゲルのみでは半
導体素子２の全体を良好に被覆することができないため
である。2. Description of the Related Art As shown in FIG. 1, an electronic circuit device in which a semiconductor element 2 having a bump electrode 1 is mounted on a circuit board 3 is known. The semiconductor element 2 connects the bump electrode 1 to the circuit board 3
Attached by soldering to the wiring conductor 4 of
It is covered with first and second protective resin layers 5 and 6 to prevent foreign matter such as moisture from entering from the outside. The first protective resin layer 5 is made of silicone gel, and is provided so as to cover the bump electrode 1 and fill the space between the lower surface of the main body 2 a of the semiconductor element 2 and the circuit board 3. The second protective resin layer 6 is made of silicone rubber,
A connection portion of the thin metal wire 8 which covers the upper surface of the main body 2a of the semiconductor element 2 and the first protective resin layer 5 and is connected to another circuit element arranged near the semiconductor element 2 for high integration. It is also formed so as to cover. Circuit board 3
Has a wiring conductor 9 for connecting a fine metal wire on the upper surface and a metal layer 10 on the lower surface. The reason why the second protective resin layer 6 made of silicone rubber is not provided so as to cover the entire surface including the lower surface of the semiconductor element 2 is that when silicone rubber is injected into the lower surface of the semiconductor element 2, the silicone rubber is relatively This is because the bump electrode 1 may be broken by lifting the semiconductor element 2 upward due to having a large elastic modulus. Also, the reason why the first protective resin layer 5 made of silicone gel is not provided so as to cover the entire surface including the upper surface of the semiconductor element 2 is that silicone gel has a sufficiently small viscosity as compared with silicone rubber. This is because it is not possible to cover the entire semiconductor element 2 satisfactorily by using only the semiconductor element 2.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上述のよう
に金属細線８が第２の保護樹脂層６で被覆されると、金
属細線８が回路基板３上の配線導体９の界面から剥離す
ることがあった。その理由は必ずしも明らかではない
が、第２の保護樹脂層６を構成するシリコーンラバーの
分解によるものと思われる。この金属細線８の剥離即ち
接続不良を防ぐために金属細線８及び配線導体９を半導
体素子２から離れた位置に設け、これ等を第２の保護樹
脂層６で被覆しない構成にすることが考えられる。しか
し、この様に構成すると高集積化が阻害され、電子回路
装置の小型化が達成されない。図１では金属細線８が回
路基板３上に設けられた電子回路素子７に接続されてい
るが、この金属細線８を回路基板３以外の部分（例えば
外部リード）に対して接続する場合にも同様な問題が生
じる。When the thin metal wire 8 is covered with the second protective resin layer 6 as described above, the thin metal wire 8 is peeled off from the interface of the wiring conductor 9 on the circuit board 3. was there. Although the reason is not necessarily clear, it is considered that the reason is that the silicone rubber constituting the second protective resin layer 6 is decomposed. In order to prevent the thin metal wire 8 from being peeled off, that is, a connection failure, the thin metal wire 8 and the wiring conductor 9 may be provided at a position distant from the semiconductor element 2 and may not be covered with the second protective resin layer 6. . However, with such a configuration, high integration is hindered, and miniaturization of the electronic circuit device cannot be achieved. Although the thin metal wire 8 is connected to the electronic circuit element 7 provided on the circuit board 3 in FIG. 1, the thin metal wire 8 may be connected to a portion other than the circuit board 3 (for example, an external lead). A similar problem arises.
【０００４】そこで、本発明はバンプ電極を有する半導
体素子を良好に保護することができると共に金属細線の
接続不良も防止することができる電子回路装置を提供す
ることを目的とする。Accordingly, an object of the present invention is to provide an electronic circuit device capable of favorably protecting a semiconductor element having a bump electrode and preventing a poor connection of a thin metal wire.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決し、上記
目的を達成するための本発明は、バンプ電極を備えた半
導体素子と、回路基板と、金属細線と、支持体と、第１
及び第２の保護樹脂層と、樹脂封止体とから成り、前記
半導体素子の平板状の本体部は前記バンプ電極によって
前記回路基板の配線導体に接続され、前記金属細線の少
なくとも一端部が前記回路基板上の前記半導体素子の近
傍の配線導体又は電子回路素子の電極に接続され、前記
回路基板は前記支持体上に配置され、前記第１の保護樹
脂層は、前記半導体素子の前記バンプ電極を被覆し且つ
前記半導体素子の前記本体部の一方の主面と前記回路基
板との間を充填しているが前記半導体素子の前記本体部
の他方の主面と前記金属細線の前記配線導体又は前記電
極に対する接続部とを被覆しないように設けられ、前記
第２の保護樹脂層は、前記半導体素子の前記本体部の他
方の主面と前記第１の保護樹脂層と前記金属細線の少な
くとも前記配線導体又は前記電極に対する接続部を被覆
するように設けられ、前記樹脂封止体は前記第２の保護
樹脂層を介して前記回路基板を覆うように設けられ、前
記第１の保護樹脂層は液状エポキシ樹脂に基づいて形成
され、前記第２の保護樹脂層はポリイミド又はポリアミ
ド系樹脂から成り、前記第１の保護樹脂層は前記第２の
保護樹脂層よりも大きい硬度（かたさ）を有しているこ
とを特徴とする電子回路装置に係わるものである。な
お、本発明において、半導体素子とはトランジスタ、ダ
イオード、サイリスタ、集積回路、混成集積回路等の半
導体を含む全ての素子又は部品を意味する。また、電子
回路装置は、半導体集積回路装置、混成集積回路装置、
複合半導体素子、半導体装置等の種々の回路装置を意味
する。SUMMARY OF THE INVENTION In order to solve the above problems and achieve the above object, the present invention provides a semiconductor device having a bump electrode, a circuit board, a thin metal wire, a support,
And a second protective resin layer, and a resin sealing body, wherein the flat main body of the semiconductor element is connected to the wiring conductor of the circuit board by the bump electrode, and at least one end of the thin metal wire is The circuit board is connected to a wiring conductor in the vicinity of the semiconductor element on a circuit board or an electrode of an electronic circuit element, the circuit board is disposed on the support, and the first protective resin layer is provided on the bump electrode of the semiconductor element. And the gap between one main surface of the main body of the semiconductor element and the circuit board is filled, but the other main surface of the main body of the semiconductor element and the wiring conductor of the thin metal wire or The second protective resin layer is provided so as not to cover a connection portion to the electrode, and the second protective resin layer is at least the other main surface of the main body portion of the semiconductor element, the first protective resin layer, and the thin metal wire. Wiring Alternatively, the resin sealing body is provided so as to cover a connection portion to the electrode, the resin sealing body is provided so as to cover the circuit board via the second protection resin layer, and the first protection resin layer is formed of liquid epoxy. The second protective resin layer is formed of a resin, the second protective resin layer is made of a polyimide or polyamide resin, and the first protective resin layer has a higher hardness (hardness) than the second protective resin layer. The present invention relates to an electronic circuit device characterized by the above. In the present invention, a semiconductor element means all elements or components including a semiconductor such as a transistor, a diode, a thyristor, an integrated circuit, and a hybrid integrated circuit. The electronic circuit device may be a semiconductor integrated circuit device, a hybrid integrated circuit device,
It means various circuit devices such as a composite semiconductor element and a semiconductor device.
【０００６】[0006]
【発明の作用及び効果】本発明は次の作用及び効果を有
する。 （イ） 半導体素子を被覆する第２の保護樹脂層がポリ
イミド又はポリアミド系樹脂から成るので、高集積化の
ために半導体素子と共に第２の保護樹脂層で被覆された
金属細線の配線導体又は電極からの剥離が防止される。
この理由は必ずしも明確でないが、ポリイミド又はポリ
アミド系樹脂は従来のシリコーンラバーに比べて耐熱性
があり、熱分解を起し難いためと思われる。 （ロ） 半導体素子と回路基板との間には第２の保護樹
脂層よりも硬度が大きいエポキシ樹脂から成る第１の保
護樹脂層が設けられているので、樹脂封止体の熱膨張又
は熱収縮によって半導体素子が回路基板の方向に押圧さ
れても、バンプ電極が押しつぶされない。なお、第１の
保護樹脂層の部分まで第１の保護樹脂層と同一のポリイ
ミド又はポリアミド系樹脂を設けると、粘度があまり高
くならないので半導体素子と回路基板との間に十分に樹
脂を充填することができず、隙き間が生じ、樹脂封止体
の熱変形によって半導体素子が押圧された時にバンプ電
極が押しつぶされるおそれがある。The present invention has the following functions and effects. (A) Since the second protective resin layer covering the semiconductor element is made of polyimide or polyamide resin, a wiring conductor or an electrode of a thin metal wire covered with the second protective resin layer together with the semiconductor element for high integration. Is prevented from being peeled off.
The reason for this is not necessarily clear, but it is considered that polyimide or polyamide resins have higher heat resistance than conventional silicone rubber and are less likely to undergo thermal decomposition. (B) Since the first protective resin layer made of an epoxy resin having a higher hardness than the second protective resin layer is provided between the semiconductor element and the circuit board, thermal expansion or heat of the resin sealing body is provided. Even if the semiconductor element is pressed in the direction of the circuit board due to shrinkage, the bump electrode is not crushed. If the same polyimide or polyamide resin as the first protective resin layer is provided up to the first protective resin layer, the viscosity does not increase so much that the resin is sufficiently filled between the semiconductor element and the circuit board. Therefore, there is a possibility that a gap is generated and the bump electrode is crushed when the semiconductor element is pressed by the thermal deformation of the resin sealing body.
【０００７】[0007]
【実施例】次に、図２を参照して本発明の実施例に係わ
る電子回路装置を説明する。図２に示す電子回路装置は
混成集積回路であって、図１と同様に金属突起から成る
バンプ電極１を有する半導体素子２と例えばセラミック
から成る絶縁性回路基板３と電子回路素子７と内部リー
ド細線としての金属細線８とを備えている。半導体素子
２のバンプ電極１は回路基板３上の配線導体４に半田付
けされている。即ち半導体素子２のＰＮ接合等を含む平
板状の本体部２ａの一方の主面が回路基板３の主面に所
定の間隔を有して対向するようにフェースダウンボンデ
ィングされている。例えば直径２００μｍのＡｌワイヤ
から成る金属細線８の一端は半導体素子２の近傍に配置
された回路基板３上の配線導体９に周知のワイヤボンデ
ィング法によってステッチボンディングされ、この他端
は電子回路素子７の上面の電極にワイヤボンディング法
によってステッチボンディングされている。Next, an electronic circuit device according to an embodiment of the present invention will be described with reference to FIG. The electronic circuit device shown in FIG. 2 is a hybrid integrated circuit. As in FIG. 1, a semiconductor element 2 having a bump electrode 1 made of a metal projection, an insulating circuit board 3 made of, for example, ceramic, an electronic circuit element 7, and internal leads And a thin metal wire 8 as a thin wire. The bump electrode 1 of the semiconductor element 2 is soldered to a wiring conductor 4 on a circuit board 3. That is, face-down bonding is performed such that one main surface of the plate-shaped main body portion 2a including the PN junction of the semiconductor element 2 faces the main surface of the circuit board 3 at a predetermined interval. For example, one end of a thin metal wire 8 made of an Al wire having a diameter of 200 μm is stitch-bonded to a wiring conductor 9 on a circuit board 3 disposed near the semiconductor element 2 by a known wire bonding method, and the other end is an electronic circuit element 7. Is stitch-bonded to the electrode on the upper surface of the substrate by a wire bonding method.
【０００８】この実施例においても、バンプ電極１を囲
み且つ半導体素子２の本体部２ａと回路基板３との間を
充填するように第１の保護樹脂層５ａが設けられ、ま
た、半導体素子２の本体部２ａの上面と第１の保護樹脂
層５ａと少なくとも金属細線８の配線導体９に対する接
続部を被覆するように第２の保護樹脂層６ａが設けられ
ている。しかし、この第１及び第２の保護樹脂層５ａ、
６ａの材料及び製造方法が図１の従来の第１及び第２の
保護樹脂層５、６と相違している。Also in this embodiment, a first protective resin layer 5a is provided so as to surround the bump electrode 1 and fill the space between the main body 2a of the semiconductor element 2 and the circuit board 3. The second protective resin layer 6a is provided so as to cover the upper surface of the main body 2a, the first protective resin layer 5a, and at least the connection portion of the thin metal wire 8 to the wiring conductor 9. However, the first and second protective resin layers 5a,
The material and the manufacturing method of 6a are different from the conventional first and second protective resin layers 5 and 6 of FIG.
【０００９】本実施例の第１の保護樹脂層５ａは、従来
の第２の保護樹脂層６を形成するためのシリコーンゴム
よりも粘度が高く、従来の第１の保護樹脂層５を形成す
るシリコーンゲルに近い粘度を有する液状エポキシ樹脂
を半導体素子２の本体部２ａと回路基板３との間に充填
し、しかる後、硬化することによって形成したものであ
る。The first protective resin layer 5a of this embodiment has a higher viscosity than the conventional silicone rubber for forming the second protective resin layer 6, and forms the first protective resin layer 5 of the prior art. It is formed by filling a liquid epoxy resin having a viscosity close to that of silicone gel between the main body 2a of the semiconductor element 2 and the circuit board 3 and then curing the liquid epoxy resin.
【００１０】第２の保護樹脂層６ａは、ポリイミド系樹
脂を塗布して硬化することによって形成したものであ
る。なお、ポリイミド系樹脂の粘度は第１の保護樹脂層
５ａの液状エポキシ樹脂の粘度よりも小さい。また、硬
化した後において、第１の保護樹脂層５ａの硬度（かた
さ）及び剛性（こわさ）は第２の保護樹脂層６ａのこれ
等よりも大きい。The second protective resin layer 6a is formed by applying and curing a polyimide resin. The viscosity of the polyimide resin is smaller than the viscosity of the liquid epoxy resin of the first protective resin layer 5a. After curing, the hardness (hardness) and rigidity (stiffness) of the first protective resin layer 5a are larger than those of the second protective resin layer 6a.
【００１１】半導体素子２が固着された回路基板３は放
熱性を有する金属支持板１１の上に配置され、この下面
の金属層１０が半田（導電性接合材）１２によって支持
板１１に結合され、これ等はエポキシ樹脂から成る樹脂
封止体１３によって一体に成形されている。樹脂封止体
１３は、回路基板３、第２の保護樹脂層６ａ、電子回路
素子７、金属細線８及び支持板１１を覆うように金型を
使用した周知のトランスファモールドで形成されてい
る。なお、図２には示されていないが、回路基板３上の
端子（電極）を外部回路に接続するための外部リードも
設けられており、この外部リードと回路基板３の端子と
が金属細線（内部リード）で接続され、これも樹脂封止
体１３で被覆されている。樹脂封止体１３の硬度は第２
の保護樹脂層６ａの硬度よりも大きく、第１の保護樹脂
層５ａの硬度と同一又はこれよりも小さいことが望まし
い。The circuit board 3 to which the semiconductor element 2 is fixed is disposed on a metal support plate 11 having heat dissipation, and the metal layer 10 on the lower surface is joined to the support plate 11 by solder (conductive bonding material) 12. These are integrally formed by a resin sealing body 13 made of epoxy resin. The resin sealing body 13 is formed by a well-known transfer mold using a mold so as to cover the circuit board 3, the second protective resin layer 6a, the electronic circuit element 7, the fine metal wires 8, and the support plate 11. Although not shown in FIG. 2, an external lead for connecting a terminal (electrode) on the circuit board 3 to an external circuit is also provided, and the external lead and the terminal of the circuit board 3 are connected to a thin metal wire. (Internal leads), which are also covered with the resin sealing body 13. The hardness of the resin sealing body 13 is the second
It is desirable that the hardness of the first protective resin layer 6a is equal to or smaller than the hardness of the first protective resin layer 5a.
【００１２】本実施例においては高集積化のために半導
体素子２の近傍に配置された金属細線８の配線導体９へ
の接続部が第２の保護樹脂層６ａによって剥離され難く
なる。この理由は必ずしも明確でないが、第２の保護樹
脂層６ａは従来のシリコーンラバーよりも耐熱性に優
れ、熱分解しにくいポリイミド樹脂から成るためと思わ
れる。また、ポリイミド樹脂は粘度が低いために半導体
素子２と回路基板３との間に良好に充填することができ
ず隙き間が生じるが、本実施例のようにポリイミド樹脂
よりも粘度が大きい液状エポキシ樹脂を使用すると隙き
間が生じないように良好に第１の保護樹脂層５ａを形成
することができる。また、第１の保護樹脂層５ａの硬度
は第２の保護樹脂層６ａの硬度よりも大きいので、樹脂
封止体１２の熱変形に基づいて押圧されてもバンプ電極
１がつぶれるような問題は生じない。In this embodiment, the connection portion of the thin metal wire 8 arranged near the semiconductor element 2 to the wiring conductor 9 for high integration is hardly peeled off by the second protective resin layer 6a. Although the reason for this is not necessarily clear, it is considered that the second protective resin layer 6a is made of a polyimide resin that has higher heat resistance than conventional silicone rubber and is less likely to be thermally decomposed. In addition, since the polyimide resin has a low viscosity, it cannot be filled well between the semiconductor element 2 and the circuit board 3 and a gap is generated. However, as shown in this embodiment, a liquid having a higher viscosity than the polyimide resin is used. If an epoxy resin is used, the first protective resin layer 5a can be formed satisfactorily so that no gap is generated. Also, since the hardness of the first protective resin layer 5a is higher than the hardness of the second protective resin layer 6a, the problem that the bump electrode 1 is crushed even when pressed based on the thermal deformation of the resin sealing body 12 is not required. Does not occur.
【００１３】[0013]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） 図２では金属細線８を電子回路素子７に接続し
ているが、この代りに外部リード（図示せず）に接続す
ることができる。 （２） 第２の保護樹脂層６ａを電子回路素子７及び金
属細線８の全部を被覆するように形成することができ
る。 （３） 支持板１１の下面を樹脂封止体１２で被覆しな
いように構成することができる。 （４） ポリアミド樹脂によって第２の保護樹脂層６ａ
を形成し得る。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) Although the thin metal wires 8 are connected to the electronic circuit element 7 in FIG. 2, they can be connected to external leads (not shown) instead. (2) The second protective resin layer 6a can be formed so as to cover the entire electronic circuit element 7 and the thin metal wires 8. (3) The lower surface of the support plate 11 can be configured not to be covered with the resin sealing body 12. (4) Second protective resin layer 6a made of polyamide resin
Can be formed.
【図１】従来の電子回路装置を示す断面図である。FIG. 1 is a sectional view showing a conventional electronic circuit device.
【図２】本発明の実施例に係わる電子回路装置を示す断
面図である。FIG. 2 is a sectional view showing an electronic circuit device according to the embodiment of the present invention.
１ バンプ電極 ２ 半導体素子 ３ 回路基板 ５ａ 第１の保護樹脂層 ６ａ 第２の保護樹脂層 ８ 金属細線 １１ 支持板 １３ 樹脂封止体 DESCRIPTION OF SYMBOLS 1 Bump electrode 2 Semiconductor element 3 Circuit board 5a 1st protective resin layer 6a 2nd protective resin layer 8 Thin metal wire 11 Support plate 13 Resin sealing body
Claims (1)
基板と、金属細線と、支持体と、第１及び第２の保護樹
脂層と、樹脂封止体とから成り、 前記半導体素子の平板状の本体部は前記バンプ電極によ
って前記回路基板の配線導体に接続され、 前記金属細線の少なくとも一端部が前記回路基板上の前
記半導体素子の近傍の配線導体又は電子回路素子の電極
に接続され、 前記回路基板は前記支持体上に配置され、 前記第１の保護樹脂層は、前記半導体素子の前記バンプ
電極を被覆し且つ前記半導体素子の前記本体部の一方の
主面と前記回路基板との間を充填しているが前記半導体
素子の前記本体部の他方の主面と前記金属細線の前記配
線導体又は前記電極に対する接続部とを被覆しないよう
に設けられ、 前記第２の保護樹脂層は、前記半導体素子の前記本体部
の他方の主面と前記第１の保護樹脂層と前記金属細線の
少なくとも前記配線導体又は前記電極に対する接続部を
被覆するように設けられ、 前記樹脂封止体は前記第２の保護樹脂層を介して前記回
路基板を覆うように設けられ、 前記第１の保護樹脂層は液状エポキシ樹脂に基づいて形
成され、 前記第２の保護樹脂層はポリイミド又はポリアミド系樹
脂から成り、 前記第１の保護樹脂層は前記第２の保護樹脂層よりも大
きい硬度を有していることを特徴とする電子回路装置。1. A flat plate of the semiconductor element, comprising: a semiconductor element having a bump electrode; a circuit board; a thin metal wire; a support; first and second protective resin layers; The main body is connected to a wiring conductor of the circuit board by the bump electrode, and at least one end of the thin metal wire is connected to a wiring conductor near the semiconductor element on the circuit board or an electrode of an electronic circuit element, The circuit board is disposed on the support, and the first protective resin layer covers the bump electrode of the semiconductor element and forms one of the main surface of the main body of the semiconductor element and the circuit board. The second protective resin layer is provided so as not to cover the other main surface of the main body portion of the semiconductor element and the connection portion of the fine metal wire to the wiring conductor or the electrode. , The semiconductor A second main surface of the main body, the first protective resin layer, and at least a connection portion of the thin metal wire to the wiring conductor or the electrode; Is provided so as to cover the circuit board with a protective resin layer interposed therebetween, the first protective resin layer is formed based on a liquid epoxy resin, and the second protective resin layer is made of polyimide or polyamide resin, The electronic circuit device according to claim 1, wherein the first protective resin layer has a higher hardness than the second protective resin layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28141496A JP2904154B2 (en) | 1996-10-02 | 1996-10-02 | Electronic circuit device including semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28141496A JP2904154B2 (en) | 1996-10-02 | 1996-10-02 | Electronic circuit device including semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10107086A true JPH10107086A (en) | 1998-04-24 |
| JP2904154B2 JP2904154B2 (en) | 1999-06-14 |
Family
ID=17638834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28141496A Expired - Fee Related JP2904154B2 (en) | 1996-10-02 | 1996-10-02 | Electronic circuit device including semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2904154B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7285446B2 (en) | 2000-02-07 | 2007-10-23 | Rohm Co., Ltd. | Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device |
| US8004075B2 (en) * | 2006-04-25 | 2011-08-23 | Hitachi, Ltd. | Semiconductor power module including epoxy resin coating |
| JP2014116409A (en) * | 2012-12-07 | 2014-06-26 | Denso Corp | Electronic device |
| CN115706100A (en) * | 2021-08-05 | 2023-02-17 | 群创光电股份有限公司 | Electronic device |
-
1996
- 1996-10-02 JP JP28141496A patent/JP2904154B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7285446B2 (en) | 2000-02-07 | 2007-10-23 | Rohm Co., Ltd. | Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device |
| US8004075B2 (en) * | 2006-04-25 | 2011-08-23 | Hitachi, Ltd. | Semiconductor power module including epoxy resin coating |
| US8125090B2 (en) | 2006-04-25 | 2012-02-28 | Hitachi, Ltd. | Semiconductor power module |
| JP2014116409A (en) * | 2012-12-07 | 2014-06-26 | Denso Corp | Electronic device |
| CN115706100A (en) * | 2021-08-05 | 2023-02-17 | 群创光电股份有限公司 | Electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2904154B2 (en) | 1999-06-14 |
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