JPH10107624A - PLL circuit - Google Patents

Abstract

(57) Abstract: A PLL circuit capable of selecting and using a phase comparator having different characteristics according to a lock state is provided. SOLUTION: A reference oscillator 1, a first frequency divider 3 for dividing a reference oscillation signal by 1 / N, and a variable oscillator 2
And a second frequency divider 4 for frequency-dividing the variable oscillation signal from the variable oscillator into 1 / M, and a frequency-dividing output from the first and second frequency dividers for phase comparison with each other. A lock state is detected by comparing a plurality of different phase comparators 5 and 6 with respective frequency division outputs from the first and second frequency dividers, and a plurality of phase comparisons are performed in accordance with the detected lock state. Phase determining means 8 for selecting a filter, and a comparison output from the selected phase comparator is supplied and filtered, and the filtered output is supplied to a variable oscillator as a frequency control signal.
And

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL circuit.

[0002]

2. Description of the Related Art In a conventional PLL circuit, the characteristics of a phase comparator and a loop filter are uniquely set in advance.

[0003]

The high-speed pull-in type phase comparator always outputs an error signal when the phase is out of phase, so that the high-speed pull-in type phase comparator uses a high-speed pull-in type phase comparator. The PLL circuit described above literally performs synchronization pull-in at a high speed, but on the other hand, its operation becomes unstable. The high-speed pull-in type phase comparator has some dead zones because of a dead zone.

The window type phase comparator outputs an error signal only within a window, and therefore has a low phase comparison capability.
The operation of the LL circuit is stable, but the synchronization is slow.
The window type phase comparator does not generate jitter.

In view of the above, the present invention provides a lock state (including a lock state and an unlock state in a narrow sense, but also an intermediate state between them).
PLL that can select phase comparators with different characteristics
It is intended to propose a circuit.

Another object of the present invention is to propose a PLL circuit in which the operation becomes stable in a locked state and at a high speed in an unlocked state such as when power is turned on.

[0007]

The PLL circuit of the present invention comprises:
A reference oscillator and a reference oscillation signal from the reference oscillator are set to 1
/ N, a first frequency divider, a variable oscillator, a second frequency divider for dividing a variable oscillation signal from the variable oscillator to 1 / M, and first and second frequency dividers. A plurality of phase comparators having different characteristics from each other for comparing phases of the divided outputs from the dividers, and the divided outputs from the first and second dividers are compared to detect a locked state, and the detection is performed. A phase determination means for selecting a plurality of phase comparators in accordance with the locked state, and a comparison output from a selected one of the plurality of phase comparators is supplied and filtered, and the filtered output is provided. A loop filter supplied to the variable oscillator as a frequency control signal.

According to the present invention, a plurality of phase comparators are selected in accordance with the lock state detected by the phase determining means, and the comparison output from the selected phase comparator is supplied to the loop filter. .

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, a PLL circuit according to the first embodiment will be described with reference to FIG. 1 is a reference frequency oscillator, 2 is a reference oscillation signal from the reference oscillator 1,
This is a first frequency divider that divides the frequency by 1 / N (N is an integer). 2
Reference numeral denotes a voltage controlled oscillator as a variable oscillator, and reference numeral 4 denotes a second frequency divider for dividing a variable oscillation signal from the voltage controlled oscillator into 1 / M (M is an integer). Note that N and M are generally integers of 2 or more, but may be 1 which means that the frequency dividers 3 and 4 do not divide the frequency.

Reference numerals 5 and 6 denote first and second phase comparators, respectively, which have different characteristics. That is, the first phase comparator 5 is a window type phase comparator, and the second phase comparator 6 is a high-speed pull-in type phase comparator. First and second
The frequency-divided outputs of the frequency dividers 3 and 4 are supplied to both the first and second phase comparators 5 and 6 and are compared in phase.

Numeral 8 is a phase judging means for comparing each divided output from the first and second frequency dividers 3 and 4 to judge whether the PLL circuit is locked or unlocked. And supplies a control signal to the first phase comparator 5,
The control signal is supplied to the inverter 9 and the inverted control signal obtained is supplied to the second phase comparator 6 to selectively activate the first and second phase comparators 5 and 6.

Next, the first and second phase determination means 8
The selection of the comparators 5 and 6 will be described with reference to FIG. Initially when power is turned on (unlocked of course)
Selects the high-speed retractable second phase comparator 6,
This is put into an operating state (step ST-1). The phase determination means 8 determines whether or not the phase is locked (step ST-2).
Returning to 1, the selection of the second phase comparator 6 is continued. If YES in step ST-2, the window type first
Is selected (step ST-3). After step ST-3, the phase determination means 8 determines again whether or not the phase is locked (step ST- 3).
4) If NO, return to step ST-1
Is selected, and if YES, the step S
Returning to T-3, the window-type first phase comparator 5 is selected (step ST-3).

Referring back to FIG. 1, reference numeral 7 denotes a loop filter, which is a loop filter body 7M.
And a resistor 1 connected in series to the first and second phase comparators 5 and 6 and mainly affecting the time constant of the loop filter 7
0A or a resistor 10B. in this case,
The resistance value of the resistor 10A connected to the window-type first phase comparator 5 side is made higher than the resistance value of the resistor 10B connected to the high-speed synchronization pull-in second phase comparator 6. We have selected a large one. And the loop filter 7
The DC component of the phase comparison output is supplied to the voltage controlled oscillator 2 and its oscillation frequency is controlled.

A specific circuit example of the loop filter 7 shown in FIG. 2 will be described. The capacitor 7B is connected between the non-inverting input terminal of the operational amplifier 7A and the ground. Resistors R1, R2 of equal resistance connected between + 5V DC power supply and ground
(10 kΩ) DC voltage obtained at the connection midpoint +2.5 V
Is applied to the non-inverting input terminal of the operational amplifier 7A. A capacitor 7C and a series circuit of a resistor 7D and a capacitor 7E are connected in parallel between the output terminal and the inverting input terminal of the operational amplifier 7A. Resistors 10A, 10
B is connected in series to the inverting input terminal of the operational amplifier 7A.

The time constant of the loop filter 7 is determined by the resistor 10
It is determined by the resistance of A (or 10B), the capacitance of capacitor 7E and the resistance of resistor 7D, but is mainly determined by the resistance of resistor 10A (or 10B). Here, the time constants of the loop filter 7 when the window type first phase comparator 5 and the high-speed synchronization pull-in type second phase comparator 6 are selected are tw and t, respectively.
Assuming that m and the resistance values of the resistors 10A and 10B are Ra and Rb, the following relational expression holds between them.

[0016]

(Tm / tw) ² ≒ Rb / Ra Instead of selecting the first and second phase comparators 5 and 6 by the phase judging means 8 to set them in the operating state, the resistor 1
A changeover switch may be provided between 0A, 10B and the loop filter body 7M, and the changeover switch may be changed over by a control signal from the phase judging means 8.

Next, a specific circuit example of the window type first phase comparator 5 of FIG. 1 will be described with reference to FIG. 1 / N divider 3 and 1 / M divider 4 are connected to input terminals 20 and 21.
The divided output signals a and b (see FIGS. 4A and 4B) are supplied. The signal a is supplied directly to the AND gate 23, and an inverted signal of the signal a is supplied to the AND gate 24. The signal b is supplied to the AND gate 23 through the inverter 22.
And the inverted signal of the signal b is supplied to the AND gate 24. Each output of the AND gates 23 and 24 is supplied to a charge pump 25, from which an output terminal 26 is derived, from which an output signal, that is, a phase comparison output c is output.

Next, the operation of the first phase comparator of FIG. 3 will be described with reference to the timing chart of FIG. 1 / M
The signal b (FIG. 4B) from the frequency divider 4 is, for example, a window signal whose window is the period of the logic L. The error signal from the output terminal 26 has a high impedance (Hi-Z) outside the window, and a substantial error signal cannot be obtained. In the window, the error signal is an exclusive OR of the signals a and b. . In this case, for example, the voltages of logic H and logic L are +5 V, 0 V, and high impedance (Hi-Z).
The voltage at the time is 2.5V.

Thus, the output terminal 26 of the first phase comparator 5 shown in FIG. 3 only outputs 1 / N of the reference oscillation signal from the 1 / N frequency divider 3 with respect to the 1 / N frequency output within the window.
Since an error signal based on the phase difference of the 1 / M frequency-divided output of the variable oscillation signal from the M frequency divider 4 is obtained, the operation of the PLL circuit in the locked state becomes stable, but it takes time to pull in the synchronization.

Next, a specific circuit example of the second phase comparator 6 of the high-speed phase pull-in type shown in FIG. 1 will be described with reference to FIG. In this circuit, reference numerals 33 to 41 denote NAND gates. NAND gates 33 and 40, 34 and 35, 3
6 and 41, 37 and 38 are connected to form a flip-flop circuit, respectively. The frequency-divided output signals a and b from the 1 / N frequency divider 3 and 1 / M frequency divider 4 are input to the NAND terminals 31 and 32, respectively.
It is supplied to gates 33 and 36.

The output of the NAND gate 33 of the flip-flop circuit composed of the NAND gates 33 and 40 is
It is supplied to a NAND gate 34 of a flip-flop circuit composed of NAND gates 34 and 35. NAND
The output of the NAND gate 36 of the flip-flop circuit composed of the gates 36 and 41 is
38 is supplied to the NAND gate 37 of the flip-flop circuit composed of. NAND gate 33 of flip-flop circuit composed of NAND gates 33 and 40
, The output of the NAND gate 34 of the flip-flop circuit composed of the NAND gates 34 and 35,
Output of NAND gate 36 of flip-flop circuit composed of D gates 36 and 41 and NAND gate 3
NAN of flip-flop circuit composed of 7 and 38
The output of the D gate 37 is supplied to the NAND gate 39, and the output is supplied to the NAND gates 40, 35, 41 and 3
8 is supplied. Then, output signals c and d of the NAND gates 40 and 41 are supplied to a charge pump 42, and an output terminal 43 from which an error signal is output is derived from the charge pump 42.

Next, the operation of the second phase comparator of FIG. 5 will be described with reference to the timing charts of FIGS. FIG. 6 shows a signal b (FIG. 6) supplied to the input terminal 32.
The output signals c (FIG. 6C) and d (FIG. 6C) of the NAND gates 40 and 41 when the frequency of B) is lower than the frequency of the signal a (FIG. 6A) supplied to the input terminal 31.
D) is shown. In this case, an output signal c is obtained in which the lower the frequency of the input signal b, the longer the period of logic 0. Note that the output signal d is always a logical 1 signal. FIG. 7 shows that the frequency of the signal b (FIG. 6B) supplied to the input terminal 32 is equal to the frequency of the signal a (FIG. 6A) supplied to the input terminal 31, but that the NAND gate 40, The output signals c (FIG. 6C) and d (FIG. 6D) of 41
Is shown. In this case, an output signal c that periodically becomes logic 0 is obtained only during a period corresponding to the phase difference between the input signal b and the input signal a. Note that the output signal d is always a logical 1 signal.

Thus, the 1 / N divider 3 is output from the output terminal 43 of the charge pump 42 of the second phase comparator 6 in FIG.
1 / M with respect to the 1 / N divided output of the reference oscillation signal
Since an error signal based on the frequency difference and phase difference of the 1 / M frequency output of the variable oscillation signal from the frequency divider 4 is always obtained,
Synchronization of the PLL circuit is performed at high speed, but stability at the time of locking is reduced.

For example, in a digital still camera,
From the camera clock signal (12.2 MHz), PA
Sampling signal of L color digital color video signal (17.734 which is four times the color subcarrier frequency 4.4336)
When the PLL circuit shown in FIG. 1 is applied to a PLL circuit having a frequency of 1 MHz, the reference oscillation frequency f ₀ of the reference frequency oscillator 1, the oscillation frequency f _V of the voltage control oscillator 2, and a 1 / N frequency divider 3 and 1 / M frequency divider 4 division ratio 1 /
An example of N, 1 / M is as follows.

F ₀ = 12.38 MHz, f _V = 17.7
3 MHz, 1 / N = 1/780, 1 / M = 1/1135 The color subcarrier frequency of the PAL color video signal is 1 /
Since there is a four-line offset, the operation of the PLL circuit is further stabilized by increasing the time constant of the loop filter 7 when the first phase comparator 5 operates during locking.

Next, a second embodiment of the present invention will be described with reference to FIG. 9. In FIG. 9, the portions corresponding to those in FIG. In the second embodiment, each comparison output of the first phase comparator 5 of the window type and the second moving comparator 6 of the high-speed synchronization pull-in type is switched by the switch 11 and supplied to the loop filter 7. This loop filter 7 has a loop filter body 7 corresponding to the loop filter body 7M of FIG.
M and a resistor 10C in which the resistors 10A and 10B and the switch 11 of FIG. 1 are replaced.
Then, the phase determining means 8 compares the divided outputs from the first and second frequency dividers 3 and 4 to determine whether the PLL circuit is locked or unlocked. The switching of the changeover switch 11 is controlled by a control signal based on the determination result.

When the PLL circuit is in the locked state, the changeover switch 11 is switched to the first phase comparator 5 side, and when the PLL circuit is in the unlocked state, the changeover switch 11 is switched to the second phase comparator 6 side. In this case, the loop filter 7
Are not switched. Accordingly, in FIG. 2, the specific circuit of the loop filter 7 is, for example, connected to the circuit of the loop filter body 7M and the inverting input terminal of the operational amplifier 7A.
This is a circuit in which only the resistor 10B is connected.

For example, in a digital still camera,
From the camera clock signal (12.3 MHz), NT
Sampling signal of SC digital color video signal (14.32 which is four times the color subcarrier frequency of 3.58 MHz)
When the PLL circuit of FIG. 2 is applied to a PLL circuit having a frequency of 1 MHz, the reference oscillation frequency f ₀ of the reference frequency oscillator 1, the oscillation frequency f _V of the voltage control oscillator 2, and a 1 / N frequency divider 3 and 1 / M frequency divider 4 division ratio 1 /
An example of N, 1 / M is as follows.

F ₀ = 12.27 MHz, f _V = 14.3
2 MHz, 1 / N = 1/780, 1 / M = 1/910

[0030]

According to the first aspect of the present invention, a reference oscillator,
A first frequency divider for dividing the reference oscillation signal from the reference oscillator into 1 / N, a variable oscillator, and a second frequency divider for dividing the variable oscillation signal from the variable oscillator into 1 / M And the first
A plurality of phase comparators having different characteristics from each other for phase-comparing the respective divided outputs from the second and third frequency dividers with the respective divided outputs from the first and second frequency dividers, and in a locked state And a phase judging means for selecting a plurality of phase comparators in accordance with the detected lock state, and a comparison output from a selected one of the plurality of phase comparators is supplied to filter And a loop filter whose filtered output is supplied as a frequency control signal to a variable oscillator.
A PLL circuit that can select and use phase comparators having different characteristics according to the locked state can be obtained.

According to the second aspect of the present invention, the reference oscillator, the first frequency divider for dividing the reference oscillation signal from the reference oscillator by 1 / N, the variable oscillator, and the variable oscillator from the variable oscillator A second frequency divider for dividing the oscillation signal by 1 / M, a window type first phase comparator for comparing the phases of the divided outputs from the first and second frequency dividers, and a high-speed pull-in The second phase comparator of the formula is compared with each divided output from the first and second frequency dividers to detect a locked state or an unlocked state. A phase judging means for selecting the comparator and selecting the second phase comparator in the unlocked state, and the comparison output from the selected one of the first and second phase comparators. Supplied and filtered, and the filtered output is supplied to a variable oscillator as a frequency control signal. Since having a loop filter, the operation becomes stable in the locked state, the unlocked state, such as when the power is turned on, PLL to draw high speed is performed
A circuit can be obtained.

According to the third invention, the P of the second invention is
In the LL circuit, the time constant of the loop filter when the first phase comparator is selected is made longer than the time constant of the loop filter when the second phase comparator is selected. Thus, a PLL circuit can be obtained in which the operation is further stabilized and the pull-in is performed at a higher speed in an unlocked state such as when the power is turned on.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a specific example of a circuit of the loop filter according to the first embodiment;

FIG. 3 is a circuit diagram illustrating a specific circuit example of a first phase comparator according to the first embodiment;

FIG. 4 is a timing chart for explaining the operation of the first phase comparator;

FIG. 5 is a circuit diagram showing a specific circuit example of a second phase comparator according to the first embodiment.

FIG. 6 is a timing chart for explaining the operation of the second phase comparator;

FIG. 7 is a timing chart for explaining the operation of the second phase comparator;

FIG. 8 is a flowchart for explaining the operation of the first embodiment.

FIG. 9 is a block diagram showing a PLL circuit according to a second embodiment of the present invention.

[Explanation of symbols]

1 reference frequency oscillator, 2 voltage controlled oscillator, 3 1 /
N frequency divider, 4 1 / M frequency divider, 5 first phase comparator,
6 second phase comparator, 7 loop filter, 7M loop filter main body, 8 phase judging means, 9 inverter, 10A, 10B resistor, 11 switch.

Claims (3)

[Claims] 1. A reference oscillator, a first frequency divider for dividing a reference oscillation signal from the reference oscillator by 1 / N, a variable oscillator, and a variable oscillation signal from the variable oscillator by 1 / M A second frequency divider for frequency division; a plurality of phase comparators having different characteristics from each other for phase-comparing respective frequency-divided outputs from the first and second frequency dividers; and the first and second frequency dividers. Phase determining means for comparing the respective divided outputs from the frequency divider to detect a locked state, and selecting the plurality of phase comparators according to the detected locked state; and A PLL circuit comprising: a comparison output from a selected one of the phase comparators, supplied and filtered, and a loop filter having the filtered output supplied to the variable oscillator as a frequency control signal. 2. A reference oscillator, a first frequency divider for dividing a reference oscillation signal from the reference oscillator by 1 / N, a variable oscillator, and a variable oscillation signal from the variable oscillator by 1 / M. A second frequency divider for frequency division; a window type first phase comparator for comparing phases of the respective divided outputs from the first and second frequency dividers; and a high-speed pull-in second phase A comparator is compared with each divided output from the first and second frequency dividers to detect a locked state or an unlocked state, and selects the first phase comparator when locked. And a phase judging means for selecting the second phase comparator in the unlocked state, and a comparison output from the selected phase comparator of the first and second phase comparators is supplied. The filtered output is supplied to the variable oscillator as a frequency control signal. PLL having a loop filter
circuit. 3. The PLL circuit according to claim 2, wherein the time constant of the loop filter when the first phase comparator is selected is set as the time constant when the second phase comparator is selected. A PLL circuit having a time constant longer than a time constant of a loop filter.