JPH10108028A - Digital signal encoding / decoding circuit - Google Patents

Abstract

(57) [Summary] [Problem] MR employed in compression of binary image data
In encoding, in a method of encoding when white pixels continue, the original data is accessed even when black pixels continue, so that the effect of reducing the number of memory accesses is small. SOLUTION: Data having a predetermined length and adjacent data are operated by a first adjacent bit holding circuit 26A and a bit operation circuit 27, and a first compression code is used when all are white pixels or black pixels, and a second compression code is used when all are not the same. The compressed code is stored in the line buffer 22 by the line buffer control circuit 21. In the case of the first compression code, white or black data is generated by the white pixel generator 28, the black pixel generator 29, and the second adjacent bit holding circuit 26B. When both the white pixels and the black pixels are continuous, the memory access becomes unnecessary, and the number of accesses can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for controlling the encoding / decoding of a digital signal, and more particularly to a pre-processing circuit for encoding / decoding.

[0002]

2. Description of the Related Art As international standards for encoding / decoding algorithms for binary images used in facsimile, known are an MH (Modified Huffman) system and an MR (Modified Read) system. The MH method is an encoding method in units of one line in the horizontal direction. On the other hand, the MR method is a coding in the vertical direction. When a certain line (called a coding line) is coded, a line immediately before the line (called a reference line) must be referred to. For this reason, two lines of memory are read in order to encode one line, and the number of memory accesses is twice as large as that in the MH system. However, since the accuracy and resolution are better than the MH method,
The R method has become mainstream.

In order to realize an MR encoding / decoding circuit, two lines of information before and after are required as described above, so that there is a problem that the number of memory accesses is large. In order to solve this, a so-called line buffer in which information for one line read from a memory as a coding line is temporarily stored in a buffer having a capacity of one line as a reference line for coding the next line. Control schemes have been proposed. However, in order to perform high-resolution and high-precision encoding / decoding, the amount of information for one line increases, and a large-capacity line buffer is required. For example, 1
When scanning mm with 16 scanning lines, an A4 size image requires a capacity of 3456 bits. Actually, storing in the line buffer and encoding are performed in parallel, so
Two line buffers are required. It is very difficult to integrate such a large-capacity line buffer on the same semiconductor chip as the encoding / decoding circuit.

To cope with such a problem, a method of reducing the number of memory accesses with a small number of line buffers by using a compression line buffer is disclosed in Japanese Patent Laid-Open No. Sho.
No. 4 publication. According to this proposal, bit data on an image memory is divided at regular intervals, a specific code is assigned if the divided specific bit lengths are all the same color, and a different code is used if a different color is included. And by storing only the allocated code in the line buffer, an encoding / decoding circuit with less line buffer memory and less memory access has been proposed. This technique will be described. FIG. 8 is a system configuration diagram of a facsimile or image workstation to which this technology or the present invention is applied.

The image information converted into a digital signal scanned by the scanner 6 is stored in an image memory area 10 in the main memory 5 via a system bus 9 under the control of the host processor 1. When the stored image information is transmitted as it is using a communication means such as a telephone line, an encoding / decoding control circuit 2 including a compression / decompression circuit is used to compress the transmission amount. This control circuit 2
Reads out image information line by line from the image memory area of the main memory 5 and encodes it by the MR method, and transfers the encoded information to the communication controller 7. On the other hand, the encoded information input via the communication controller 7 is temporarily stored in the main memory 5 under the control of the host processor 1. The information stored in the main memory 5 is read out line by line by the encoding / decoding control circuit 2, decoded into original image information, and stored in the image memory area 10 of the main memory 5. The host processor 1 can read out the image information that has been decoded and written in the image memory area 10 from the main memory 5 and print it on the image printer 3 or display it on the CRT 4 or save it on the magnetic disk 8.

FIG. 9 shows an encoding / coding scheme proposed in the above publication.
3 shows an internal block diagram of the decoding circuit 2. FIG. The figure shows the circuits required for encoding. The encoding / decoding control circuit 2 has to read out the information to be encoded from the main memory 5 line by line as described above and encode it, and transfer the encoded information to the communication controller 7. When the host processor 1 reads out information from the main memory 5, the processing capability of the host processor 1 is reduced. Therefore, a DMAC (direct memory access controller) that accesses the main memory 5 instead of the host processor 1. 900 are used. DM
AC 900 is connected to system bus 9 and reads information line by line from image memory area 10 of main memory 5. The read one line of information is input to an encoding line FIFO circuit 901 for encoding, and
The data is input to the black pixel detector 904, and it is determined whether or not all are white. The data in 16-bit units is converted into 1-bit code information. Stored temporarily.

The line buffer control circuit 905 compresses the information of one line input to the encoding line FIFO circuit 901 by the MR encoding circuit 903 so that the corresponding data can be referred to by referring to the information of the previous line. Is read out from the line buffer 906, and at this time, if all white based on the code information, the data is reproduced using the white pixel generator 907, and the data is reproduced by the encoding reference line FIFO circuit 9
Enter 02. If not all white, the data is read from the main memory 5 via the system bus 9 using the DMAC 900.
Therefore, in this method, for image data having many white pixels, data reproduced by the white pixel generator 907 based on the code information can be used, so that memory access at that time becomes unnecessary, and the number of times of memory access is reduced. It is possible to reduce it.

[0008]

However, according to the above proposal, if all the data of a specific bit length is, for example, a white pixel, memory access is not performed, so that the compression proceeds efficiently. If there are black pixels at the point, it is necessary to perform the same memory access as usual, so compression generally proceeds efficiently for images with many white pixels, but for images with many black pixels. There is a problem that the effect is small because the same number of memory accesses as usual is required.

An object of the present invention is to provide a compression line buffer type encoding / decoding circuit which can obtain the same effect as the above-mentioned proposal even for an image having many black pixels. .

[0010]

According to the present invention, each data within a predetermined bit length of a digital signal to be written into a line buffer is subjected to a certain operation with specific data adjacent to the predetermined bit, thereby obtaining each data. And a first circuit for generating one of a first compressed code in the case where all are the same, a second compressed code in the case where they are not the same, and a compressed code generated by the first circuit in the line buffer. A second circuit for controlling writing and reading, and, if the compressed code read by the second circuit is the first compressed code, perform a specific operation on a corresponding predetermined bit length and adjacent specific data. Thereby, data of a white pixel or a black pixel is created and supplied to the encoding / decoding circuit, and if the data is the second compressed code, the data corresponding to the second compressed code is generated. The motor and having a third circuit supplying read from the memory where the data to be the source is stored in the coding / decoding circuit.

The first circuit compares 1-bit data of adjacent data with bit data of predetermined data, and outputs a first compression code when detecting that all the predetermined data are the same pixel. It is configured to Alternatively, it is configured to perform an XOR operation on bit data corresponding to adjacent data and predetermined data. Further, the third circuit inputs a means for generating a white pixel, a means for generating a black pixel, a first compressed code and predetermined data, and outputs a signal obtained by calculating these inputs. Means for selecting one of the white pixel generation means and the black pixel generation means based on the white pixel generation means. Further, the third circuit includes means for outputting a read signal to a memory in which original data is stored when the second compression code is input.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an encoding / decoding circuit including a compression / decompression control circuit according to an embodiment of the present invention. DMAC (direct memory device) connected to the system bus 9 having the system configuration shown in FIG.
The access controller 20 has a reference line FIF
O circuit 23, coding line FIFO circuit 24, bit operation circuit 27, white pixel generator 28, black pixel generator 2
9 are connected. And the bit operation circuit 2
7, a first adjacent bit holding circuit 26A and a line buffer control circuit 21 are connected, and a line buffer 22 is connected to the line buffer control circuit 21. The white pixel generator 28 and the black pixel generator 29 have a second
The second adjacent bit holding circuit 26B is connected to the reference line FIFO circuit 23.
And the line buffer control circuit 21.
Further, an MR encoding circuit 25 is connected to each of the FIFO circuits 23 and 24. That is, this circuit is characterized in that a first adjacent bit holding circuit 26A, a bit operation circuit 27, a black pixel generator 29, a white pixel generator 28, and a second adjacent bit holding circuit 26B are provided.

Next, the operation will be described. When compressing information, DMA
C20 transfers binary image information from the image memory area 10 in the main memory 5 shown in FIG.
The data is read out in units of six pixels and sent to the bit operation circuit 27 and the encoding line FIFO circuit 24 at the same time. Bit operation circuit 2
7 is composed of the circuit shown in FIG.
20 data (D0 to D1) sent from
5) is received by the NOR gate 30 and the AND gate 32, and the respective outputs are input to the multiplexer 33. The control signal of the multiplexer 33 is the first adjacent bit holding circuit 2
6A, if "1", the output of the AND gate 32 is selected, and if "0", the output of the NOR gate 30 is selected. The output of the multiplexer 33 is applied to the flip-flop 31. Assuming that the white information is “0” and the black information is “1”, the 16
If the pixel data is all white and the signal from the adjacent bit holding circuit A is 0, the output of the OR gate becomes "1" and the flip-flop 31 is set to "1". On the other hand, 16
If any of the pixels has at least one bit of black and the signal from the first adjacent bit holding circuit 26A is "0", the output of the NOR gate 30 is "0" and the flip-flop 31 is "0". Is set to

The first adjacent bit holding circuit 26A latches the rightmost 16 bits of the input data for the operation of the next word. The output of the flip-flop 31 is written to the line buffer 22 via the line buffer control circuit 21. The 16-bit word data supplied from the DMAC 20 is compressed by the black pixel detector 27 into 1-bit code information. That is, if the pixel is the same as the rightmost 16th bit of the 16 bits of one adjacent word, it is set to “1”; otherwise, it is set to “0”. Therefore, G
In the case of 4-mode facsimile, image information of 3456 bits per line in the A4 size is compressed to 3456/16 = 216 bits according to the embodiment, and the capacity of the line buffer is reduced to 1/16 of the conventional one. It is suitable for LSI.

As described above, the information written in the line buffer 22 is necessary as reference line information (the line immediately before the line to be encoded) in MR encoding. However, in the present embodiment, since the reference line information is compressed and stored in the line buffer 22, it is necessary to return the compressed information to the original information at the time of encoding. In this embodiment, a white pixel generator 28, a black pixel generator 29, and a second adjacent bit holding circuit 26B are provided to simplify this operation. These white pixel generators 28,
FIG. 3 shows a specific circuit of the white pixel generator 29 and the second adjacent bit holding circuit 26B.

The white pixel generator 28 has 16 buffers B0
To B15, and all inputs of each buffer are GN
D. The buffer is controlled by the compression code LW read from the line buffer 22 and the second adjacent bit holding circuit 26B, and is activated when LW is “1” and the output of the second adjacent bit holding circuit 26B is “0”, and is output to each output. Generates “0”. As a result, when LW = 0, 1
Information in which the 6-bit data D0 to D15 are all “0” is generated and input to the reference line FIFO circuit 23.

The black pixel generator 29 has 16 buffers IB
0 to IB15, and all inputs of each buffer are connected to VCC. Buffer is line buffer 2
2 is controlled by the compressed code LW read from the second and the second adjacent bit holding circuit 26B, and is activated when LW is “1” and the output of the adjacent bit holding circuit B is “1”, and generates “1” at each output. . As a result, when LW = 0, information in which 16-bit data D0 to D15 are all “1” is generated and input to the reference line FIFO circuit 23.

On the other hand, when LW = 1, that is, when the pixel is not the same as the adjacent bit, buffers B0 to B15, IB0
IB15 are not activated, and the output terminal of each buffer becomes high impedance. Note that a switching transistor may be used instead of the buffer. At this time, LW
The 16-bit information corresponding to = 1 must be read from the corresponding area of the image memory area 10 of the main memory 5 using the DMAC 20. Therefore, when LW = 1, the white pixel generator outputs a REQ (request) signal requesting the DMAC 20 to access the reference line information. The REQ signal generating circuit includes, for example, OR gates 34 and 36, an AND gate 33, an inverter 35, and a TF / F 32 as shown in FIG. This REQ
When one of the timing signals S3 and S4 described later becomes "1", the logic of the output CSEL of the T-type flip-flop 32 whose state is inverted and the LW signal satisfies [CSEL + CSEL × LW]. Occurs at times. When the REQ signal is generated from the white pixel generator 28,
The DMAC 20 sends the corresponding reference line address to the main memory 5 and fetches necessary 16-bit image information and inputs it to the reference line FIFO circuit 23. As a result, the 16-bit image information to be encoded is set in the encoding line FIFO circuit 24, and the corresponding 16-bit image information of the reference line is set in the reference line F.
It is set in the IFO circuit 23. At this timing, the rightmost 16th bit of the input 16-bit data is latched in the second adjacent bit holding circuit 26B.

FIG. 4 shows an internal block diagram of the line buffer control circuit 21 and the line buffer 22. The line buffer control circuit 21 includes multiplexers 40 and 42 for receiving the compressed code LX output from the black pixel detector 27,
A write address generation circuit 44 that generates a write address to the line buffer 22, a read address generation circuit 45 that generates a read address to the line buffer 22, and multiplexers 41 and 43 that input the write address and the read address. And a switching control circuit 48 for applying a switching signal to the multiplexers 40 to 43. The multiplexers 40 and 42 are connected to the line buffer and have a function of outputting the compressed code LW output from the line buffer. Line buffer 2
2 has two line buffer memories 46 and 47, the data input and output of which are connected corresponding to the multiplexers 40 and 42, and the address input terminals are the multiplexers 41 and 43.
Is connected correspondingly.

When a write address is supplied to the line buffer memory 46 via the multiplexer 41, the write address is written to the line buffer memory 46 via the compression code LX multiplexer 40 output from the black pixel detector 27. When writing the compressed code into the line buffer memory 46, the previously written compressed code LW is read from the line buffer memory 47. On the other hand, when the compressed code LX is written in the line buffer memory 47, the compressed code LW is read from the line buffer memory 46. As described above, by alternately executing the read / write to the two line buffer memories 46 and 47B, the MR encoding can be performed at high speed. The line buffer memories 46 and 47 need only have a capacity of 216 bits. The line buffer memory 46 is used to store image information of odd lines, and the line buffer memory 47 is used to store image information of even lines. Both the write address generation circuit 44 and the read address generation circuit may be counters capable of specifying addresses 0 to 215, and may be incremented one by one corresponding to one compression code.

FIG. 5 is an internal block diagram of the DMAC 20. The DMAC 20 needs a function of creating an address specifying the image memory area 10 in the main memory 5 for both the reference line and the encoding line. For this purpose, a reference line address register 50 and an encoding line address register 51 are provided, and the output is alternately applied to an address incrementer 53 via a multiplexer 52. The address incrementer 53 adds +1 to the address input via the multiplexer 52 and outputs the output via the address buffer 54 to the system bus 9.
To access the main memory 5 and store the incremented result in the corresponding address register 50, 51.
Feedback to As a result, the address register 5
The contents of 0 and 51 are alternately added by +1. The coding line address register 51 is used as an address register for reading out a line to be coded, and the line information read out from the main memory 5 by this address is input to the coding line FIFO circuit 24 via the data buffer 59. At the same time, it is input to the black pixel detector 27, compressed as reference line information for encoding the next line, and stored in one of the line buffer memories 46 and 47.

The host processor 1 shown in FIG.
At the start of A, an initial value is set in the reference line address register 50 and the coded line address register 51, and an end address of each line is set in the reference line end address register 55 and the coded line end address register 56. The multiplexer 57 alternately supplies the reference line end address and the coded line end address to the comparator 58 in response to the CSEL signal, compares the reference line end address with the contents of the address incrementer 53, and when one stage is completed, outputs a signal (END) indicating the end of the DMA. The data is transmitted to the host processor 1. The multiplexers 52 and 57 have the same CSE
Since the switching is controlled in response to the L signal, the comparator 58
Performs the comparison between the reference line address and the reference line end address and the comparison between the coded line address and the coded line end address alternately and synchronously. DM
The AC 20 further has a timing control circuit 60, the details of which are shown in FIG.

As shown in FIG. 6, the timing control circuit 60 uses four types of timing signals S1 to S4, each of which is output from each of four connected delay-type flip-flops (DFFs) 61 to 64. Taken out. Only the DFF 61 is set in the initial state or by a reset signal. The DFF 62 receives the output of the DFF 61 at the falling edge of the clock CK and generates S2. Similarly D
The FF 63 outputs the DFF 62 at the falling edge of the clock CK.
To generate S3. The output of DFF63 is C
The signal is input to the DFF 64 at the falling edge of the clock CK via the AND gate 66 which receives the output of the AND gate 65 which receives SEL and LW. The input of DFF61 is the input of DFF64, the output of DFF63 and R
The output of the OR gate 68 which receives the output of the AND gate 67 receiving the EQ signal as an input is applied. Where CSE
The L signal is, as shown in FIG. 3, the timing signals S3 and S3.
4 is the output of the flip-flop 32 whose state is inverted each time it becomes "1", and CSEL is the reaction output thereof. In this embodiment, when CSEL = "0", the reference line is selected, and when "1", the coding line is selected. The LW signal is a compressed code signal read from the line buffer, and LW is a reaction signal thereof.

In FIG. 6, S1, S2, and S3 are sequentially generated in this order in synchronization with one cycle of the clock. However, S4 is only generated when CSEL is "1" and LW is "1". Generated. That is, the S4 signal is generated only when the compression code read from the line buffer is "0" (when all the reference line information is white). In other words, when the compression code read from the line buffer is "1", S4 is not generated. At this time, the REQ signal shown in FIG. 3 is generated.
The output of the ND gate 67 becomes "1", and S1 is generated. That is, the DMAC 20 operates in two cycles of the cycle of S1 to S3 and the cycle of S1 to S4, and these are selected by the compression code “0” or “1”. The reason is that if the compression code is "0", a signal in which 16 bits are all "0" or all "1" is generated from the white pixel generator 28 or the black pixel generator 29. Since the signal may be input to the FIFO circuit 23, it can be executed in one clock period shown in S4. However, when the compression code is "1", the DMAC 2
This is because 16 bits of information corresponding to this must be read from the main memory 5 using 0, so that three clock periods of S1 to S3 are required.

Returning to FIG. 5, since the data buffer 59 must permit input of coded line information and input of reference line information when the compression code is "1", the RE
It is activated by the Q signal. On the other hand, since the address buffer 54 outputs the address necessary for reading the encoded line and the address necessary for reading the reference line when the compression code is "1", the timing signals S1 to S13 are generated. It only needs to be activated when there is. Therefore, the address buffer 54 is activated by the output of the OR gate 61 having S1 to S3 as inputs.

FIG. 7 is a block diagram showing another example of a bit operation circuit according to the present invention. In this example, a latch (adjacent bit holding circuit) 71 for holding an adjacent word and a 16-bit XOR operation circuit 72 are provided. ing. As a facsimile input image, a black and white image obtained by dithering an input signal may be used. In the converted image, regular data examples are continuously generated in units of 16 bits. Therefore, in such an image, when the XOR operation is performed in units of adjacent words, one word composed of all “0” is obtained. In this way, the data after the XOR operation is converted
By operating the flip-flop 74, "1" is used as the compression code when the data after the operation is all "0", and "0" is used as the code otherwise. In the generation of the coding line, the coding line can be easily generated by performing the inverse operation.

Here, in the above-described embodiment, an example of the MR system is described.
Applicable to the method. The present invention can also be used when compressing a large amount of information and storing it in a small-capacity memory.

[0028]

As described above, the present invention detects whether data within a certain pixel length has the same rule as that of adjacent data, writes the corresponding compressed code into the line buffer, and reads out the compressed code from the line buffer. When the compressed code is the same as the adjacent bit, it has a means for generating a white pixel or a black pixel of a fixed pixel length and sending it to the reference line, so that the capacity of the line buffer is compressed to within the conventional fixed pixel length. The bit data is sufficient, and there is an effect that the size can be greatly reduced. Therefore, according to the present invention, an effective compression effect can be obtained for both an image having many white pixels and an image having many black pixels due to the nature of the image. Needless to say, the present invention is also effective for a binary image generated according to a certain rule such as a dither image. Therefore, according to the present invention, it is possible to obtain a compression / expansion circuit that can be easily formed into an LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of an encoding / decoding circuit according to the present invention.

FIG. 2 is a block diagram of a bit operation circuit.

FIG. 3 is a block diagram of a white pixel generator and a black pixel generator.

FIG. 4 is a block diagram of a line buffer control circuit and a line buffer;

FIG. 5 is a block diagram of an internal configuration of a DMAC.

FIG. 6 is a block diagram of an internal configuration of a timing control circuit.

FIG. 7 is a block diagram of another example of the bit operation circuit according to the present invention.

FIG. 8 is a system block diagram to which the present invention is applied.

FIG. 9 is a block diagram of an internal configuration of a conventional control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Host processor 2 Encoding / decoding control circuit 3 Image printer 4 CRT 5 Main memory 6 Scanner 7 Communication controller 8 Magnetic disk 9 System bus 10 Image memory area 20 DMAC 21 Line buffer control circuit 22 Line buffer 23 Reference line FIFO circuit 24 Encoding line FIFO circuit 25 MR encoding circuit 26A First adjacent bit holding circuit 26B Second adjacent bit holding circuit 27 Bit operation circuit 28 White pixel generator 29 Black pixel generator

Claims (5)

[Claims] In a digital signal control circuit having an input / output digital signal encoding / decoding circuit and a line buffer into which the digital signal can be written, predetermined bits of the digital signal to be written to the line buffer Each data within the length is subjected to a certain operation with specific data adjacent to the predetermined bit, so that either the first compression code when all the data are the same or the second compression code when the data are not the same. A first circuit for creating the compressed code, a second circuit for writing and reading the compressed code created by the first circuit to the line buffer, and a compressed code read by the second circuit. In the case of the first compressed code, the data of a white pixel or a black pixel is obtained by performing a specific operation on a corresponding predetermined bit length and adjacent specific data. And generates and supplies the data to the encoding / decoding circuit.
And a third circuit for reading out the original data corresponding to the compressed code from the memory storing the original data and supplying the read data to the encoding / decoding circuit. Encoding / decoding circuit. 2. A first circuit compares 1-bit data of adjacent data with bit data of predetermined data, and outputs a first compression code when detecting that all of the predetermined data are the same pixel. 2. The digital signal encoding / decoding circuit according to claim 1, which is configured as follows. 3. The digital signal encoding / decoding circuit according to claim 1, wherein the first circuit is configured to perform an XOR operation on corresponding bit data of adjacent data and predetermined data. 4. A third circuit is obtained by inputting a means for generating a white pixel, a means for generating a black pixel, a first compression code and predetermined data, and calculating these inputs. 4. The digital signal encoding / decoding circuit according to claim 2, further comprising: means for selecting either the white pixel generating means or the black pixel generating means based on the signal. 5. The circuit according to claim 4, wherein said third circuit includes means for outputting a read signal to a memory in which original data is stored when the second compression code is input.
Digital signal encoding / decoding circuit.