JPH10112182A - Semiconductor device, semiconductor device system, and digital delay circuit - Google Patents

Abstract

[PROBLEMS] To realize a semiconductor device whose timing is adjusted so that data is output at a predetermined phase with respect to an external clock irrespective of characteristic variations, temperature changes, and power supply voltage changes. And An input circuit receives an external input signal and outputs a reference signal, an output circuit receives an output timing signal and outputs an output signal, and outputs an output timing from the output circuit to an external input signal. A delay circuit 21 for delaying a reference signal by a selected delay amount and outputting the delayed signal as an output timing signal; and a reference signal. And a delay control circuit 23 for selecting a delay amount of the delay circuit based on the comparison result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for outputting an externally input signal at a predetermined accurate phase, a semiconductor device system using such a semiconductor device, and a digital delay used therein. The present invention relates to a circuit, and more particularly, to a synchronous semiconductor memory that always outputs a signal at a predetermined phase with respect to an external clock regardless of a change in an ambient temperature or a power supply voltage.

[0002]

2. Description of the Related Art Usually, in a semiconductor integrated circuit (LSI),
A signal is input from the outside, a processing operation according to the input signal is performed, and an output signal is output. Therefore, at what timing an output signal is obtained with respect to an external input signal is important. In general-purpose LSIs, this timing is generally determined by specifications. For example, in a dynamic random access memory (DRAM), the timing at which data is output from a changing edge of an address signal and the data setup time for writing data are defined along with the maximum frequency of the address signal.

In recent years, C in computer systems
With the increase in the speed of the PU clock or the increase in the processing speed of various other electronic circuits, it is necessary to increase the speed of the interface. For example, if the clock is 1
Although some CPUs with a frequency of 00 MHz or more have appeared, the access speed and data transfer speed of a DRAM widely used as a main memory are operating speeds one digit lower. So 100MH
Synchronous D enabling data transfer speeds above z
Various new DRAM systems such as a RAM (SDRAM) have been proposed.

The SDRAM performs input / output of data in synchronization with a high-speed clock input from the outside. The SDRAM includes a plurality of units capable of inputting / outputting a plurality of bits of data in parallel. This interface converts the multi-bit data into serial data and speeds up the interface with the outside. There is a method to make it. Hereinafter, a pipeline type DRAM will be described as an example.

FIG. 1 is a block diagram of a 16M / 2-bank 8-bit wide SDRAM, which is an example of a pipelined synchronous DRAM (hereinafter simply referred to as an SDRAM). SDRAM is a general-purpose DRAM
In addition to the RAM cores 108a and 108b, a clock buffer 101, a command decoder 102, an address buffer / register & bank address select (hereinafter simply referred to as an address buffer) 103, an I / O data buffer / register 104, control signal latches 105a and 105b, Mode register 106, column address counter 107a,
07b. / CS, / RAS, / CAS, /
The WE terminal is different from the conventional operation in that the operation mode is determined by inputting various commands in a combination thereof. Various commands are decoded by a command decoder, and each circuit is controlled according to an operation mode. Also, / CS, / RAS, / CAS, /
The WE signal is also input to the control signal latches 105a and 105b, and its state is latched until the next command is input.

On the other hand, the address signal is supplied to the address buffer 1
03, and is used as a load address of each bank, and column address counters 107a, 107b
Used as the initial value of DRAM cores 108a, 1
The signal read from 08b is amplified by the I / O data buffer / register 104 and output in synchronization with the rising of the external clock CLK input from the outside. The same operation is performed for the input, and the input data is written to the I / O data buffer / register 104.

FIG. 2 is a diagram showing the timing of a read operation of a general SDRAM. The external clock CLK is a signal supplied from a system in which the SDRAM is used, and operates so as to take in various commands, address signals, input data, or output output data in synchronization with the rise of the CLK. .

When data is read from the SDRAM, command signals (/ CS, / RAS, / CAS,
/ WE signal), an active (ACT) command is input to a command terminal, and a row address signal is input to an address terminal. When this command and a row address are input, the SDRAM is activated, selects a word line corresponding to the row address, outputs cell information on the word line to the bit line, and amplifies it with a sense amplifier.

On the other hand, after the operation time (tRCD) of the portion related to the row address, the read command (R
input) and a column address. According to the column address, the selected sense amplifier data is output to the data bus line, amplified by the data bus amplifier, further amplified by the output buffer, and output to the output terminal (DQ). These series of operations are exactly the same as those of a general-purpose DRAM, but in the case of an SDRAM, a circuit related to a column address operates in a pipeline, and read data is continuously output every cycle. . Thus, the data transfer cycle becomes the cycle of the external clock.

There are three types of access times in the SDRAM, all of which are defined with reference to the rising edge of CLK. In FIG. 2, tRAC is a row address access time, tCAC is a column address access time, tA
C indicates a clock access time. This SDRA
When M is used in a high-speed memory system, t is the time from when a command is input to when data is first obtained.
Although RAC and tCAC are important, the clock access time tAC is also important in increasing the data transfer speed.

FIG. 3 is a block diagram for explaining a pipeline operation in the SDRAM, and shows a case where three stages of pipes are provided as an example. A processing circuit related to a column address in an SDRAM is divided into a plurality of stages along a processing flow, and each divided circuit is called a pipe. In the clock buffer 101, C
An internal clock signal to be supplied to each pipe is generated from the LK, and each pipe is controlled according to the supplied internal clock signal. Switches for controlling the transmission timing of signals between the pipes are provided between the pipes, and these switches are also controlled by the internal clock signal generated by the clock buffer 101.

In this example, in the pipe-1, the address signal is amplified by the column address buffer 116 and sent to the column decoder 118, and the information of the sense amplifier circuit 117 corresponding to the address selected by the column decoder 118 is transmitted. Is output to the data bus, and the data bus information is amplified by the data bus amplifier 119. Pipe-2 is only the data bus control circuit 120,
It is assumed that the pipe-3 is composed of only the I / O buffer 104. If the circuits in any of the pipes complete the operation within the clock cycle time, data can be sent out in a relay manner by opening and closing the switches between the pipes in synchronization with CLK. As a result, the processing in each pipe is performed in parallel, and data is continuously output to the output terminal in synchronization with CLK.

[0013]

FIG. 4 is a plan view of FIG. 1 to FIG.
FIG. 10 is a diagram for explaining a problem when the conventional SDRAM described in FIG. 1 is used in a high-speed memory system. In FIG. 4, tAC indicates the clock access time from the system clock CLK, and tOH indicates the output data holding time in the previous cycle or the next cycle. Considering the variation in the characteristics of the SDRAM, the temperature dependency, and the power supply voltage dependency, tAC and tOH do not coincide with each other and have a certain width. The time corresponding to this width is the time when the data is indeterminate,
This means a time during which it is not known what data is output, and is a time that cannot be used in a memory system, that is, a so-called dead band. In addition, although not shown,
The dead band includes the wiring delay time and variation on the board.

On the other hand, to take in (receive) the output of the SDRAM on the system side, the setup time (tS
I), a hold time (tHI) is required, and this time must be within the time when the data of the memory output is determined. The time is (tCLK + tOH-tA) from the figure.
C). For example, considering a system operating at 100 MHz, if the cycle time (tCLK) is 10 ns, the memory access time (tAC) is 6 ns, and the hold time is 3 ns, the subtraction time of 7 ns can be used on the system side. The total (tSI + tHI) of the setup time and hold time of the receiving logic in the system using the normal input circuit is 3 ns, and the remaining 4 ns is the system allowance time such as the signal delay on the board and the variation between the DQ terminals. Become. Considering the signal propagation time on the board, this value can be said to be a very severe value for the system. Needless to say, a higher-speed system requires increasingly strict timing adjustment. Therefore, it has become important to minimize the uncertainty time of the data shown in FIG.

In order to shorten the data uncertainty time, data is always output at a predetermined phase with respect to the external clock CLK even if there is a variation in characteristics, a change in temperature, or a change in power supply voltage. It is sufficient that the time tAC is always constant. If it is desired that the data output be performed in synchronization with the rise of the external clock CLK, the clock access time tAC may be always zero.

The necessity of outputting an output signal in synchronization with an externally input signal has been described above by taking a synchronous DRAM as an example.
Not only M but also common to many semiconductor devices. Various measures can be taken inside the semiconductor device so that each semiconductor device can perform a desired operation. However, when a processing result inside each semiconductor device is output, another semiconductor device may be used. Therefore, it is important to keep the output timing constant.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a semiconductor which outputs data at a predetermined phase with respect to an external clock CLK irrespective of characteristic variations, temperature changes, and power supply voltage changes. The purpose is to realize the device.
In particular, it aims at realizing a synchronous semiconductor memory in which the clock access time tAC is always kept constant.

[0018]

FIG. 5 is a diagram showing a basic configuration of a semiconductor device according to the present invention. As shown in FIG. 5, in the semiconductor device of the present invention, an input circuit 13 that receives an external input signal and outputs a reference signal, receives an output timing signal, and outputs an output signal at a timing corresponding to the output timing signal And an output timing control circuit 20 for controlling the output timing of the output signal from the output circuit 14 to a predetermined phase with respect to the external input signal. The circuit 20 has a selectable delay amount, delays the reference signal by the selected delay amount, and compares the phase of the reference signal and the phase of the output timing signal with the delay circuit 21 applied to the output circuit 14 as an output timing signal. And a delay control circuit for selecting a delay amount of the delay circuit 21 based on the comparison result of the phase comparison circuit 22. 2
3 is provided.

In the semiconductor device of the present invention, the amount of delay for the timing adjustment in the output timing control circuit 20 is not fixed, and the actual circuit signal is output from the input circuit 13 to the external clock signal (corresponding to the reference signal). In order to adjust the delay amount so as to have a predetermined phase relationship as compared with the above, the phase relationship of the output signal with respect to the external clock signal is determined even if there is a variation in the characteristics of the semiconductor device, a temperature change, a power supply voltage change, or the like. It is possible to maintain exactly the value of

The signal to be compared with the external clock signal needs to be a signal delayed by an amount equal to the amount of delay in the actual circuit. The external clock signal is input to the input circuit 13 of the semiconductor device and is subjected to processing such as amplification. Therefore, the external clock signal that can be compared is the external clock signal output from the input circuit, which has a phase difference from the actual external clock signal by the delay in the input circuit 13. Therefore, a dummy input circuit 24 that generates the same delay amount as the input circuit 13 is provided. , It is desirable to cancel the delay amount in the input circuit 13.

In the configuration shown in FIG. 5, the output of the delay circuit 21 is input to the dummy input circuit 24. Therefore, the comparison target signal compared with the external clock signal in the phase comparison circuit 22 does not include the delay in the output circuit 14. Of course, the phase relationship to be controlled is determined in consideration of this correction. However, the delay in the output circuit 14 is larger than the delay amount in other portions, and the characteristics of the semiconductor device vary, the temperature changes, the power supply voltage changes, and the like. However, there is a problem that the change in the delay amount in the output circuit 14 is relatively large and cannot be ignored.

FIG. 6 is a diagram for explaining this problem. Here, a description will be given assuming that the output is controlled in synchronization with the rising edge of the external clock signal CLK. The output timing signal which is supplied from the delay circuit 21 to the output circuit 14 and defines the output timing of the signal from the output circuit 14 takes into account the delay in the output circuit 14, and
Rises a predetermined amount before the rising edge of. If the delay amount in the output circuit 14 is a predetermined value, the CL
The output changes in synchronization with the rising edge of K. However, due to the above factors, the output circuit 14
, The output timing from the output circuit deviates from the rising edge of CLK. If there is such a variation, it is necessary to allow for the margin, and it becomes difficult to increase the speed accordingly.

To solve such a problem, the output signal of the output circuit 14 is input to the dummy input circuit 24, and the phase of the output signal is compared with the external clock signal. In order to perform the phase comparison, the output signal of the output circuit 14 needs to change. During normal operation, output data is output from the output circuit 14. This output data is a random signal, and the “high” level or the “low” level may be continuous. Therefore, in order to compare the phase of the output signal of the output circuit 14 with respect to the external clock signal during normal operation, the phase comparison circuit 22 determines whether the output signal has changed,
The phase control circuit 23 compares the phases only when the output signal changes, and controls the delay control circuit 23 so that the delay amount up to that point is maintained when the output signal does not change. Feedback control is performed based on the comparison result so that the phases match. As another configuration, an initialization operation is performed before starting a normal operation, and dummy data that changes in a predetermined cycle is output in the initialization operation. And performs feedback control so that the phases match. After the coincidence, the adjusted delay amount is maintained. Since the dummy data always changes in a predetermined cycle, the phase comparison circuit 22 can compare the phases by determining which direction the change is.

Further, as shown in FIG. 7, a dummy output circuit having the same characteristics as the output circuit 14 may be provided to compare the phase of the output signal of the dummy output circuit with the external clock signal. The semiconductor device of FIG. 7 is different from the configuration of FIG.
1 from the dummy output circuit 35.
And a dummy output signal output from the dummy output circuit 35 in accordance with the output timing signal.
4 in that it is input to a phase comparison circuit 32 via an external circuit 4 and is compared with an external clock signal from an input circuit.

With the configuration shown in FIG. 7, a signal suitable for phase determination independent of the output signal from the output circuit can always be output from the dummy output circuit. Therefore, the feedback control can be performed by always outputting the dummy data as described above. If the dermis data is a signal that changes more slowly than the cycle of the clock signal, the power consumption of the circuit can be reduced.

Further, a second output timing control circuit for the dummy output circuit is provided separately from the first output timing control circuit for the output circuit, and the output signal and the dummy output signal are synchronized with the external clock signal at the time of initialization. . This means that the output signal and the dummy output signal are also synchronized, and thereafter, the dummy output signal is fed back to the first output timing control circuit to perform control.
With such a configuration, even when the dummy output circuit is used, adjustment including the effect of the load connected to the actual output circuit can be performed.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, an embodiment in which the present invention is applied to a synchronous DRAM will be described. However, as described above, the present invention is not limited to a synchronous DRAM, but is synchronized with an externally input signal. The present invention can be applied to any semiconductor integrated circuit that outputs an output signal.

A synchronous DRAM according to an embodiment of the present invention.
(SDRAM) has the entire configuration as shown in FIG. FIG. 8 is a diagram showing the timing of the read operation of the SDRAM of the embodiment. As is apparent from a comparison between FIG. 3 and FIG. 8, the SDRAM of the embodiment has substantially the same configuration as the conventional SDRAM, but the configuration of the clock buffer 101 is different. In the SDRAM of the embodiment, the clock buffer 101 has an internal clock generation circuit 121 and an output timing control circuit 122. The internal clock generation circuit 121 is the same as a conventional SDRAM, generates an internal clock signal from an external clock CLK, and supplies it to the pipe-1 and the pipe-2. The output timing control circuit 122 has the basic configuration shown in FIG.
4 is output from the external clock CLK.
Is controlled to always have a predetermined phase.

FIG. 9 is a diagram showing the configuration of the output timing control circuit 122 according to the first embodiment, in which the external clock CLK is used.
, An output circuit 14, and a data output terminal 12 are also shown. As shown in FIG.
The output timing control circuit according to the embodiment includes an input circuit 13 that receives an external clock CLK input to the external clock input terminal 11 and a clock output from the output circuit 14 by delaying the CLK input from the input circuit 13. A DLL (Delay Lock Loop) circuit 40 for generating a prescribed output clock, a dummy input circuit 34 having the same circuit configuration as the input circuit 13, and a dummy output having a circuit configuration equivalent to the output circuit 14 Circuit 37
And a dummy signal wiring 36 provided between the DLL circuit 40 and the dummy output circuit 37 and equivalent to a signal wiring from the DLL circuit 40 to the output circuit 14, and a load connected to the data output terminal 12, and equivalent to the same. And a dummy output load 38 having an appropriate load.

The input circuit 13 is an electrostatic protection circuit (ESD)
131 and a current mirror circuit 132 for amplifying CLK
, Latch circuit 133, CLK control circuit 134, 1
/ N frequency divider 135. This input circuit 13
Since the external clock input circuit is widely used except for the / N frequency divider 135, the 1 / N frequency divider 135 will be described later, and a detailed description thereof will be omitted here.
Like the input circuit 13, the dummy input circuit 34 includes a dummy ESD 341, a dummy current mirror circuit 342,
Dummy latch circuit 343 and dummy CLK control circuit 34
4 and each circuit is made the same as that of the input circuit 13, and the signal delay amount is the same.

The DLL circuit 40 includes a CLK control circuit 134
A delay circuit 41a for delaying a signal input from the DUT by a selected amount, a dummy delay circuit 41b for delaying a signal input from the 1 / N divider 135 by a selected amount, and a 1 / N divider 135 and a delay circuit 41 based on the comparison result of the phase comparison circuit 42.
a and a delay control circuit 43 for selecting a delay amount of the dummy delay circuit 41b.

FIG. 10 is a diagram showing the circuit configuration and operation waveforms of the delay circuit 41a and the dummy delay circuit 41b. (1) shows the configuration of the delay circuit for one bit.
(3) is a time chart showing the configuration and operation when a delay circuit for one bit is connected in a plurality of stages, and (2) is a time chart showing the operation of the delay circuit for one bit. As shown in FIG. 10A, the one-bit delay circuit includes two NAND circuits 401 and 402 and an inverter 4.
It consists of 03. The operation of the one-bit delay circuit will be described with reference to FIG. 10 (2). The input φE is an activation signal, and the delay circuit operates when it is at “H” level.
(2) shows a state in which the signal φE becomes “H” and the signal can be received. The signal IN is the input signal to the 1-bit delay circuit, φN is the signal from the adjacent right side connected in multiple stages, OUT is the output signal of the 1-bit delay circuit, 4a-1 and 4a-2 Shows the waveform of the corresponding internal terminal in the circuit of (1). Therefore,
OUT becomes φN to the left.

When φN is “L”, OUT is always “L”. When φN is “H” and φE is “L”, O
UT is "H". When φN is “H” and φE is “H”, OUT becomes “H” if the input signal IN is “L”, and “L” if IN is “H”. In FIG. 10B, when IN rises from L to H in the state of φE = H and φN = H, the input signal IN is transmitted to the output OUT while being inverted by the NANAD gates 401 and 402 and the inverter 403. It is shown that it is being done.

FIG. 10 (3) shows an example in which the delay circuits for one bit in (1) are cascaded in a plurality of stages, and corresponds to an actual delay circuit. Although only three stages are shown in the figure, they are actually connected in multiple stages. Activation signal φE
Signal lines of φE-1, φE-2, φE-
The signals are controlled by a delay control circuit 43.

In the figure, the middle one-bit delay circuit is activated, and φE-2 is "H".
In this case, when the input signal IN changes from “L” to “H”, φE-1 and φE-3 of the leftmost one-bit delay circuit and the rightmost one-bit delay circuit are “L”. , The input signal IN is the NAND circuit 401
-1 and 401-3. On the other hand, φE-2 of the activated 1-bit delay circuit in the middle is used.
Is at "H" level, the input signal IN passes through the NAND circuit 401-2. Since the output OUT of the one-bit delay circuit on the right side is “H”, the input signal IN also passes through the NAND circuit 402-2 and is transmitted to OUT as a signal “L”. As described above, when OUT on the right side, that is, when φN is “L”, OUT is always “L”, so this “L” signal is sequentially transmitted to the NAND circuit and inverter of the delay circuit for one bit on the left side. Transmitted and taken out as the final OUT signal.

As described above, the input signal IN is transmitted so as to be folded back through the activated 1-bit delay circuit, and finally becomes the OUT signal. That is,
The delay amount can be controlled depending on which part of the activation signal φE is set to “H”. The delay amount for one bit is determined by the total signal propagation time of the NAND circuit and the inverter, and this time is the delay unit time of the DLL circuit. The entire delay time is an amount obtained by multiplying the delay amount for one bit by the number of stages to be passed.

FIG. 11 is a diagram showing the circuit configuration of the delay control circuit, and FIG. 12 is a time chart showing the operation thereof. As shown in FIG. 11, the delay control circuit is also configured such that one bit of the delay control circuit 430-2 surrounded by a dotted line is connected by the number of stages of the delay circuit. Signal φE. The delay control circuit 430-2 for one bit is connected to the NAND 432-
2 and a transistor 4 connected in series to both ends of a flip-flop constituted by an inverter 433-2.
35-2, 437-2, 438-2, 439-2, and a NOR circuit 431-2. Transistor 438
The gate of -2 is connected to the terminal 5a-2 of the preceding stage, and the gate of the transistor 439-2 is connected to the terminal 5a-5 of the following stage to receive the signals of the preceding and following stages. On the other hand, set signals φSE and φSO for counting up and reset signals φRE and φRO for counting down are connected every other circuit to the other transistor connected in series. As shown, in the delay control circuit 430-2 for one bit at the center, the transistor 435-2 is set to φSO, and the transistor 437-2 is set to φR
O, and the circuits on both sides of the delay control circuit 430-2 are connected to φSE and φRE, respectively. The NOR circuit 431-2 includes 5a-1 on the left side and 5a-
4 is input. Note that φR is a signal for resetting the delay control circuit, which temporarily goes to “L” level after power-on, and is thereafter fixed at “H”.

FIG. 12 is a diagram showing the operation of the delay control circuit of FIG. First, φR temporarily goes to “L”, and the terminals 5a-1, 5a-3, and 5a-5 go to “H”.
a-2, 5a-4 and 5a-6 are reset to "L".
When counting up, the count-up signal φSE
And φSO alternately repeat “H” and “L”. When φSE changes from “L” to “H”, 5a-1 is grounded and changes to “L”, and 5a-2 changes to “H”. In response to the change of 5a-2 to “H”, φE-1 changes from “H” to “L”. Since this state is latched by the flip-flop, the output φE-1 remains at “L” even if φSE returns to “L”. Then, in response to the change of 5a-1 to “L”, the output φE-2 changes to “L”.
From “H” to “H”. Since 5a-2 changes to "H", transistor 438 # 2 is turned on, and when [phi] SO changes from "L" to "H", 5a-3 is grounded to "L" and 5a-4 is "L". H ”. In response to the change of 5a-4 to “H”, φE-2 changes from “H” to “L”. Since this state is latched by the flip-flop, the output φE-2 remains at “L” even if φSO returns to “L”. Then, in response to the change of 5a-3 to “L”, the output φE-3 becomes “L”.
From “H” to “H”. In the figure, only φSE and φSO are output one pulse at a time, however, the delay control circuit is connected in multiple stages, and φSE and φSO alternately become “H”.
And “L” are repeated, the position of the stage where the output φE becomes “H” is sequentially shifted to the right. Therefore, the phase comparison circuit 42
When it is necessary to increase the delay amount according to the comparison result of, the pulses of φSE and φSO may be input alternately.

If the state where the count-up signals φSE and φSO and the count-down signals φRE and φRO are not output, that is, the state of “L”, is maintained, the output φ
The position of the stage where E becomes "H" is fixed. Therefore, when it is necessary to maintain the delay amount according to the comparison result of the phase comparison circuit 42, φSE, φSO, φRE, and φRO
Do not input the pulse of.

When counting down, φRE and φR
When the O pulse is input alternately, the position of the stage where the output φE becomes “H” is sequentially shifted to the left, contrary to the counting up. As described above, in the delay control circuit shown in FIG. 11, by inputting a pulse, the position of the stage where the output φE becomes “H” can be moved one by one. By controlling the delay circuit shown in FIG. 10C, the delay amount can be controlled so as to increase or decrease by one unit.

Here, the delay circuit and the delay control circuit will be described in more detail. In the first embodiment, a circuit as shown in FIG. 10 (3) is used as a delay circuit, and is controlled by a delay control circuit as shown in FIG. In order to realize a circuit in which the delay amount can be changed stepwise by a unit amount, a plurality of signal paths connected in series are provided, and a signal is selectively output from a part of the plurality of signal paths. In general, a delay line whose delay amount can be selected is used. In such a delay line, it is necessary to avoid a state in which any signal path is not selected even in a transient state in which a signal is output from an adjacent signal path in order to change the delay amount. Therefore, a delay control circuit for controlling such a delay line needs to always output a signal for selecting one of the signal paths even in a transient state. In the delay control circuit of FIG. 11, each stage outputs two complementary signals. That is, NAND
The output of the gate and the output of the inverter are complementary signals. Up to a certain stage, the complementary signal in one state is output, the subsequent stages output the inverted complementary signal, and the stage that outputs the inverted complementary signal first is shifted. In other words, the delay control circuit of FIG. 11 performs the same operation as the shift register. In the circuit of FIG.
Among the complementary signals of such a shift register, the R gate calculates the NOR of two different complementary signals adjacent to each other for each stage, and outputs its output to the selection signal of each stage in (3) of FIG. Connected to the wire. In the MOS transistor, generally, the falling speed from the logical value of “H” to the logical value of “L” is faster than the rising speed from the logical value of “L” to the logical value of “H”. In the circuit shown in FIG. 11, the output of the NOR gate whose input is a logical value of "L" indicates the selection position of the delay line. One of the inputs of this NOR gate changes to the logical value of "H". The input of "H" of the NOR gate, which indicates the position of the delay line to be selected later, changes to "L" at a faster speed. Therefore, before the output of the NOR gate, which previously indicated the selected position, stops indicating the selected position, the NO indicating the next selected position is not determined.
Since the output of the R gate will indicate the selected position,
A state in which none of the NOR gates indicates the selected position can be avoided.

FIG. 13 is a diagram showing an output change when the position of the NOR gate designating the selected position in the delay control circuit of FIG. 11 changes sequentially. As shown, the next selection signal rises before the previous selection signal falls.
Therefore, the problem that none of the paths of the delay line is selected does not occur. For example, in the circuit of FIG. 11, an AND gate having the nodes 5a-2 and 5a-3, 5a-4 and 5a-5 as inputs is provided, and the outputs thereof are φE-1 and φE-
A delay control circuit such as 2 can be considered, but such a circuit has a problem that the outputs of all the AND gates become “L” in a transient state.

FIG. 14 is a diagram showing an example in which an AND gate (a combination of a NAND gate and an inverter) is used instead of the NOR gate in the circuit of FIG. In this circuit, the input of the AND gate is a complementary signal that is different in every other stage. With such a configuration, two adjacent
The outputs of the AND gates simultaneously become "H", that is, a state in which the selected position is indicated. Since the two AND gates that indicate the selected position change one by one, one of the AND gates always remains “H”, and a state in which none of the AND gates indicates the selected position is avoided. In addition,
When the outputs of the two AND gates are at "H", in the delay line of (3) in FIG.
If the delay amount of the stage is small, it can be ignored.

The phase comparison circuit 42 is composed of two circuit parts, a phase comparison unit and an amplification circuit unit. 15 is a diagram showing a circuit configuration of the phase comparison unit, FIG. 16 is a time chart showing an operation of the phase comparison unit, FIG. 17 is a diagram showing a circuit configuration of the amplification circuit unit, and FIG. 6 is a time chart showing the operation of the unit. In FIG. 15, φout
And φext are an output signal and an external clock to be compared by the phase comparison circuit 42, and φout is based on φext.
Are determined, and φa to φe indicate output signals connected to the amplifier circuit. As shown in FIG. 15, the phase comparison unit includes flip-flop circuits 421 and 422 composed of two NAND circuits, latch circuits 425 and 426 for latching the state, and a circuit 424 for generating an activation signal for the latch circuit. , And a delay circuit 423 for one delay for obtaining a permissible phase value of the external clock φext.

In FIG. 16, (1) shows a signal φ to be compared.
This shows a case where out has a phase ahead of the comparison reference signal φext, and φout changes from “L” to “H” before φext. φout and φext are both “L”
At the time of terminal 6 of the flip-flop circuits 421 and 422
a-2, 6a-3, 6a-4, and 6a-5 are all at "H". When φout changes from “L” to “H”, both terminals 6a-2 and 6a-4 change from “H” to “L”. Then, φext changes from “L” to “H”, 1
The terminal 6a-1 changes from "L" to "H" with a delay by a delay, but no change occurs because the potentials at both ends of the flip-flop have already been determined. Eventually, 6a-2 is "L", 6a-3 is "H", 6a-4 is "L", 6a-
5 maintains “H”. On the other hand, in response to φext changing from “L” to “H”, φa of the circuit 424 changes from “L” to “H”, and a pulse temporarily changing to “H” level is applied to 6a-6. Is applied. This 6a-6
Is input to the NAND circuits of the latch circuits 425 and 426, the NAND circuit is temporarily activated, and the potential states at both ends of the flip-flop circuits 421 and 422 are taken into the latch circuits 425 and 426. Finally, φb is “H”, φc is “L”, φd is “H”,
φe becomes “L”.

Next, in (2), the phase of the comparison target signal φout and the comparison reference signal φext are almost the same, and φout is φ
A case where the signal changes from “L” to “H” almost simultaneously with ext is shown. This is the time when φout changes from “L” to “H” within the time difference between the rising point of φout and the rising point of 6a-1. In this case, first, when φext changes from “L” to “H”, the terminal 6a-3 of the flip-flop 421 changes from “L” to “H”. Because it remains
Conversely, 6a-4 changes from "H" to "L". Thereafter, 6a-1 changes from "H" to "L", but no change occurs because the state of the flip-flop 422 is already determined. Thereafter, since 6a-6 temporarily becomes "H", this state is stored in the latch circuit. After all,
φb is “L”, φc is “H”, φd is “H”, and φe is “L”.

Further, in (3), the phase of the comparison target signal φout is later than that of the comparison reference signal φext.
Is changed from “L” to “H” after φext. In this case, the two flip-flop circuits 421 and 422 change due to φext, and 6a-3
And 6a-5 change from "H" to "L". Finally, φb becomes “L”, φc becomes “H”, φd becomes “L”, and φe becomes “H”.

As described above, with reference to the rise time of φext, the rise time of φout has become “H” before that, has been almost simultaneous, or has been delayed by “H”.
Can be detected. These detection results are latched as values of φb, φc, φd, and φe, and whether to count up or count down the delay control circuit is determined based on the values.

FIG. 17 is a diagram showing the circuit configuration of the amplifier circuit section of the phase comparison circuit 42. The amplifying circuit section includes two parts: a JK flip-flop 427 and an amplifying section 428 composed of a NAND and an inverter. The signal φa is input to the JK flip-flop 427 from the phase comparing unit in FIG. It is designed to repeat "L" and "H". The amplifying unit 428 receives and amplifies the output signal of the JK flip-flop 427 and the signal from φb to φd, and outputs the amplified signal.

First, the operation of JK flip-flop 427 will be described with reference to the timing chart of FIG. When φa changes from “H” to “L” at time T1, the terminals 7a-17a-10 change from “L” to “H”. On the other hand, according to the change of 7a-1, 7a-5, 7a-6 and 7a-5
Although the state changes at a-7, no change occurs at 7a-8 because φa is "L". After all, output 7a-
9 does not change, and only 7a-11 changes from "L" to "H". Next, at time T2, φa changes from “L” to “H”.
, The terminal 7a-8 changes from "H" to "L" in reverse to the movement at the time T1, the terminal 7a-10 does not change since 7a-7 does not change, and the output 7a-9 changes from "L". It changes to "H" and 7a-11 does not change. As described above, the JK flip-flop circuit 427 outputs the output 7 according to the movement of φa.
a-9 and 7a-11 alternately repeat "H" and "L".

Next, the operation of the amplifier 428 will be described with reference to FIGS. FIG. 19 shows the comparison reference signal φ.
The case where the comparison target signal φout first changes from “L” to “H” with respect to the rise of ext is shown. In this case, the input signal from the phase comparison unit has φb “H” and φc
Is “L”, φd is “H”, and φe is “L”. After all,
7a-12 is fixed at "H", 7a-13 is fixed at "L", and φSO and φSE change according to the state of the JK flip-flop.
Because it does not change.

FIG. 20 shows a case where the comparison target signal φout changes from “L” to “H” almost simultaneously with the comparison reference signal φext. In this case, the input signals from the phase comparison unit are as follows: φb is “L”, φc is “H”, φd is “H”, φe
Is “L”. Eventually, 7a-12 and 7a-13 are fixed at "L", and φSO and φSE do not affect the output of the JK flip-flop to the amplification section.
SE, φRO, and φRE remain fixed at “L”.

FIG. 21 shows a case where the comparison target signal φout changes from “L” to “H” with a delay with respect to the rise of the comparison reference signal φext. In this case, the input signals from the phase comparator are as follows: φb is “L”, φc is “H”, φd
Is “L” and φe is “H”. Eventually, 7a-12 is fixed at "L", 7a-13 is fixed at "H", and φRO and φRO are fixed.
RE changes according to the state of the JK flip-flop, but φSO and φSE do not change because 7a-13 is "L".

FIG. 22 is a diagram showing a circuit configuration of the output circuit 14. As shown in FIG. In FIG. 22, Data1 and Data2
Is read from the cell array 115 and sense amplifier 1
17, data bus amplifier 119 and data bus control circuit 1
20 is a signal corresponding to the storage data output through the line 20. Data1 and Data2 are both "L" when the output data is "H", and are both "L" when the output data is "L". H ". It is also possible to take a high impedance state in which the output data is neither “H” nor “L”, in which case the data bus control circuit 120
Data1 is converted to “H” and Data2 is converted to “L”. φoe is an output signal of the delay circuit 40, and the output timing from this output circuit is controlled according to φoe. When φoe becomes “H”, Data1
It operates to output the information of and Data2 to the data output terminal 14. Now, assuming that “H” is output to the data output terminal 14, φoe changes from “L” to “H”, 8a-1 changes to “L”, and 8a-2 changes to “H”. When the transfer gate turns on, Data1 and Da
ta2 is transmitted to 8a-3 and 8a-6. After all, 8a
-5 becomes "L", 8a-8 becomes "H", the output P-channel transistor turns on, the N-channel transistor turns off, and "H" output appears at the data output terminal 14. become. When φoe becomes “L”, the transfer gate is turned off, and the output state up to that time is maintained.

FIG. 23 is a diagram showing a circuit configuration of the dummy output circuit 37, and further shows a capacitive element 38 provided as a dummy output load. FIG. 24 is a diagram showing the operation of the dummy output circuit 37 of FIG. 23, and shows the relationship between the internal clock signal and the dummy output signal of 8a-9. FIG. 24A shows a case where the 1 / N frequency divider 135 is not provided, and FIG. 24B shows a case where the frequency division ratio is 4.

As is apparent from comparison with the output circuit 14 of FIG. 22, the dummy output circuit 37 has a circuit configuration similar to that of the output circuit 14, but unlike the output circuit 14, the dummy output circuit 37 needs to output data. Therefore, both signals input to the transfer gate are fixed at "L". As a result, when outputting data, the dummy output 8a-9 always becomes "H". Further, Int-CLK is an internal clock, and in addition to opening and closing a transfer gate for controlling output timing from the dummy output circuit, a feedback inverter is inputted to one terminal of the NAND circuit as a NAND circuit. As shown in (1) of FIG. 24, when Int-CLK becomes “H”, the output circuit 14
By the same operation as described above, 8a-9 becomes "H". On the other hand, I
When nt-CLK returns to "L", the transfer gate is closed and at the same time, both 8a-3 and 8a-6 become "H".
, And the dummy output 8a-9 is returned to "L".

FIG. 24A shows a waveform without the 1 / N divider 135, and Int-CLK is a signal having the same cycle as the external clock signal CLK. FIG. 24 (1) shows a case where the load capacitance 38 of the dummy output load is very small. It is necessary to provide an appropriate load, and the rise and fall time of 8a-9 becomes very slow, and the operation of this dummy output circuit is limited by the rise and fall speed of 8a-9. Therefore, when the cycle of the external clock signal CLK is shortened, the dummy output circuit may not operate.

Therefore, in this embodiment, a 1 / N frequency divider 135 is provided as shown in FIG. 1 / N frequency divider 1
At 35, the output of the latch circuit 133 is frequency-divided, and the Int-CL shown in (2) of FIG.
Generate K. This Int-CLK is a signal that becomes “H” for one cycle for four pulses of the external clock signal. Such an Int-CL is used for the dummy output circuit.
By using K, it is possible to avoid the problem that the operable frequency of the dummy output circuit is limited by the rising and falling speeds.

When the 1 / N divider 135 is provided, the dummy output 8a-9 becomes as shown in (2) of FIG. 24. Therefore, the phase comparison between the dummy output and the external clock signal in the phase comparator 42 is as follows. Since the operation is performed once for four cycles of the external clock signal, power consumption is reduced accordingly.
The above is the description of each part of the SDRAM of the first embodiment. In the SDRAM of the first embodiment, the delay circuits 41a and 41a
The selection of the delay amount in b is performed by first resetting to select the initial position, and then shifting the selected position by one stage so as to have a predetermined phase relationship based on the result of the phase comparison. Therefore, a certain amount of time is required from when the delay amount is reset when the power is turned on to when the optimum delay amount is selected. Therefore, the SDR of the first embodiment
In the case of using AM, it is necessary to provide a predetermined initialization period after power-on, and to apply a predetermined number or more of external clock signals during that period.

In the SDRAM of the first embodiment, the internal processing system is divided into a plurality of pipes which are continuously processed.
Each works in parallel. In the above description, only the output is described, but the input is similarly piped. As a result, data input / output can be performed in synchronization with a high-speed external clock signal, and the transfer speed is greatly increased.

As described above, the SDR of the first embodiment
In AM, the data output timing is controlled so as to be at a predetermined phase of the external clock signal. Therefore, even if there is a change in temperature or power supply voltage during use, data is always at the predetermined phase of the external clock signal. It will be done synchronously. In addition, dummy circuits equivalent to the input circuit and the output circuit are provided and the phase is controlled so as to have a predetermined phase including a change in the amount of delay, so that the phase relationship can be controlled very accurately. is there. As a result, the transfer speed can be further increased.

In a current semiconductor device, a standard of an output signal is determined in order to obtain signal compatibility with other semiconductor elements. In SDRAMs and semiconductor devices used in combination with SDRAMs, "Low Voltage Transistor Tran
sistor Logic (LVTTL) "and" Series Stub Termination Log
ic (SSTL) "is generally used. An SDRAM is provided with an output circuit capable of outputting data in either of these two standards, and the output circuit is adapted to the two standards by applying a selection signal from outside. If the output circuit can be switched so as to be able to output with a different standard, the switching will change the characteristics of the output circuit. It has already been mentioned that it is important to provide a dummy output circuit equivalent to the output circuit and compare the phase with the signal passing through it because the change in the delay amount is large. In the second to fourth embodiments, the characteristics of the output circuit can be changed by the switching. This is an embodiment of the present invention.

FIG. 25 is a diagram showing a circuit configuration of a dummy output circuit of the SDRAM of the second embodiment. S of the second embodiment
In the DRAM, parts other than the dummy output circuit have the same configuration as the SDRAM of the first embodiment. As apparent from comparison with FIG. 23, the difference between the dummy output circuit of the SDRAM of the second embodiment and that of the first embodiment is that the driver circuit composed of an N-channel transistor and a P-channel transistor is denoted by a reference numeral. LVT indicated by 371
Two drivers are provided for the TL and the SSTL indicated by 372, and instruct the NAND circuit and the NOR circuit connected to the gates of the N-channel transistor and the P-channel transistor, respectively, which driver circuit to select. That is, the selection signal cttZ is being input.
The size of the P-channel transistor and the N-channel transistor forming the driver circuit 371 for CVTTL is different from the size of the P-channel transistor and the N-channel transistor forming the driver circuit 372 for SSTL, and each of the driver circuits is formed. The size of the transistor is appropriately defined depending on the output mode. The selection signal cttZ is a signal which becomes “H” when instructing the SSTL standard and becomes “L” when instructing the LVTTL standard. The voltage applied from the outside to the reference power supply terminal is a predetermined value Vref. It is generated by determining whether or not the above is true. In the circuit of FIG. 23, when the selection signal cttZ is “L”, the N level of the LVTTL driver circuit 371
The signals applied to the gates of the channel transistor and the P-channel transistor are changed by 8a-4 and 8a-7 to output a dummy signal, and the gates of the N-channel transistor and the P-channel transistor of the SSTL driver circuit 371 have Signals of “L” and “H” are applied, respectively, and both the N-channel transistor and the P-channel transistor of the SSTL driver circuit 371 are turned off, so-called a high impedance state. Conversely, when the selection signal cttZ is “L”,
The LVTTL driver circuit 371 enters a high impedance state, and the SSTL driver circuit 371 outputs a dummy signal.

As described above, the SDRAM of the second embodiment
Then, the characteristics of the dummy output circuit are switched. FIG.
FIG. 14 is a diagram showing a circuit configuration of a dummy output circuit of the SDRAM of the third embodiment. In the SDRAM of the third embodiment, parts other than the dummy output circuit are the same as those of the first embodiment.
It has the same configuration as AM.

In the SSTL standard and the LVTTL standard, the current flowing through the output transistor of the driver circuit is different.
The TL standard requires a larger current to flow. Since the current flowing in the output transistor changes depending on the dimensions of the transistor, it is necessary to make the transistor for the SSTL standard larger. Generally, a transistor of a driver circuit has a large size. If two driver circuits for SSTL and LVTTL are provided as shown in FIG. 25, a large area is required. Therefore, in the dummy output circuit of the SDRAM of the third embodiment, the LVTTL driver circuit 373 and the LVTTL
A driver circuit 374 capable of passing an SSTL standard current by matching the driver circuit 373 is provided.
When the L standard is instructed, the driver circuit 374 is set to the high impedance state, and when the SSTL standard is instructed, the LVTTL driver circuit 373 and the driver circuit 3 are set.
Both of them are in the operating state so that the SSTL standard current can flow.

In the SSTL standard and the LVTTL standard, the output load is also specified. Therefore, it is possible to switch the dummy output load as well.
It is. FIG. 27 is a diagram showing a circuit configuration of a dummy output circuit of the SDRAM of the fourth embodiment. SDR of Fourth Embodiment
In the AM, parts other than the dummy output load have the same configuration as the SDRAM of the third embodiment.

As shown in FIG. 27, the SDR of the fourth embodiment
In the dummy output circuit of AM, as the dummy output load, S
Two loads, an STL load 377 and an LVTTL load 378, are provided, and only one of them can be selectively connected to the dummy output terminals 8a-24 by the selection signal cttZ. 30p for SSTL load 377
The F capacitive element is a 50 pF capacitive element as an LVTTL load. Further, when the SSTL load 377 is selected, a terminating resistor 379 having one end connected to the power supply VccQ is connected to the dummy output terminals 8a-24. In the first to fourth embodiments, the dummy output circuit is "L"
Only the rising data which changes to "H" is output, and the phase of the rising edge with respect to the external clock signal is detected. However, the change in the amount of delay in the output circuit is
The case of the rising data in which the output signal changes from “L” to “H” is different from the case of the falling data in which the output signal changes from “H” to “L”. Therefore, in the configurations of the first to fourth embodiments, a phase difference occurs between the rising data and the falling data with respect to the external clock signal. Generally, as a driver circuit of an output circuit, FIGS.
The N-channel transistor and the P-channel transistor are connected in series between the power supply terminal and the ground as shown in (1), and one of the transistors is turned on according to data to be output. In such a driver circuit, a difference tends to occur particularly when the driving capabilities of the N-channel transistor and the P-channel transistor are unbalanced due to a difference in process conditions between the N-channel transistor and the P-channel transistor. The fifth embodiment is an embodiment in which such a problem is solved.

FIG. 28 is a diagram showing the configuration of the output timing control circuit of the SDRAM of the fifth embodiment. 9 and 2
As apparent from comparison of FIG. 8, the SDRAM of the fifth embodiment
The difference from the SDRAM of the first embodiment is that the delay circuit and the dummy delay circuit each have two delay circuits so that the phases of the rising data and the falling data can be adjusted independently. Hereinafter, points different from the first embodiment will be described.

The first delay circuit 41a-H is a delay circuit for adjusting the output timing of rising data, and the second delay circuit 41a-L is a delay circuit for adjusting the output timing of falling data. In both cases, CLK is input from the output of the CLK control circuit 134. The output of the first delay circuit 41a-H is input to the output circuit 14 and used as a timing signal when outputting "H" data. The output of the second delay circuit 41a-L is input to the output circuit 14 and used as a timing signal when outputting "L" data. Similarly, the first dummy delay circuit 41b-
H is a dummy delay circuit for adjusting the output timing of rising dummy data, and the second delay circuit 41b-L is a dummy delay circuit for adjusting the output timing of falling dummy data.
Int-CLK is input from the output of the / N divider 135. The output of the first dummy delay circuit 41b-H is input to the dummy output circuit 37 via the dummy signal wiring 36-H and is used as a timing signal when outputting "H" dummy data. The output of the second dummy delay circuit 41b-L is input to the dummy output circuit 37 via the dummy signal line 36-L, and is used as a timing signal when outputting "L" dummy data. Each delay circuit is made in the same way.

The delay control circuit comprises two circuits 43-H
And 43-L, each having the configuration shown in FIG. The output of the delay control circuit 43-H is
Of the delay circuit 41a-H and the first dummy delay circuit 41b-H are selected.
The output of L selects the amount of delay of the second delay circuits 41a-L and the second dummy delay circuits 41b-L.

FIG. 29 is a diagram showing the configuration of the phase comparison circuit in the fifth embodiment. As is apparent from comparison with FIGS. 15 and 17, the difference from the first embodiment is that the signal φ is provided by the signal data before the comparing section of the phase comparator.
A switch circuit 412 for always setting “L” and “H” of ddq to “H” is provided, and two amplifying units 414 for “H” output and amplifying unit 415 for “L” output are provided. That is the point.

In the switch circuit 412, for example,
When data outputs “H” as “H”, φdd
q also changes from “L” to “H”. Since the data is “H”, the transfer gate 416 is turned on and φdd
q is input to the phase comparison unit 413 as a signal φout.
Conversely, when the data is “L”, the transfer gate 417 is turned on, so that a signal obtained by inverting φddq is input to the phase comparison unit 413 as the signal φout. As described above, the input φout of the phase comparison unit 413 is always input as a signal that changes from “L” to “H”. Note that the same circuit as that shown in FIG. 15 is used as the phase comparison unit 413.

Each of the two amplifiers 414 and 415 has the same configuration as the circuit configuration shown in FIG.
The difference is that the NAND gate to which φe is input as a 3-input gate can be controlled by the signal data. When the data is “H”, the “H” output amplifying unit 414 is activated and operates, and when the data is “L”, the “L” output amplifying unit 415 is activated and operates. The internal operation is the same as that of the circuit of FIG.

FIG. 30 shows a dummy output circuit 3 according to the fifth embodiment.
7 is a diagram showing a configuration of FIG. The dummy output circuit 37 includes first and second dummy delay circuits 41b-H, 41b-L
, Two activation signals .phi.doeH and .phi.doeL, which are the timing signals outputted from. φdoeH is an activation signal used when outputting “H”.
doeL is an activation signal used when outputting "L". Which activation signal to use is determined by the signal da
selected by ta and / data.

Now, assuming that data is "H" and / data is "L", φdoeH becomes valid and terminal 10- is operated so that the upper transfer gate in the figure operates.
A switching signal of 1 and 10-2 is output. Conversely, when data is "L" and / data is "H", φdoeL becomes valid, and a switching signal for terminals 10-10 and 10-11 is output so that the lower transfer gate in the figure operates. Once the data is output to the dummy output circuit, it is latched and held by the latch circuit. Therefore, even when the activation signal becomes "L", the output is maintained until the next activation signal is input.

The activation signals φdoeH and φdoeL
Instead of the first and second delay circuits 41a-H, 41
The output circuit 14 has the same configuration as that of FIG. 26 except that a timing signal output from aL is input. FIG.
FIG. 1 is a waveform chart showing the operation of each unit in the fifth embodiment. The upper side shows the case of "H" output, and the lower side shows the case of "L" output.

In the case of "H" output, the external clock signal CL
K changes from “L” to “H”, and the signal is input to the input circuit 13.
Amplified by φ1 / N is a signal that has passed through the frequency divider 135 and is input to the dummy delay circuits 41b-H and 41b-L. φdoeH is a signal after passing through the dummy delay circuit 41b-H and becomes an activation signal input to the dummy output circuit 37. The activation signal activates the dummy output circuit 37 to output a dummy output 10-9. This signal is input to the dummy input circuit 34, and the phase comparison circuit 4
2 input signal φout. After all, the phase comparison circuit is
The rising edge of (a) surrounded by a circle is compared with the rising edge of (b) surrounded by a circle which is the input signal φout of the phase comparison circuit.

In the case of the "L" output, the description up to φ1 / N is the same as above, and φdoeL is a signal that has passed through a dummy delay circuit 41b-L different from the above, and this signal is a dummy output as an activation signal. The dummy output circuit 37 outputs “L” in response to the input to the circuit 37. This signal is input to the dummy input circuit 34 and becomes φddq. This is inverted by the switch circuit 412 in FIG. 29 and is input to the phase comparison circuit 42 as a signal φout. Eventually, the phase comparison circuit starts with the rising edge of (a)
The input signal φout of the phase comparison circuit is compared with the rising edge of (c) surrounded by a circle.

As described above, in the fifth embodiment, since the delay amount can be controlled separately for the "H" output and the "L" output, the clock access time at the "H" output and the "L" output
It is possible to match the clock access time at the time of output. As a result, the timing margin in a system using this SDRAM is expanded, and the system can operate at high speed.

In the first to fifth embodiments, a delay circuit for outputting output data, a dummy delay circuit similar to the output circuit, a dummy output circuit, and a dummy load similar to a load connected to the output terminal are provided. And a dummy output signal similar to the output signal actually output is generated, and the phase of the dummy output signal is compared with that of the external clock signal. As a result, the phase relationship between the output signal and the external clock signal is maintained very accurately as compared with the conventional example. But,
In a system in which such a semiconductor device is used, the layout of wiring actually connected to the output terminal is not constant, and the load (capacitance, output impedance) is rarely always constant. Therefore, the load of the actual output circuit and the dummy load rarely coincide with each other, and a slight temporal error occurs between the actual output waveform and the dummy output waveform.

FIG. 32 is a diagram for explaining the occurrence of such an error. The delay circuit operates to delay the output timing signal after the operation time completion time T2 of the input circuit with reference to the rising time T1 of the external clock signal CLK, and outputs data from the output circuit. Here, the time required for this is T4. Here, the clock access time is indicated by T6. Even if a similar dummy delay circuit is manufactured, there is a slight error, and even if the same position is selected, a difference occurs in the delay amount. Further, there is also a difference in the delay amount due to a manufacturing error of the dummy output circuit and the dummy load, so that the delay amount of the dummy circuit is T5. The error is indicated by T7 in the figure.

Such an error is small, and such a small time lag has not conventionally been a problem.
In recent high-speed systems, this slight error has come to affect the operating speed limit, which has become a problem. The sixth embodiment is an SDRAM in which such a small error is reduced. In the first to fifth embodiments, the same delay amount is selected for the delay circuit and the dummy delay circuit according to the selection signal from the common delay control circuit. On the other hand, in the sixth embodiment, a phase comparison circuit and a delay control circuit are separately provided for the delay circuit and the dummy delay circuit, respectively. During the initialization period immediately after power-on, a considerable number of dummy cycles are performed. In this dummy cycle, dummy data is also output from the output circuit, and the delay circuit is controlled so that the phases of the dummy data and the external clock signal are synchronized. . Independently of this, the dummy delay circuit is controlled such that the phases of the dummy data output from the dummy output circuit and the external clock signal are synchronized. In this state, the delay amount of the delay circuit is controlled to a value at which the phase of the output data from the output circuit and the phase of the external clock signal including the effect of the load actually connected are synchronized. Similarly, the dummy delay circuit is controlled to a value at which the phases of the dummy output data and the external clock signal are synchronized. In this state, if dummy output data is input to the phase comparison circuit on the normal delay circuit side, the output data and the phase of the external clock signal are controlled so that they follow even if they fluctuate thereafter. become. Such a configuration can be applied to the SDRAM of the first embodiment shown in FIG. 9, but the sixth embodiment described below applies such a configuration to the SDRAM of the fifth embodiment of FIG. 26.
This is an example applied to a DRAM.

FIG. 33 is a block diagram of the SDRAM of the sixth embodiment. As shown in the figure, in the sixth embodiment, a DLL circuit 44 for generating a timing signal for defining an output timing of the output circuit 14 to which normal data is output, and an output of a dummy output circuit 37 to output a dummy output are provided. A dummy DLL circuit 45 that generates a dummy timing signal that defines timing is provided. The DLL circuit 44 includes an “H” delay circuit 441 a and an “L”
A delay circuit 441b, a phase comparison circuit 442, and a delay control circuit 443a are provided. Further, the dummy DLL circuit 45 includes an “H” dummy delay circuit 4.
51a, an "L" dummy delay circuit 451b, a phase comparison circuit 452, and a delay control circuit 453a are provided. Further, dummy input circuits 34c and 34d are provided corresponding to the DLL circuit 44 and the dummy DLL circuit 45, respectively. A signal corresponding to the external clock signal from the input circuit 13 is input to each delay circuit. Also, a signal from the input circuit 13 and a corresponding signal from the dummy input circuit are input to each phase comparison circuit. The power supply voltage VccQ is applied to the output circuit 14, and an output timing signal from the DLL circuit 44 is supplied. The output of the output circuit 14 is connected to the output terminal 12 and the switching circuit 3
9. The output terminal 12 is connected to a board wiring 151 and an input circuit receiver 152 of another LSI, and these become an actual output load. Similarly, the power supply voltage VccQ is applied to the dummy output circuit 37, and a dummy output timing signal from the dummy DLL circuit 45 is supplied. The output of the dummy output circuit 37 is a dummy output load 3
8 and to the dummy input circuit 34d.
It is supplied to the switching circuit 39. The switching circuit 39
The signal supplied to the dummy input circuit 34c is switched between the output of the output circuit 14 and the output of the dummy output load 38. The dummy circuit described above and the normal circuit corresponding to the dummy circuit are configured to be similar with the same circuit configuration.

In addition, a dummy data generating circuit for generating dummy data for forcibly outputting "L" and "H" outputs from the output circuit 14 and the dummy output circuit 37 in a dummy cycle immediately after power-on. 53, a power-on detection circuit 52 for detecting power-on, and a command decoder circuit 5
1 is provided. Hereinafter, the operation of the circuit of the sixth embodiment will be described.

When the changing edge of the output signal and the dummy output signal is earlier with reference to the rising point of the external clock signal, the phase comparators 442 and 452 reversely increase the delay amount of the delay circuit. If the time is later than the rising edge of the external clock signal, control is performed in a direction to reduce the delay amount. Of course, this control is performed independently for both the "H" and "L" transition edges.

In a memory system using such an SDRAM, immediately after the system power is turned on, the memory system starts a clock operation to check and adjust the operation of various logics and PLL circuits mounted on the system.
A considerable number of dummy cycles are performed and an external clock signal comes in. During this dummy cycle, by repeating the operation of shifting the delay amount of each delay circuit so that the changing edge of the output signal and the dummy output signal has a predetermined phase with respect to the external clock signal, the DLL circuit and the dummy D
The LL circuit can be adjusted. However, immediately after the power is turned on, since no information is written in the memory, the output signal and the dummy output signal are constant, and the adjustment operation cannot be performed as it is. Therefore, it is necessary to internally generate data for adjusting the delay circuit in the dummy cycle. In this embodiment, for this purpose, a dummy data generation circuit 53 is newly provided, and the output waveforms of the power-on detection circuit 52 and the command decoder circuit 51 which are provided in the conventional SDRAM before are forcibly applied. Generates dummy data and adjusts the delay circuit.

FIG. 34 is a diagram showing a circuit configuration of a dummy data generation circuit according to the sixth embodiment. The dummy data generation circuit includes two parts, an activation signal generation unit 371 and a flip-flop unit 372. Activation signal generator 3
71, a signal φext obtained by amplifying the external clock signal CLK by the input circuit and φR indicating that the power is turned on.
And a signal φMRS that completes the initialization of the memory and actually starts the operation. These operations will be described with reference to the operation waveforms in FIG.

At time T1, the Vcc voltage is applied and V
The cc voltage rises. After a while, the power-on detection circuit 52 operates to output φR. When this signal is received by the dummy data generation circuit 53, φSW becomes “H” and / φS
W becomes "L". Next, at time T2, φext as a reference signal is input from the outside. With this signal, the flip-flop unit 372 outputs φD and / φD at twice the cycle of the external clock signal. These signals are input to an output circuit and a dummy output circuit and used as output data.

In the case of the SDRAM, it is necessary to set the operation mode in the mode register in the memory before starting the actual operation. In order to set the operation mode in the mode register, the setting is to be performed by inserting a mode register set instruction. When this command is received, the command decoder 51 outputs a signal φMRS. Assuming that φMRS is output at the time of T3, receiving this signal,
φSW becomes “L” and / φSW becomes “H”, and 10a-
2 is constant. Thereafter, the dummy data has a constant value.

FIG. 36 is a diagram showing a circuit configuration of the output circuit 14 of the sixth embodiment, and FIG. 37 is a time chart showing the operation thereof. The dummy output circuit 37 has the same circuit configuration as the output circuit, and is similar in size only to a small size. Therefore, the operation is exactly the same. The dummy data generated by the dummy data generation circuit 53 is output to the output circuit 14.
Is input to The output circuit 14 includes a high impedance control unit 141, a dummy data switch unit 142, and an output amplification unit 143. The dummy data is input to the high impedance control unit 141. / ΦZ is a signal for setting the output to a high impedance state. When the output is set to high impedance, / φZ is set to “L”.
It becomes invalid during the dummy cycle period immediately after power-on in which W is "H", and 12a-1 becomes "L" and 12a-2 becomes "H". On the other hand, since / φSW is “L”, the dummy data switch section 142 is in a state of passing the dummy data φD. Conversely, the signal DB of the actual data bus is not swept out to 5a-11 and 5a-12 since φSW is “H”.

In this state, since dummy data φD is valid, when φD is “H”, 5a-11 and 5a-11
a-12 both become "H". External clock signal φex
t in synchronization with the output circuit activation signal φoe (DLL circuit 4
4) is "H", "H" is output as an output signal. Conversely, when φD is “L”, RI and φoe 5a-11 and 5a-12 are both “L”.
Is "H", "L" is output as an output signal.

As described above, by using the dummy cycle immediately after the power is turned on, the time when the external clock signal rises and the time when the output signal becomes “H” and “L” become D.
The time when the dummy output signal becomes “H” and “L” by the LL circuit 44 coincides with the dummy DLL circuit 45. Of course, since the waveform of the output signal and the waveform of the dummy output are slightly different, the setting values of the respective delay circuits of the DLL circuit 44 and the dummy DLL circuit 45 are different, but at this time, the external clock signal, the output signal, This means that the three signals of the dummy output signal are synchronized.

After the end of the dummy cycle (after φMRS is output), the memory operation is actually started, so that the data stored in the memory is output to the output terminal 12. These data are completely random, and it is not known what data is output. Furthermore, SD
In the RAM, the data input terminal and the data output terminal 12
Since it is a / O common terminal, input data may come in. That is, the system of the DLL circuit 44 cannot be used for adjusting the delay circuits 441a and 441b. Therefore, the switching circuit 39 is switched, and DL
The comparison target signal of the L circuit 44 is switched from the output signal to the dummy output signal.

FIG. 38 is a diagram showing a circuit configuration of the switching circuit 39. Two transfer gates in which an N-channel transistor and a P-channel transistor are connected in parallel are provided, and control is performed so that one of them is made to pass through by a signal φSW. As a result, when the temperature or the like fluctuates during the memory operation and it is necessary to adjust the delay amount of the delay circuit of the DLL circuit 44, the dummy output signal is used as the comparison target signal. Since the three waveforms of the external clock signal, the output signal, and the dummy output signal were matched during the dummy cycle immediately after the input, the deviation of the waveform between the external clock and the dummy output signal was detected.
If the adjustment is made based on the detection result, the output signals will also match.

In the sixth embodiment, it is possible to synchronize the external clock signal and the output signal by a series of operations, including the difference between the wiring of the board actually used and the wiring load. As a result, a sufficient margin is secured even in a system operating at a higher speed, and the operation is stabilized even in a system operating at a higher speed. In the first to sixth embodiments, a dummy output circuit is provided to output dummy data, and the phase of the output signal is compared with the phase of the external clock signal. It is also possible to compare the phases of the signal and the external clock signal. The seventh embodiment is an example in which the output signals are compared in phase.

FIG. 39 is a diagram showing the configuration of the output timing control circuit of the seventh embodiment. As shown in FIG. 39, the output timing control circuit of the seventh embodiment
, Output circuit 14, delay circuit 501, delay control circuit 502, phase comparison circuit 503, input circuit 1
3, a 位相 phase shift circuit 504 for generating a シ フ ト shift clock having a 180 ° phase difference from the clock signal CLK1 output from the third clock signal CLK1, the first and second dummy input circuits 505 and 506, the first, second and Third latch circuit 507,5
08, 509. Input circuit 13 and output circuit 14
Is the same as that of the embodiment described so far. In the seventh embodiment, the phase comparison circuit 503 determines whether the output signal has changed, and when the output signal does not change, the hold (HOL)
D) A signal is output, the phase is compared only when it changes, and a control signal (U) instructing the delay control circuit 502 to increase or decrease the delay amount based on the comparison result.
(P / DOWN) signal. 1/2 phase shift circuit 504 and first, second and third latch circuits 507,
08 and 509 are circuits that generate signals for the phase comparison circuit 503 to determine whether the output signal has changed and to compare the phases. As for the latch circuit, a normal latch circuit is used and its configuration is widely known,
Here, the description is omitted.

FIG. 40 is a diagram showing a configuration example of the first delay circuit 501 and the delay control circuit 503. In addition,
The second delay circuit 502 is also controlled by the same output of the delay control circuit 503, but is not shown here. As illustrated, the delay circuit 501 includes an inverter array 521 in which a plurality of inverters are connected in series, and a plurality of AND gates 522-1 provided such that one of the inputs receives the output of each of the two stages of the inverter array 521. , 522-
, 522-n, and the output of each AND gate is applied to the gate, the source is grounded, and the N-channel transistors 523-1, 523- are commonly connected to the drain. 2, ..., 523-n
, A resistor 524 connected between the signal line to which the drains of the N-channel transistors are commonly connected and the high potential side of the power supply, and an input connected to the signal line and the internal clock CLK2. And a buffer 525 that outputs The delay control circuit 502 includes an up / down counter 526 and a decoder 527, and the up / down counter 526 outputs the hold signal H
When OLD is at "L", the count operation is not performed. When the hold signal HOLD is at "H", the count operation is performed in synchronization with the rise of the φ1 / 2 CLK1, and when the up / down signal UP / DOWN is at "H". It counts up and counts down when it is "L". Decoder 52
Reference numeral 7 decodes the output of the up / down counter 29 to set one of the outputs to "H" and the other output to "L". When the up / down counter 526 counts up, the output position to be set to “H” is shifted to the right, and when the countdown is performed, the output position to be set to “H” is shifted to the left. The output of the decoder 527 is output to each of the AND gates 522-1, 522-2,.
And only the AND gate to which "H" is input from the decoder 527 is activated. The signal input to the activated AND gate among the outputs of the inverter train is the internal clock CLK2.
And the number of stages passing through the inverter row changes depending on which AND gate is activated, so that the delay amount of the internal clock can be selected. Therefore, the adjustment unit of the delay amount control is the delay amount for two inverters. It is necessary to consider the delay control circuit 503 so that any one of the paths is always selected by the delay circuit 501, as described with reference to FIGS.

FIG. 41 is a diagram showing the configuration of the 1/2 phase shift circuit 504. As shown in FIG. 41, the 1/2 phase shift circuit 504 includes a current mirror circuit 511, a clock input buffer circuit 512, first and second 1/2 delay circuits 513 and 516 having the same configuration,
Buffer circuits 514 and 517, and phase comparison circuit 518
, A delay control circuit 519, and a buffer circuit 515 for outputting the φ1 / 2 clock signal φ1 / 2CLK1. The current mirror circuit 511 and the clock input buffer circuit 512 are parts constituting an input circuit. First
And the second 1/2 delay circuits 513 and 516 are digital delay lines whose delay amounts can be selectively changed, and are controlled so as to have the same delay amount. The phase comparison circuit 518 compares the phase of the clock signal output from the buffer circuit 512 with the phase of the clock signal output from the buffer circuit 517, and compares the phase comparison result with the delay control circuit 519.
Output to Based on the comparison result of the phase comparison circuit 518, the delay control circuit 519 determines whether the phases of the clock signal output from the buffer circuit 512 and the clock signal output from the buffer circuit 517 match each other by the first and second 1/1.
The 2φ delay circuits 513 and 516 are controlled. The circuit shown in FIG. 42 described later is used as the phase comparison circuit 518, and the circuit shown in FIG. 40 is used as the delay circuits 513 and 516.

The clock signal output from the buffer circuit 512 is delayed by the first delay circuit 513,
Second delay circuit 516 via buffer circuit 374
And is delayed by the same amount as the delay amount of the first delay circuit 513, and is input to the phase comparison circuit 518 via the buffer circuit 517. The phase comparison circuit 518 compares the phases of the clock signals output from the buffer circuits 512 and 517, and the delay control circuit 519 uses the first and second delay circuits so that the two phases match based on the comparison result. The delay amounts of 513 and 516 are changed. When the two phases match, a path from the first delay circuit 513 to the input to the second delay circuit 516 via the buffer 514, and a phase comparison circuit 518 from the second delay circuit 516 via the buffer 517. Is the same, so that the second delay circuit 51
The phase of the signal input to the first delay circuit 513 is shifted from the phase of the signal input to the first delay circuit 513 by exactly a half cycle. Therefore, the phases of the clocks output from the buffer circuits 514 and 517 are also shifted by a half cycle, and
15 outputs a 1/2 shift clock φ1 / 2 obtained by shifting the clock signal by a half cycle. As described above, by using the 1/2 phase shift circuit as shown in FIG. 40, a 1/2 shift clock φ1 / 2 obtained by exactly shifting the clock signal by 1/2 phase can be obtained.

In the seventh embodiment, the 1/2 shift clock φ1 / 1 obtained by exactly shifting the clock signal by 1/2 phase is used.
The circuit as shown in FIG. 41 is used because 2 is required in other parts. However, in the seventh embodiment, since a signal whose phase is exactly shifted by 1/2 is not necessary, an inverter may be used simply. . In any case, the latch circuit 507 latches the output of the dummy output circuit 505 in synchronization with the rise of CLK1, the latch circuit 508 latches the output of the dummy output circuit 506 in synchronization with the fall of CLK1, and the latch circuit 509. Latches the output of the latch circuit 508 in synchronization with the fall of CLK1. Therefore, the latch circuit 509
Latches the output of the dummy output circuit 506 one cycle after the fall of CLK1 latched by the latch circuit 508. The output of the latch circuit 507 is input to the phase comparison circuit 503 as RG1, the output of the latch circuit 508 is input as RG2, and the output of the latch circuit 509 is input as RG0.

FIG. 42 is a circuit diagram showing a configuration of phase determining circuit 503. The operation of phase determining circuit 503 will be described with reference to FIGS. When there is no phase shift, the output signal is the clock signal C output from the input circuit 13.
It changes at the rising edge of LK1φ1.
The positions indicated by arrows in the figure are the timings at which each latch circuit latches the output signal, and RG0, RG1, R
G2. State 1 in FIG. 43 is a state in which the output signal remains at “H” and does not change, and RG0, RG1, RG
2 are all "H", the hold signal HOLD becomes "L" and the phase shift cannot be determined, so that the count operation is not performed. Similarly, state 2 is when the output signal remains at “L” and does not change.
0, RG1, and RG2 are all "L", and similarly, the hold signal HOLD becomes "L", and the count operation is not performed.

In states 3 and 4 shown in FIG. 44, the output signal changes from "H" to "L".
If the changing edge of the output signal is behind the rising edge of LK1, RG0, RG1, and RG2 become "H", "H", and "L", respectively. In this case, the hold signal HOLD becomes “H”, the up / down signal UP / DOWN becomes “L”, and the delay circuit 501
And 502, the amount of delay is reduced. CLK as in state 4
When the changing edge of the output signal is ahead of the rising edge of 1, RG0, RG1, and RG2 become "H", "L", and "L", respectively. In this case, HOL
D becomes "H", UP / DOWN becomes "H", and the delay amount of the delay circuits 501 and 502 is increased.

In states 5 and 6 shown in FIG. 45, the output signal changes from "L" to "H".
When the changing edge of the output signal is behind the rising edge of LK1, RG0, RG1, and RG2 become "L", "L", and "H", respectively. In this case, H
OLD becomes "H", UP / DOWN becomes "L", and the delay amount of the delay circuits 501 and 502 is reduced. If the changing edge of the output signal is ahead of the rising edge of CLK1 as in state 6, RG
0, RG1, and RG2 are "L", "H", "H", respectively.
become. In this case, HOLD becomes “H” and UP /
DOWN becomes “H”, and the delay circuits 501 and 502
Increase the amount of delay.

Each of the above states and RG0, RG1,
The values of RG2 and the necessary operations are shown in the truth table of FIG. As described above, in the output timing control circuit of the seventh embodiment shown in FIG. 39, the phase of the output signal is compared with the phase of the clock signal, and the output signal is controlled so that the phase of the output signal is synchronized with the clock signal. The output signal is a random signal, and the “high” level or the “low” level may be continuous. The phase comparison circuit 503 of the seventh embodiment determines whether the output signal has changed. Only when the output signal does not change, the delay control circuit 502 controls so that the delay amount up to that point is maintained. When the output signal does not change, the delay control circuit 502 performs the phase comparison.
Since feedback control is performed so that the phases match based on the comparison result of 3, the output signals can be compared in phase.

FIG. 47 is a block diagram showing a configuration of the output timing control circuit of the eighth embodiment. The output timing control circuit of the eighth embodiment is different from the output timing control circuit of the seventh embodiment in that the output signal described in the fifth embodiment is "L".
This is an example to which a configuration in which different timing controls are applied when changing from "H" to "H" and when changing from "H" to "L", respectively. The seventh embodiment is different from the seventh embodiment in that two delay circuits 501-H and 501-L are controlled independently of each other.
The difference is that two delay control circuits 502-H and 502-L are provided. Here, further description is omitted.

When comparing the phase of the output signal with the external clock signal, a phase adjustment mode is provided.
Phase adjustment may be performed. To do this, a dummy data output circuit for outputting dummy data that changes in a predetermined cycle shown in FIG. 34 is provided. In the phase adjustment mode, the output circuit outputs dummy data, and its output signal and an external clock signal are output. And performs feedback control such that the phases match. After the coincidence, the mode is switched to the normal mode, in which the adjusted delay amount is maintained. In this case, the phase can be adjusted by feedback control as in the first to sixth embodiments.

FIG. 48 is a block diagram showing a configuration of the output timing control circuit of the ninth embodiment. The output timing control circuit of the ninth embodiment is an example in which another phase comparison circuit is applied to the basic configuration of the output timing control circuit having the dummy output circuit shown in FIG. As described above, when the dummy output circuit is provided, the dummy data generated by the dummy data generation circuit and changing in a predetermined cycle is output, and the phase comparison with the output signal is performed. Since the dummy data changes in a predetermined cycle, the phase determination circuit 5
32 determines whether or not the output signal changes, and when it does not change, there is no need to output a hold signal so as not to change the delay amount of the delay circuit. Therefore, in the circuit of the ninth embodiment, the dummy input circuit 5 is synchronized with CLK1.
A latch circuit 533 for latching the output signal
A latch circuit 534 that latches the output signal of the dummy input circuit 506 in synchronization with / 2CLK1 is provided, and the output of the latch circuit 533 is input to the phase determination circuit 532 as RG1 and the output of the latch circuit 534 is input as RG2. .
The phase determination circuit 532 determines the phase based on RG1 and RG2.

FIG. 49 is a diagram showing a circuit configuration of the phase comparison circuit 532 used in the output timing control circuit of the ninth embodiment. As is clear from the figure, this phase comparison circuit is constituted by a circuit only on the side for calculating the up / down signal UP / DOWN of the phase comparison circuit shown in FIG.
As described above, in the ninth embodiment, it is determined whether or not the output signal changes. When the output signal does not change, it is not necessary to output the hold signal. Therefore, the portion for generating the hold signal HOLD is omitted.

FIG. 50 shows a decision operation of phase decision circuit 532 in FIG. As shown in (1) of FIG.
When the output signal DQ (here, the output of the dummy input circuit) lags behind the clock signal CLK1, RG1 and RG2 have different values. When DQ is advanced with respect to CLK1, RG1 and RG2 have the same value.
Therefore, the phase determination circuit 532 sets the up / down signal UP / DOWN to "L" so as to reduce the clock delay when RG1 and RG2 have different values, and when the RG1 and RG2 have the same value, the clock delay UP / DOWN is set to “H” so as to increase. The above states, the values of RG1 and RG2 at that time, and the necessary operations are shown in the truth table of FIG.

Returning to FIG. 48, as the delay circuit 501 and the delay control circuit 531, the seventh circuit shown in FIG.
The same circuit as that of the embodiment is used. However, as shown in FIG.
No LD is input and no hold function is required. FIG.
FIG. 19 is a block diagram illustrating a configuration of an output timing control circuit according to a tenth embodiment. The output timing control circuit according to the tenth embodiment uses the 1 / N frequency dividing circuit described in the first embodiment to reduce the change period of the output signal from the dummy output circuit to 1 / N.
Is applied to the circuit of the ninth embodiment.
As shown, a 1 / N frequency dividing circuit 542 and a CLK control circuit 5 for delaying a clock signal by a 1 / N frequency dividing circuit 542
41, a delay circuit 501b for delaying the clock CLK1 / N divided by 1 / N, and a dummy input circuit 505
And 506 are provided with dummy CLK control circuits 543 and 544 having the same delay amount as that of the CLK control circuit 541. The latch circuit 533 latches the dummy CLK control circuit 543 in synchronization with CLK1 / N, and 534 differs from the ninth embodiment in that the dummy CLK control circuit 544 is latched in synchronization with / CLK1 / N obtained by inverting CLK1 / N. The other parts are the same as in the ninth embodiment.

FIG. 54 is a diagram showing the judging operation of the tenth embodiment. As shown in the figure, even when the external clock signal CLK is not a signal with a duty of 50% due to deterioration during transmission or the like, the changing edge of the signal CLK1 / N divided by 1 / N is synchronized with the rise of CLK. CLK1 / N
, The dummy output signal changes in synchronization with the rising edge of CLK1 / N as shown in FIG. Therefore, the timing at which the latch circuit 533 latches is near the rising edge of CLK1 / N, and the timing at which the latch circuit 534 latches is near the rising edge of CLK1 / N. That is, the latch timing of the latch circuit 534 is near the midpoint of the changing edge of the dummy output signal. When DQ is delayed, RG1 and RG2 have different values.
Are advanced, RG1 and RG2 have the same value.

FIG. 55 is a block diagram showing the configuration of the output timing control circuit of the eleventh embodiment. The output timing control circuit of the eleventh embodiment differs from the output timing control circuit of the tenth embodiment in that the output signal described in the fifth embodiment changes from "L" to "H" and from "H" to "H". This is an example in which a configuration in which different timing controls are performed when changing to “L” is applied. Here, further description is omitted.

The output timing control circuit of the semiconductor device of the present invention has been described in the first to eleventh embodiments. How to apply such an output timing control circuit in such a semiconductor device is described. An example of will be described. FIG. 56 shows the clock input circuit 13, the output timing control circuit 30, and the first to m-th output circuits 571-1 and 571- in the semiconductor device of the twelfth embodiment.
2, 571-m and the arrangement of clock signal distribution circuits 580.

As shown, a plurality of signals OS-1, OS-2,..., OS-n are output from this semiconductor device, so that output circuits 571-1, 571-1-1 are output for each output signal.
, 571-m are provided. The clock distribution circuit 580 converts the clock signal supplied from the clock input circuit 13 via the output timing control circuit 30 into a plurality of buffer circuits (CB1, CB21,.
.., 571-m arranged in the semiconductor device via 81 to 583. The wiring is equidistant so that the wiring length to the distribution destination and the number of passing buffer circuits are all the same. Therefore, in FIG. 56, each output circuit 571-1, 571
,..., 571-m all have the same phase. The clock input circuit 13 and the output timing control circuit 30 are connected to the output circuits 571-1 and 571
, 571-m, in this case, in the vicinity of the first output circuit 571-1. Then, the output timing control circuit 30 controls so that the phase of the output signal from the first output circuit 571-1 is synchronized with the external clock CLK. As described above, the clock distribution circuit 580
Are equidistant wiring, the phases of the clock signals input to each output circuit are all the same, and the phase of the output signal of the first output circuit 571-1 is the external clock CLK.
, The phases of the output signals from all the output circuits are synchronized with the external clock CLK.

In the semiconductor device to which the circuits of the first to twelfth embodiments described above are applied, the accuracy of synchronizing the output signal with respect to the external clock is greatly improved as compared with the conventional example.
A description will be given of an embodiment in which a semiconductor device system is configured using a semiconductor device which outputs with high synchronization accuracy to such an external clock. First, the conventional output timing and its problem will be described. FIG. 57 is a diagram illustrating output timing of a conventional semiconductor device that outputs data in synchronization with an external clock signal. In the conventional example, an operation for outputting data is started according to the rising of the external clock signal CLK (t0). The output actually appears at the output terminal after a certain time. This time varies depending on process variations, power supply fluctuations, temperature, and the like. The output appears at t1 at the shortest and at t2 at the longest. That is, the clock access time is in the range of tOH and tAC from the rising edge of the external clock signal. These tOH and tAC are specified in the specifications of the semiconductor device.
The period between t1 and t2 is a time during which data that cannot be actually used is uncertain.

On the side receiving such an output, a setup time tIS and a hold time tIH are required, and tIS and tIH are defined for the rising edge of the external clock signal. The start time of the setup time tIS is t3, and the end time of the hold time tIH is t5.
Indicated by Therefore, in the figure, the difference between the time from t2 to t6 and t3 to t5 is the timing margin of the system. This timing margin is necessary to a certain degree or more to absorb errors due to various factors of the system.

In recent years, the frequency of the external clock signal has been increasing, and there has been a problem that this timing margin cannot be sufficiently secured. FIG. 58 is a diagram showing output timing of the semiconductor device of the present invention. In the conventional example, as shown in FIG. 57, the output operation is started from the rising edge of the external clock signal. On the contrary,
In the semiconductor device of the present invention, the output signal is output in synchronization with the falling edge of the external clock signal.
Of course, the rising and falling edges of the external clock signal are 180 degrees out of phase with a 50% duty ratio.
It is assumed that the signal is As described above, in the semiconductor device of the present invention, it is possible to accurately control the output timing of the output signal so as to have a predetermined phase with respect to the external clock signal. Therefore, the output signal appears immediately at the output terminal in synchronization with the falling edge of the external clock signal. Therefore, the center of the period in which the output signal is determined coincides with the rising edge of the external clock signal, and the same timing margin can be obtained before and after the input. Here, considering the case where the cycle of the external clock signal becomes narrower, the advantage of outputting at such timing becomes clear.

FIG. 59 shows a thirteenth embodiment constructed using semiconductor memories 610 to 613 capable of accurately controlling the output timing of an output signal to a predetermined phase with respect to an external clock signal. FIG. 2 is a diagram showing the arrangement of elements and the state of signal wiring in a memory system. Also,
FIG. 60 is a diagram showing the phase relationship between the clock signal CLK and data in the memory system of the thirteenth embodiment.

In the figure, reference numeral 601 denotes a controller of this memory system. The semiconductor memories 610 to 613 are arranged as shown in FIG.
0 to 613 are stored in the clock signal line 6
The data is output to the data bus 602 in synchronization with the clock signal CLK applied to the data bus 03. Here, the clock signal CLK
Assuming that the direction of propagation of the clock signal line 603 from the right side to the left side of the figure as shown in FIG. Become. However, the time required for the data output in synchronization with the CLK to reach the controller 601 is shorter in the left memory. Assuming that the propagation speed of the clock signal CLK on the clock signal line 603 is equal to the propagation speed of the data signal on the data bus 602, as shown in FIG.
The clock reaches the controller 601 at the timing when the CLK reaches the controller 601. Therefore, the controller 601 may fetch data based on CLK.

FIG. 61 is a diagram showing the arrangement of elements and the state of signal wiring in the memory system of the fourteenth embodiment.
In the memory system of the fourteenth embodiment, CLK is first input to the controller 601, and the controller 601 generates a write clock signal Write-LK and a read clock signal Read-CLK from this CLK. Re
The clock signal line through which ad-CLK is propagated is signal line 6
After the signal is once propagated to the position of the rightmost memory 613 at 05, the signal is returned to the controller 601 via the signal line 606. The supply of Read-CLK to each memory is performed from the signal line 606. Thus, the data output from each memory is taken into the controller 601 in the same manner as in the thirteenth embodiment.

In the fourteenth embodiment, the Read-CLK transmitted on the signal line 606 is
-Entered as Receive. And this Re
The delay amount of Read-CLK is adjusted such that ad-CLK and Read-Receive match. FIG. 62
FIG. 33 is a diagram illustrating a system of a clock signal in a controller 601 according to the fourteenth embodiment.

As shown in FIG. 42, CLK input from the outside enters the output buffer 621, and
CLK is output. The Write-CLK passes through the current mirror circuit 622 and the driver 623, is amplified, is delayed by an amount selected by the delay circuit 624, and is output from the output buffer 625 as Read-CLK. The returned Read-CLK is Read-CLK.
Received as Receive, current mirror circuit 6
26 and the driver 627, the phase comparison circuit 62
8 is input. The phase comparison circuit 628 includes the driver 62
3 is also input and the phases are compared. Then, the delay control circuit 629 selects a delay amount of the delay circuit based on the comparison result. In this way, Read-CL
K and Read-Receive match so that
The delay amount of d-CLK is adjusted.

FIG. 63 is a diagram showing the arrangement of elements and the state of signal wiring in the memory system of the fifteenth embodiment.
In the memory system of the fifteenth embodiment, as in the thirteenth embodiment, the controller 601 transmits a clock signal CLK propagating in the direction in which the output data from the memory propagates.
Received as d-Receive. Controller 601
Generates a write clock signal Write-CLK from this Read-Receive. Reading from the memory is performed in synchronization with CLK. Write to be output
The delay amount of -CLK is adjusted so that the phase of Read-Receive coincides with that of Read-Receive.

FIG. 64 is a diagram showing a clock signal system in the controller 601 in the fifteenth embodiment.
As shown in FIG. 64, CLK-Re input from the outside
"ceive" is the current mirror circuit 631 and the driver 6
32, and is delayed by the amount selected by the delay circuit 633.
It is output as item-CLK. This Write-C
LK is input to the phase comparison circuit 637 after passing through the current mirror circuit 635 and the driver 636. The output of the driver 632 is also input to the phase comparison circuit 637, and the phases are compared. Then, the delay control circuit 638 selects the delay amount of the delay circuit 633 based on the comparison result. In this way, the phase of Write-CLK is changed to Re.
Adjusted to match ad-Receive.

FIG. 65 is a diagram showing the arrangement of elements and the state of signal wiring in the memory system of the sixteenth embodiment.
In the memory system of the sixteenth embodiment, the controller 6
The clock terminal 01 is used for both the read clock and the write clock. Similarly to the seventh embodiment, the clock signal CLK propagates in the direction in which the output data from the memory propagates.
Is received by the controller 601 as R / W-CLK.
Therefore, the controller 6 of the data output from the memory
01 is the same as in the seventh embodiment. The clock signal CLK branches to the clock signal line 607 immediately before being input to the controller 601 and returns in the opposite direction, which becomes a clock signal for writing. Therefore, the controller 6
The data to be written to the memory and the clock signal for writing output from 01 are propagated in parallel. The problem is to match the phases of the data to be written to the memory and the clock signal for writing.

FIG. 66 is a diagram showing a clock signal system in the controller 601 in the sixteenth embodiment.
As shown in FIG. 66, R / W-CL input from outside
K is amplified by passing through a current mirror circuit 641 and a driver 642, delayed by an amount selected by a delay circuit 643, and then supplied to a data output buffer 644. The data output buffer 644 outputs the data of the write data register 640 in synchronization with the timing signal supplied from the delay circuit 643. This timing signal is input to the current mirror circuit 645 after being delayed by the dummy output buffer 649 by the same delay amount as that of the data output buffer 644. After the output of the current mirror circuit 645 passes through the driver 646, the output of the phase comparison circuit 6
47 is input. The driver 6 is included in the phase comparison circuit 647.
The output of 42 is also input and the phases are compared. Then, the delay control circuit 648 selects a delay amount of the delay circuit 643 based on the comparison result. In this way, the write data Write-Data is synchronized with R / W-CLK, that is, the write clock signal.

[0127]

As described above, according to the present invention,
Since the amount of delay is adjusted so that the actual circuit signal is compared with the external clock signal so as to have a predetermined phase relationship, even if there is variation in the characteristics of the semiconductor device, temperature change, power supply voltage change, etc., the output signal Can be accurately maintained at a predetermined value with respect to the external clock signal.

Further, since an input dummy circuit and an output dummy circuit are provided to make the signal to be compared with the external clock signal a signal close to the actual output signal, the phase can be adjusted accurately. Further, since the phases of the rising output data and the falling output data are adjusted respectively, the phase error can be further reduced.

Further, even if the dummy circuit is manufactured in a similar manner, there is a difference from the circuit related to the actual output, and the load actually connected to the output terminal cannot be predicted. Is inevitable. Such a difference becomes an error in the phase adjustment. According to the present invention, the adjustment is performed including such an error, so that the error can be further reduced. Further, by using such a semiconductor device, a semiconductor system which can operate at high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a synchronous DRAM (SDRAM).

FIG. 2 is a time chart showing a basic operation of the SDRAM.

FIG. 3 is a basic operation diagram of a pipeline type SDRAM.

FIG. 4 is a diagram for explaining the timing of the SDRAM and problems at the time of high-speed operation.

FIG. 5 is a diagram showing a basic configuration of a semiconductor device of the present invention for synchronizing a timing signal supplied to an output circuit with an external clock signal.

FIG. 6 is a diagram illustrating a problem in the basic configuration of FIG. 5;

FIG. 7 is a diagram showing a configuration of a semiconductor device of the present invention in which the basic configuration of FIG. 5 is further improved.

FIG. 8 is an operation diagram of the SDRAM of the embodiment.

FIG. 9 is a diagram showing a configuration of a portion related to output timing control of the SDRAM of the first embodiment.

FIG. 10 is a diagram showing the configuration and operation of the delay circuit of the first embodiment.

FIG. 11 is a diagram illustrating a configuration of a delay control circuit according to the first embodiment.

FIG. 12 is a time chart illustrating the operation of the delay control circuit according to the first embodiment.

FIG. 13 is a diagram illustrating a change in an output signal of the delay control circuit according to the first embodiment.

FIG. 14 is a diagram illustrating another example of the delay control circuit.

FIG. 15 is a diagram illustrating a configuration of a phase comparison unit of the phase comparison circuit according to the first embodiment.

FIG. 16 is a time chart illustrating an operation of the phase comparison unit of the phase comparison circuit according to the first embodiment.

FIG. 17 is a diagram illustrating a configuration of an amplifier circuit unit of the phase comparison circuit according to the first embodiment.

FIG. 18 shows J of the amplifier circuit section of the phase comparison circuit of the first embodiment.
6 is a time chart illustrating an operation of a K flip-flop.

FIG. 19 is a time chart illustrating a count-up operation of the amplifier circuit unit of the phase comparison circuit according to the first embodiment.

FIG. 20 is a time chart illustrating a count maintaining operation of the amplifier circuit unit of the phase comparison circuit according to the first embodiment.

FIG. 21 is a time chart illustrating a countdown operation of the amplifier circuit unit of the phase comparison circuit according to the first embodiment.

FIG. 22 is a diagram illustrating a configuration of an output circuit according to the first embodiment.

FIG. 23 is a diagram showing a configuration of a dummy output circuit of the first embodiment.

FIG. 24 is a time chart showing the operation of the dummy output circuit of the first embodiment.

FIG. 25 is a diagram illustrating a configuration of a dummy output circuit according to a second embodiment.

FIG. 26 is a diagram illustrating a configuration of a dummy output circuit according to a third embodiment.

FIG. 27 is a diagram illustrating a configuration of a dummy output circuit according to a fourth embodiment.

FIG. 28 is a diagram showing a configuration of a portion related to output timing control of the SDRAM of the fifth embodiment.

FIG. 29 is a diagram showing a configuration of a phase comparison circuit of the SDRAM of the fifth embodiment.

FIG. 30 is a diagram illustrating a configuration of a dummy output circuit according to a fifth embodiment.

FIG. 31 is a time chart showing the operation in the fifth embodiment.

FIG. 32 is a diagram for explaining an occurrence of an error due to a change in characteristics of a normal route and a dummy route.

FIG. 33 is a diagram showing a configuration of a portion related to output timing control of the SDRAM of the sixth embodiment.

FIG. 34 is a diagram illustrating a configuration of a dummy output circuit according to a sixth embodiment;

FIG. 35 is a time chart showing the operation of the dummy output circuit in the sixth embodiment.

FIG. 36 is a diagram illustrating a configuration of an output circuit according to a sixth embodiment.

FIG. 37 is a time chart illustrating the operation of the output circuit in the sixth embodiment.

FIG. 38 is a diagram illustrating a configuration of a switching circuit according to a sixth embodiment.

FIG. 39 is a diagram showing a configuration of a portion related to output timing control of the SDRAM of the seventh embodiment.

FIG. 40 is a diagram illustrating a configuration example of a delay circuit and a delay control circuit of a receiving-side semiconductor device according to a seventh embodiment.

FIG. 41 is a diagram showing a configuration of a 1/2 phase shift circuit of a seventh embodiment.

FIG. 42 is a diagram illustrating a configuration of a phase determination circuit according to a seventh embodiment.

FIG. 43 is a diagram illustrating a phase determination operation in the seventh embodiment.

FIG. 44 is a diagram illustrating a phase determination operation in the seventh embodiment.

FIG. 45 is a diagram illustrating a phase determination operation in the seventh embodiment.

FIG. 46 is a truth table of the phase determination operation in the seventh embodiment.

FIG. 47 is a diagram showing a configuration of a portion related to output timing control of the SDRAM of the eighth embodiment.

FIG. 48 is a diagram showing a configuration of a portion related to output timing control of the SDRAM of the ninth embodiment.

FIG. 49 is a diagram illustrating a configuration of a phase determination circuit according to a ninth embodiment.

FIG. 50 is a diagram illustrating a phase determination operation in the ninth embodiment.

FIG. 51 is a truth table of a phase determination operation in the ninth embodiment;

FIG. 52 is a diagram illustrating a configuration of a delay control circuit according to a ninth embodiment;

FIG. 53 is a diagram showing a configuration of a portion related to output timing control of the SDRAM of the tenth embodiment.

FIG. 54 is a diagram illustrating a phase determination operation in the tenth embodiment.

FIG. 55 is a diagram showing a configuration of a portion related to output timing control of the SDRAM of the eleventh embodiment.

FIG. 56 is a diagram showing an arrangement of a clock input circuit, an output timing control circuit, a clock distribution circuit, and an output circuit in the SDRAM of the twelfth embodiment.

FIG. 57 is a diagram showing output timing in a conventional semiconductor device.

FIG. 58 is a diagram showing output timing in the semiconductor device of the present invention.

FIG. 59 is a diagram showing element arrangement and signal wiring in a semiconductor device system of a thirteenth embodiment.

FIG. 60 is a time chart showing signal waveforms in the thirteenth embodiment.

FIG. 61 is a diagram showing element arrangement and signal wiring in a semiconductor device system according to a fourteenth embodiment.

FIG. 62 is a diagram showing a system for clock timing adjustment in the controller of the fourteenth embodiment.

FIG. 63 is a diagram showing element arrangement and signal wiring in the semiconductor device system of the fifteenth embodiment.

FIG. 64 is a diagram showing a system of clock timing adjustment in the controller of the fifteenth embodiment.

FIG. 65 is a diagram showing element arrangement and signal wiring in a semiconductor device system of a sixteenth embodiment.

FIG. 66 is a diagram illustrating a system for clock timing adjustment in the controller according to the sixteenth embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... External signal input terminal 12 ... Signal output terminal 13 ... Input circuit 14 ... Output circuit 20, 30 ... Output timing control circuit 21, 31 ... Delay circuit 22, 32 ... Phase comparison circuit 23, 33 ... Delay control circuit 34 ... Dummy Input circuit 35 ... Dummy output circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Terumasa Kitahara 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Masao Nakano 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 Fujitsu Limited (72) Inventor Masao Taguchi 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 1-1 (Inside) Fujitsu Yoshihiro Takemae 4 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 1-1 1-1 Fujitsu Co., Ltd. (72) Inventor Yasuo Matsuzaki 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Co., Ltd. (72) Koichi Nishimura 4 Ueodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (72) Inventor Yoshinori Okajima 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fuji The Corporation

Claims (39)

[Claims] An input circuit for receiving an external input signal and outputting a reference signal; an output circuit receiving an output timing signal and outputting an output signal at a timing corresponding to the output timing signal; And an output timing control circuit for controlling the output timing of the output signal to a predetermined phase with respect to the external input signal, wherein the output timing control circuit is capable of selecting a delay amount, A delay circuit that delays the reference signal by a selected delay amount and applies the output signal as the output timing signal to the output circuit; and a phase comparison circuit that compares a phase of the reference signal with a phase of a signal responsive to the output timing signal. And a delay control circuit that selects a delay amount of the delay circuit based on a comparison result of the phase comparison circuit. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein a signal responsive to the output timing signal is input, and the dummy input delays the output timing signal by a delay amount equal to a delay amount in the input circuit. A semiconductor device including a circuit, wherein the phase comparison circuit compares a phase of the reference signal with a phase of an output signal of the dummy input circuit. 3. The semiconductor device according to claim 1, further comprising: a dummy output circuit to which the output timing signal is input and delaying the output timing signal by a delay amount equal to a delay amount in the output circuit. The semiconductor device, wherein the phase comparison circuit compares a phase of the reference signal with a phase of a signal responsive to an output signal of the dummy output circuit. 4. The semiconductor device according to claim 2, further comprising: a dummy output circuit to which the output timing signal is input and delays the output timing signal by a delay amount equal to a delay amount in the output circuit. A semiconductor device to which the output timing signal delayed by the dummy output circuit is input to the dummy input circuit; 5. The semiconductor device according to claim 3, further comprising: a dummy load circuit having a predetermined load driven by said dummy output circuit, wherein said phase comparison circuit includes a phase of said reference signal and said dummy load. A semiconductor device for comparing the phase of a signal in response to an output signal of a circuit. 6. The semiconductor device according to claim 4, further comprising a dummy load circuit having a predetermined load driven by said dummy output circuit, wherein an output of said dummy load circuit is input to said dummy input circuit. Semiconductor device. 7. The semiconductor device according to claim 3, wherein said output circuit is capable of switching drive characteristics in accordance with a switching signal, and said dummy output circuit is also capable of switching drive characteristics in accordance with said switch signal. Semiconductor device. 8. The semiconductor device according to claim 5, wherein said output circuit is capable of switching drive characteristics in accordance with a switching signal, and said dummy output circuit is also capable of switching drive characteristics in accordance with said switching signal. Semiconductor device. 9. The semiconductor device according to claim 8, wherein a load of said dummy load circuit is switchable according to said switching signal. 10. The semiconductor device according to claim 3, wherein a drive power supply for the output circuit is a power supply supplied from an external source different from an internal power supply of the semiconductor device. A semiconductor device, wherein a drive power supply for the dummy output circuit is the same power supply as a drive power supply for the output circuit. 11. The semiconductor device according to claim 1, wherein said delay circuit includes first and second delay circuits, and said output circuit outputs said output signal at a high level. At the timing according to the output timing signal output from the first delay circuit, and when the output signal changes to a low level, at the timing according to the output timing signal output from the second delay circuit. Outputting the output signal, the delay control circuit selects a delay amount of the first delay circuit based on a comparison result of the phase comparison circuit when the output signal changes to a high level, A semiconductor device for selecting a delay amount of the second delay circuit based on a comparison result of the phase comparison circuit when an output signal is at a low level. 12. The semiconductor device according to claim 1, wherein the phase comparison circuit includes a value of an output signal of the output circuit at a predetermined phase of the reference signal and a value before and after the predetermined phase. Detecting the value of the output signal of the output circuit in the above, does not perform the determination operation when the value before and after is the same, and compares the phase from the value before and after when the value before and after is different from the value at the predetermined phase, The delay control circuit controls the delay amount up to that time when the phase comparison circuit does not perform the determination operation, and controls the delay amount based on the determination result when the phase comparison circuit performs the determination operation. Semiconductor device that changes 13. The semiconductor device according to claim 1, wherein: a dummy data generation circuit that outputs dummy data that changes in a predetermined cycle; and a signal output from the output circuit is a normal data signal.
An output data switching circuit for switching between the dummy data output from the dummy data generation circuit and the dummy data output from the output circuit when the semiconductor device is initialized. A semiconductor device to which a data signal is output. 14. The semiconductor device according to claim 13, wherein the phase comparison circuit includes a value of an output signal of the output circuit at a predetermined phase of the reference signal and the value of the output signal before the predetermined phase. The value of the output signal of the output circuit is detected, and the phase is compared with the previous value and the value at the predetermined phase. The delay control circuit initializes the delay amount based on the determination result of the phase comparison circuit at initialization. And controlling the delay amount after initialization to maintain the delay amount. 15. The semiconductor device according to claim 3, further comprising: a dummy data generation circuit that generates dummy data that changes in a predetermined cycle, wherein the dummy output circuit includes the dummy output circuit. A semiconductor device that outputs a data output circuit. 16. The semiconductor device according to claim 15, wherein said phase comparison circuit includes a value of an output signal of said output circuit at a predetermined phase of said reference signal and said value before said predetermined phase. A semiconductor device which detects a value of an output signal of an output circuit and compares a phase with the previous value and a value at the predetermined phase. 17. The semiconductor device according to claim 1, wherein said reference signal output from said input circuit is shifted by a half period from said reference signal. A semiconductor device including a 1/2 phase shift circuit that generates a shift clock. 18. The semiconductor device according to claim 3, wherein the input circuit (13) converts the reference signal to 1 / N (N:
A 1 / N frequency dividing circuit for generating a 1 / N frequency dividing signal having the same phase as the reference signal corresponding to the signal divided by (integer). The same delay amount as the delay circuit is selected by the control circuit, and a dummy delay circuit that outputs a dummy output timing signal to the dummy output circuit is provided. The dummy output circuit replaces the output timing signal from the delay circuit. A semiconductor device configured to receive a dummy output timing signal from the dummy delay circuit. 19. The semiconductor device according to claim 18, wherein said dummy output timing signal is provided between said dummy delay circuit and said dummy output circuit and output from said dummy delay circuit. A semiconductor device including a dummy signal line for delaying by a delay amount equal to a signal line from a delay circuit to the output circuit. 20. The semiconductor device according to claim 18, wherein said delay circuit includes first and second delay circuits, and said dummy delay circuit is a first and second dummy delay circuit. The output circuit comprises: a timing corresponding to an output timing signal output from the first delay circuit when the output signal is at a high level, and the second delay circuit when the output signal is at a low level. The dummy output circuit outputs the output signal at a timing corresponding to the output timing signal output by the first dummy delay circuit when the first dummy delay circuit outputs a high-level signal. When outputting a low-level signal at a corresponding timing, a dummy output timing signal output from the second dummy delay circuit Outputting a dummy output signal at a timing corresponding to the first delay circuit and the first dummy circuit based on a comparison result of the phase comparison circuit when the dummy output signal is at a high level. The delay amount of the second delay circuit and the second dummy delay circuit based on the comparison result of the phase comparison circuit when the dummy output signal is at a low level. The semiconductor device to select. 21. The semiconductor device according to claim 18, further comprising: a dummy data generation circuit that generates dummy data that changes in a predetermined cycle, wherein the dummy output circuit includes the dummy output circuit. A semiconductor device that outputs a data output circuit. 22. The semiconductor device according to claim 21, wherein the dummy data is a signal having a duty of 50%. 23. The semiconductor device according to claim 21, wherein said phase comparison circuit includes a value of an output signal of said output circuit at a predetermined phase of said reference signal and a value of said output signal before said predetermined phase. A semiconductor device that detects a value of an output signal of the output circuit and compares a phase of the output signal with a value at the predetermined phase. 24. Claims 3 to 10, 15, 16, 18
24. The semiconductor device according to any one of claims 23 to 23, wherein: a second phase comparison circuit that compares a phase of the reference signal with a phase of a third timing signal; and a comparison result of the second phase comparison circuit. A second delay control circuit for selecting a delay amount of the delay circuit based on the following: a signal supplied to the second phase comparison circuit as the third timing signal, the output of the output circuit and the dummy output A switching circuit for switching between signals and a dummy data generating circuit for generating dummy data for phase comparison, wherein the switching circuit outputs the output of the output circuit at the time of initialization of the semiconductor device, and after completion of the initialization. Is a semiconductor device that switches so as to supply the dummy output signal to the second phase comparison circuit. 25. The semiconductor device according to claim 24, wherein the output circuit outputs the dummy data during the initialization. 26. The semiconductor device according to claim 25, wherein said dummy output circuit outputs said dummy data during said initialization, and outputs output data output from said output circuit after completion of said initialization. Semiconductor device. 27. The semiconductor device according to claim 25, wherein said dummy output circuit always outputs said dummy data. 28. The semiconductor device according to claim 1, wherein the external input signal is a clock signal whose rising and falling phases are shifted by 180 degrees. Fetching data in synchronization with one of the rising and falling edges of the external input signal; and outputting the output signal from the output circuit in synchronization with the other rising and falling edge of the external input signal. Semiconductor device controlled as follows. 29. The semiconductor device according to claim 1, wherein a plurality of the output circuits are provided, and the reference signal is transmitted from the input circuit to each output circuit. A semiconductor device whose signal path has the same delay amount. 30. The semiconductor device according to claim 29, wherein a signal path for transmitting the reference signal from the input circuit to a plurality of the output circuits is an equidistant wiring. 31. The semiconductor device according to claim 1, wherein a plurality of the output circuits are provided, and the timing control circuit is provided for each output circuit. Semiconductor device. 32. The semiconductor device according to claim 1, wherein said semiconductor device is a synchronous semiconductor memory. 33. A phase of rising and falling is 18
In a semiconductor device that inputs and outputs data in synchronization with an external clock signal shifted by 0 degrees, a data output circuit that outputs data in synchronization with one of the rising and falling, and a data output circuit that outputs data in synchronization with the other of the rising and falling And a data input circuit for receiving data from the semiconductor device. 34. The semiconductor device according to claim 33, further comprising: a timing signal generation circuit that generates an output timing signal and an input timing signal from the external clock signal, wherein the data output circuit operates according to the output timing signal. A semiconductor device which outputs data, and wherein the data input circuit inputs data according to the input timing signal. 35. The semiconductor device according to claim 34, wherein the timing signal generation circuit includes: a delay circuit that delays the output timing signal; and a timing comparison circuit that compares the external clock signal with the output timing signal. A semiconductor device that controls a delay amount of the delay circuit based on a comparison result of the timing comparison circuit so that data output from the data output circuit is synchronized with one of the rising edge and the falling edge . 36. A semiconductor device system in which a plurality of semiconductor devices are connected to output data in synchronization with a first external signal and input data in synchronization with a second external signal. A semiconductor device system in which a line for transmitting output output data and a line for transmitting the first external signal are arranged in parallel, and a transmission direction of the output data and a transmission direction of the first external signal are the same. . 37. The semiconductor device system according to claim 36, wherein a wiring for transmitting input data to be input to the semiconductor device and a wiring for transmitting the second external signal are arranged in parallel. A semiconductor device system in which a transmission direction of input data and a transmission direction of the second external signal are the same. 38. A delay line having a plurality of signal paths connected in series, wherein a delay amount is selectable by selectively outputting a signal from a part of the plurality of signal paths; A delay control circuit for selecting a delay amount of the delay line, wherein the delay amount is changed stepwise, wherein the delay control circuit outputs a complementary signal to each stage, Outputs a complementary signal, the subsequent stages output an inverted complementary signal, and the position of the stage that first outputs the inverted complementary signal is shifted. A gate for calculating a logical value of a complementary signal on a different side, wherein the output of the gate selectively activates the delay line. A digital delay circuit, which outputs a signal for activating the delay line when the complementary signal of the register has the original logical value on the slow side. 39. A delay line having a plurality of signal paths connected in series, wherein a delay amount is selectable by selectively activating a part of the plurality of signal paths, and a delay of the delay line. A delay control circuit for selecting an amount, wherein the delay amount is changed stepwise, wherein the delay control circuit activates at least two adjacent signal paths of the delay line. Characteristic digital delay circuit.