JPH1011992A - Sample hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sample hold circuit which assures smaller offset voltage in the sampling period, operation with a high speed clock and small power consumption. SOLUTION: An input signal Vin is amplified by a full feedback type differential amplifier (transistors Q5 , Q6 , constant current source 6A) and it is then transferred to an output terminal 5 via an output transistor Q7 of the emitter follower having a voltage holding capacitor C at an output point. ON-OFF of the full feedback type differential amplifier and transistor Q7 is respectively controlled by the differential amplifier (transistors Q1 , Q2 ) and differential amplifier (transistors Q3 , Q4 ) which switch the current path depending on the clock CLK. A transistor Q8 is provided between the power supply terminal 1 and the base electrode of the transistor Q7 . The input signal Vin is input to the full feedback type amplifier and it is also input to the base electrode of the transistor Q8 . Thereby, a base voltage of the output transistor Q7 in the OFF state is caused to follow voltage change of the input signal Vin .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a sample and hold circuit.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional sample and hold circuit. FIG. 4 shows input / output waveforms during operation of the circuit. The operation of the circuit will be described below with reference to FIGS. Since the clock terminal 3 is at the high (H) level during the period t _{1 to} t ₂ in FIG.
_1, Q ₄ is turned on. On the other hand, transistors Q ₂ ,
Q ₃ are the signal to the clock terminal 3 is supplied a signal which is inverted to low (L) level by the inverter to the base electrode, turned off. During the period t ₁ ~t ₂ Thus, the transistors Q _5, Q _6, full feedback circuit and an emitter follower transistor Q ₇ becomes a constant current source 6A is in ON state, the voltage waveform input to the input terminal 2, The signal is output to the output terminal 5 as it is. This operation period is called a sampling period.

Next, a period t_Two~ T_ThreeClock is low
Because it is in the bell, transistor Q₁ , Q_FourIs off
Become. On the other hand, transistor Q_Two, Q_ThreeIs turned on.
You. Therefore, the period t_Two~ T_ThreeDuring the period, the all feedback circuit and
And emitter follower transistor Q₇Is in the off state
Time t_TwoImmediately before transistor Q₇By conden
The voltage V charged to the capacitor C_CIs held. The result
As a result, the voltage of the output terminal 5 is equal to the period t._Two~ T_ThreeInput terminal
Constant voltage V even if the input voltage to_CBecomes this
The operation period is called a hold period.

[0004] By repeating the above operation, an output waveform as shown in FIG.

Meanwhile, in the circuit shown in FIG. 3, the time t ₂
When the transistors Q ₂ and Q ₃ are turned on,
The current I ₀₁ of the constant current source 6A is all transistors Q ₂ and Q ₃
Flows to However, since the constant current source 6A has no element for fixing the collector potentials of the transistors Q ₂ and Q ₃ ,
Transistor Q _2, the collector potential of the Q ₃ are transistors Q _2, Q forward voltage drop V _F min to about 0 from the base potential of the base-collector junction thereof transistor _3.
The potential drops by 6V. Therefore, the two transistors Q ₂ and Q ₃ are both saturated. Switching speed of the transistors in saturation as is well known, since remarkably slower than desaturate, time t ₃
Even now in base potential of the transistor Q _2, Q ₃ is changed to the L level, the transistors Q _2, Q ₃ can not transition to the OFF state immediately, turned off after a certain delay time t _d. Meanwhile, all the feedback circuit and an emitter follower transistor Q ₇ described above is not accustomed to the ON state, the output voltage delayed by time t _d follows the input voltage. Therefore, even if the sampling period starts again at time t ₃ , the output voltage is not the same as the input voltage at time t ₃ , but outputs a voltage value lower by the offset voltage V _os .

As described above, in the circuit shown in FIG. 3, the offset voltage V is applied to the output during the sampling period.
There is a problem that _os occurs. Furthermore, the frequency of the clock input to the clock terminal increases,
If the H-level period is shorter than the delay time t _{d of the} circuit, that is, if t _d > the H-level period of the clock, the circuit can no longer operate. That is, there is a disadvantage that high-speed operation cannot be performed.

A circuit shown in FIG. 5 is an improved sample-and-hold circuit in which the above-mentioned disadvantages are improved. Referring to FIG. 5, this circuit is the basic operation is the same as the circuit shown in FIG. 3, the transistor Q ₈ is added. When the transistors Q ₂ and Q ₃ are turned on during the hold period, a voltage source 7 for setting the base voltage of the transistor Q _{8 is} used to prevent the transistors Q ₂ and Q _{3 from} becoming saturated. (Output voltage =
V _REF ) has been added. The output voltage V of this voltage source 7
_REF is set to satisfy the following conditions. That is,
When the H level voltage of the input clock to the base electrodes of both transistors Q ₂ and Q ₃ is V _CLKH and the power supply voltage of the circuit is V _CC , the collector electrodes (node N ₁ ) of transistors Q ₂ and Q ₃ The voltage V _{N1 is set so that} V _N1 ≧ V _CLKH . Therefore, determining the _{V N1 = V REF -V BE8 ≧} V CLKH (1) and so as to voltage VREF. However, V _BE8 in the formula (1) is the base-emitter forward voltage drop of the transistor Q _8.

[0008]

The above-mentioned improved sample hold circuit (FIG. 5) also has the following points to be improved. The offset voltage V _os during the sampling period is large. The upper limit of the input frequency to the clock terminal is low. It is difficult to reduce power consumption. The description is given below.

FIG. 6 is a diagram showing input and output waveforms of the improved sample and hold circuit shown in FIG. In FIG.
During the sampling period from t _{1 to} t ₂ , the level of the clock terminal 3 is at the H level, and the transistors Q ₁ and Q ₄ are in the ON state. On the other hand, the transistors Q ₂ and Q ₃ are off. In addition, transistors Q ₅ and Q ₆ , constant current source 6A
Is in operation. Therefore, the emitter electrode of the transistor Q ₈ (node N ₁₎ appears the same voltage waveform as the input waveform inputted from the input terminal 2. Then, the transistor Q ₈ is in the off state and the transistor Q ₇ is in the on state.
As in the output waveform shown in FIG. 6, the same voltage waveform as the input is output.

Here, to make the description concrete, each voltage, current, input / output level, etc. are set as follows. That is, power supply voltage V _CC = 5.0 V Clock terminal 3 input H level voltage V _CLKH = 1.5 V Clock terminal 3 input L level voltage V _CLKL = 1.0 V Input terminal 2 input signal amplitude V _inPP = 2.0 V _PP input Signal center value = 3.5V Input terminal 2 input signal L level voltage _VinL = 3.5-1.
0 = 2.5V Input terminal 2 input signal H level voltage _VinH = 3.5 + 1.
0 = 4.5V constant current source 6B current I ₀₂ = 400 .mu.A constant current source 6A current _{I 01 = I 02/2 =} 200μA constant current source 6C current I ₀₃ = I ₀₂ = 400μA base-emitter forward voltage of each transistor Descent V
_BE = 0.7V.

At time t ₁ in FIG.
When _inH = 4.5V, the full feedback circuit as described above, the voltage V _N1 = 4.5V at node N _1. Therefore, the output voltage V _out of _the output terminal 5 becomes _{V out = V N1 -V BE7 =} 4.5-0.7 = 3.8V (2). That is, during the sampling period, the voltage _{Vout (TS)} represented by the following equation (3) is always output as the output voltage _Vout .

V _{out (TS)} = input voltage V _in −V _BE7 (3) Next, the clock terminal is at the L level during the period t _{2 to} t ₃ , the circuit is in the hold period, and the transistors Q ₁ , Q ₄ Turns off, and the transistors Q ₂ and Q ₃ turn on. Therefore, all the above-mentioned feedback circuits are in a non-operation state,
The voltage V of the emitter electrode (node N ₁ ) of the transistor Q _{8
N1 (TH),} because the transistor Q ₈ is turned on, is fixed to the voltage represented by the following formula (4).

V _{N1 (TH)} = V _CC − (V _REF + V _BE8 ) (4) At this time, the voltage V _{out of the} output terminal becomes a constant voltage as described below. That is, the capacitor C has the time t ₂
Circuit voltage value immediately before the change to the hold period from the sampling period has been charged by the transistor Q ₇ in. In the hold period, the transistors Q ₂ and Q ₃ are turned on.
Since ₇ is turned off, the input voltage value at time t ₂ V
_{Assuming that inL} (= 2.5 V), a constant voltage of V _out = 2.5-V _BE7 = 1.8 V is obtained. That is, in the hold period, the voltage V _{out (TH)} represented by the following equation (5) is always output.

V _{out (TH)} = V _{in (t 2)} −V _BE7 (5) Next, the emitter voltage of the transistor Q ₈ during the hold period, that is, the voltage V _{N1 of the} node N ₁ and the transistor Q _{8
Will be} described. When the hold period, the emitter voltage of the transistor Q ₈ is transistor Q
₇ must be set to a voltage that cannot be turned on, that is, a value that satisfies the condition represented by the following equation (6).

V _N1 −V _{out (TH)} <V _BE7 = 0.7 V (6) Under the above condition, the voltage charged and held in the capacitor C by the transistor Q ₇ during the hold period changes. This is to prevent At this time, it is necessary to consider the output voltage at the time of the minimum input level, that is, _VinL . V _{inL (t2)} = 2.5V
Therefore, the output voltage is obtained from the equation (5) as V _{out (TH)} =
2.5-0.7 = 1.8V.

Here, assuming that the solution expressed by the equation (6) is 0 in consideration of the temperature characteristics, the voltage V _N1 becomes V _N1 = V _out =
1.8V. Therefore, the voltage V _REF of the voltage source 7 may be set so as to satisfy Expression (1) and to satisfy V _N1 = 1.8 V.

Therefore, the voltage V _REF is obtained by transforming the equation (7) from V _CC − (V _REF + V _BE8 ) = V _N1 (7), and V _REF = V _CC − (V _BE8 + V _N1 ) = 5 0.0- (0.7+
1.8) = 2.5V. From this, V _REF -V _BE8 = 2.5-0.
7 = 1.8 V, and V _REF −
The condition of V _BE8 ≧ V _CLKH = 1.5 V is also satisfied.

Next, the time after time t ₃ will be considered. FIG.
At time t ₃ , the clock terminal 3 goes high. Thus, the circuit is again in the sampling period. At this time, the transistors Q _1, Q ₄ is the transistor Q _2, Q ₃ together with the ON state by the OFF state, full feedback circuit and the transistor Q ₇ is tries to transition to the on state, the node N ₁ The voltage is applied to transistors Q ₆ , Q ₂ ,
Due to the parasitic capacitance of Q ₃ (in this case, the junction capacitance C _cb between the collector and the base and the junction capacitance C _sub between the collector and the substrate), the input signal cannot be instantaneously followed, and the period t _{3 in} FIG.
As shown in ~t _4, it rises with a certain delay time t _d. As a result, if the output voltage V _out is the original voltage (FIG. 6, the input voltage V _in at time t ₃ is the V _inH = 4.5V, therefore the original output voltage V _out from the equation (2) , V
_out = 3.8V) becomes minute only low voltage of the voltage V _os than. That is, there is a disadvantage that an offset occurs during the sampling period.

Here, the circuit conditions are set as follows, and the offset voltage V _os is estimated.

Power supply voltage V _CC = 5.0 V Clock terminal 3 input H level voltage V _CLKH = 1.5 V Clock terminal 3 input H level voltage V _CLKL = 1.0 V Input terminal 2 input signal amplitude V _inPP = 2.0 V _PP Input signal center value = 3.5V Input terminal 2 input signal L level voltage _VinL = 3.5-1.
0 = 2.5V Input terminal 2 input signal H level voltage _VinH = 3.5 + 1.
0 = 4.5V with a constant current source 6B current I ₀₂ = 400 .mu.A constant current source 6A current _{I 01 = I 02/2 =} 200μA constant current source 6C current I ₀₃ = I ₀₂ = 400μA input signal V _in is sin waveform, frequency f _in = 10MH
z, period T = 0.1 μs, parasitic capacitance C _j of node N ₁ = 2p
F.

At time t ₃ in FIG. 6, the voltage V _{N1 at} the node N ₁ is V _N1 = 1.8 V according to equation (6).
Also, since the circuit to work properly in the time t ₃ after, when the voltage value V _N1 of the node N ₁ rises to the same value as the input voltage V _in that is, a time t _4, it until the delay takes time t _d.

[0022] the voltage V _N1 rises, it is necessary to charge the parasitic capacitance C _j of the node N ₁ by the current I ₀₁ of the constant current source 6A, the time is represented by the following formula (8).

[0023] _{t d = C j · V in} (t4) / I 01 (8) At this time, the input voltage V _in is represented by the following formula (9).

V _{in (t 4)} = V _inH · sin (2π · {(1 / T) − (1 / t _d )}) (9) Solving equations (8) and (9) for the delay time t _d And the following equation (10) is obtained.

{(I ₀₁ · t _d ) / (C _j · V _inH )} + sin (2π / t _d ) = 0 (10) By solving the equation (10), t _d = 28 ns is obtained.

[0026] Next, when the output voltage V _out has ramps up with a delay time t _d, determine the offset voltage V _os of the output voltage.

V _{out (t 4)} = (V _inH −V _BE7 ) · sin (2π {(1 / T) − (1 / t _d )}) According to (11), V _{out (t 4)} = 1.61 V obtain.

[0028] The input voltage V _in at time t ₃ is V _inH = 4.
5 V and the output voltage V _out when the delay time t _d = 0
From equation (3), V _out = V _inH −V _BE7 = 4.5−
0.7 = 3.8V. Therefore, the offset voltage V _os
Than the following equation _{(12) V os = V out} (t3) -V out (t4) (12), a V _os = 3.8-1.16V = 2.64V.

From the above discussion, in the case of the conventional circuit, an offset voltage of V _os = 2.64 V is generated under the above conditions.

Next, the operating frequency of the circuit is estimated. As described above, when the duty (duty) of the input frequency f _in to the clock terminal 3 and 50%, the relationship between the half of the period, that the sampling period of the magnitude and the input frequency of the delay time t _d is the following formula When the condition of (13) is not satisfied, the sampling period becomes zero. That is, the circuit cannot respond.

T _d ≦ 1 / (2 · f _in ) (13) In the equation (13), the operation limit is set to t _d = 1 / (2 · in).
Given that f _in), the upper limit f _INmax input frequency to the clock terminal 3 is given by expression (14).

_Finmax ≦ 1 / (2 · t _d ) (14) When t _d = 28 ns is substituted into the equation (14) to obtain the upper limit input frequency _finmax , _finmax = 17.8 MHz is obtained.

As described above, in the case of the conventional circuit, the input frequency to the clock terminal 3 has an upper limit under the above-described conditions.
It is limited to _finmax = 17.8 MHz.

Next, the upper limit of the clock frequency is _defined as f _inmax =
Each constant current source current I ₀₁ , I required for 50 MHz
_02, estimate the I _03. In this case, equations (8) and (1)
4), solving for the current I ₀₁ gives the following equation (15)
Get.

[0035] _{I 01 = 2 · C j ·} V in (t4) · f inmax (15) where, V _{in (t4)} in the equation (9), T = 1 / 50MHz =
0.02 μs, 1 / t _d = 1/2 × 50 MHz = 0.0
By substituting 1 μs and V _inH = 4.5 V, V _{in (t4)} = 3.2 V is obtained.

By substituting this condition and each of the above conditions into equation (15), I ₀₁ = 640 μA is obtained.

Here, as described above, I ₀₂ = 2 · I
₀₁ , I ₀₂ = I ₀₃ , so that I ₀₂ = I ₀₃ = 2 × 640 μA = 1.28 mA. That is, in order to set f _inmax = 50 MHz, the circuit current I _cc = I ₀₁ + I ₀₂ + I ₀₃ is 3.2 mA, which must be increased 3.2 times from the initial value I _cc = 1.0 mA. . That is, in order to cope with high-speed operation, it is necessary to greatly increase the circuit current I _CC , and it is difficult to reduce power consumption.

From the above description, it can be seen that the conventional sample and hold circuit has a problem that the offset voltage during the sampling period is large. It has a large variation of the node N ₁ voltage when the operation in the sampling period from the hold period is switched, because the response speed of the order circuit is slow.

Next, there is a problem that the upper limit of the clock input frequency is low. This is because, similarly to the above-described problem, the delay time of the circuit is large, and the circuit cannot respond even if a frequency twice or more the delay time is input.

Another problem is that it is difficult to reduce power consumption. The reason is, for example, that the upper limit of the input clock frequency is 2.8 times (17.8 MHz to 50 MHz)
This is because the circuit current must be increased by a factor of 3.2 in order to achieve

Accordingly, it is an object of the present invention to provide a sample and hold circuit which has a small offset voltage during a sampling period, can be operated by a high-speed clock, and has low power consumption.

[0042]

SUMMARY OF THE INVENTION A sample and hold circuit according to the present invention provides an input signal to be sampled and held,
The amplifier is amplified by a full-feedback differential amplifier whose activation and deactivation is controlled by a differential amplifier whose current path is switched according to an external clock, and the amplified output is provided with a voltage holding capacitor at an output point. An output transistor of an emitter follower whose conduction and non-conduction is controlled by a differential amplifier whose current path is switched according to the clock is transmitted to an output terminal. A sample and hold circuit including a transistor for controlling a base potential of the output transistor when in a non-conducting state, wherein the input signal is
The base voltage of the output transistor in the non-conducting state is input to the full-feedback differential amplifier and to the base electrode of the transistor for controlling the base potential so that the base voltage of the input signal is equal to the voltage of the input signal. It is characterized by following changes.

[0043]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a sample and hold circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing input / output waveforms during the operation. FIG.
Comparing FIG. 5, this embodiment is that connecting the base electrode of the transistor Q ₈ to the input terminal 2 are conventional circuits and saying. The base electrode of the transistor Q ₈ has conventionally been fixed to a constant voltage V _REF provided by the voltage source 7. The basic circuit operation of this embodiment is the same as the conventional circuit, based on the are the input signal V _in to the base electrode of the transistor Q _8, the operation of the hold period is different from the conventional You. The differences will be described below.

[0044] The hold period in the conventional circuit shown in FIG. 5, the voltage at node N ₁ transistor Q ₇ is a voltage not become the ON state i.e., it is necessary to set the V _N1 = 1.8V. Therefore, the hold period, the node voltage V _N1 regardless of the voltage of the input signal V _in is constant, this is causing that increase the response time of the circuit.

[0045] In the circuit of this embodiment shown in FIG. 1 is connected to the base electrode input terminal 2 of the transistor Q _8, since the hold period the transistor Q _2, Q ₃ is in the on state, the transistor Q _{8 is} also on. Accordingly, the voltage V _{N1 at} the node N ₁ is not constant, but changes following the input signal Vin as _in the period t _{2 to} t _{3 in} FIG.

At this time, the voltage V _{N1 at} the node N ₁ is expressed by the following equation (16).

V _N1 = V _in -V _BE8 (16) Next, FIG. 2 (this embodiment) and FIG. 6 (conventional circuit)
At time t ₃ , consider the amount of change ΔV _N1 in the voltage at node N ₁ when the circuit switches from the hold period to the sampling period. Input voltage V _in at this time is in the H level,
Since V _in = V _inH , the following is obtained.

ΔV _N1 (conventional circuit) = V _inH −V _N1 =
4.5-1.8 = 2.7V ΔV _{N1 (Embodiment) = V inH - (V in} -V BE8) where the input voltage V _in at time t _3, all the feedback circuit is operated are therefore a V _in = V _inH, therefore, the amount of change in node voltages in this embodiment, [Delta] V _{N1 (embodiment) = V inH - (V inH} -V BE8) = V BE8 = 0.7V (17)

[0049] Thus, this embodiment requires the variation [Delta] V _N1 of the node voltage is 1/4 of the conventional, the offset voltage V _os small, high speed operation.

Next, the estimation performed on the conventional circuit will be performed on the present embodiment under the same conditions as those of the conventional circuit. First, the delay time t in FIG.
_d is t _d = C _j · V _{in (t 4)} / I ₀₁ (18), as in the equation (8).

[0051] In addition, the input voltage V _in at this time, equation (17)
_Therefore , Vin _(t4) = _VBE8 = 0.7V is constant.

Therefore, substituting each condition into equation (18), t
Solving for _d gives t _d = 7.0 ns.

Next, when the output voltage V _out is t _d = 0.7 ns
Offset voltage V of output voltage when rising with delay of
_os is V _{out (t 4)} = (V _inH −V _BE7 ) · sin (2π {(1 / T) − (1 / t _d )}) (19) as in the equation (11). From this equation (19), V _{out (t4)} = 1.8 V is obtained.

[0054] The input voltage V _in at time t ₃ is V _inH = 4.
It is 5V, and the output voltage when t _d = 0 is V _out = V _inH -V _BE7 = 4.5-0.7 = _3.8V as in the equation (3). Therefore, the offset voltage V _os becomes V _os = V _{out (t 3)} −V _{out (t 4)} (20) as in the equation (12), and V _os = 3.8−2.0 = 1.8 V Become.

As described above, under the above-described conditions, an offset voltage of 2.64 V is generated in the case of the conventional circuit, whereas V _os = 1.8 V in the present embodiment,
0.84V can be improved.

Next, the operating frequency will be considered. The upper limit of the operating frequency is _finmax ≦ 1 / (2 · t _d ) (21), as in Expression (14). Substituting t _d = 7 ns into equation (21) gives f
_inmax = 71.4 MHz is obtained.

As described above, under the above-mentioned conditions, the case where the conventional circuit had a _finmax = 17.8 MHz was used.
In the present embodiment, _finmax = 71.4 MHz,
About a four-fold improvement is made.

Next, the upper limit of the operating frequency is _defined as f _inmax = 50.
MHz necessary constant current source currents I ₀₁ , I ₀₂ , I
I'll ask for ₀₃ . Current I _01, similarly to the equation (15), a _{I 01 = 2 · C j ·} V in (t4) · f inmax (22). Substituting the same condition (Vin _(t4) = 0.7 V) in the conventional circuit into the equation (22), I ₀₁ = 1
Obtain 40 μA. Also, as described above, I ₀₂ = I ₀₃ =
2 × 140 = 280 μA. Therefore, f _inmax = 5
In order to set it to 0 MHz, the circuit current I _cc = I ₀₁ + I ₀₂ +
I ₀₃ = 700 μA, and I _cc =
1 / 4.5 is enough for 3.2 mA. finmax = 50M
The fact that the circuit current required for setting the frequency to 1 Hz is only 1 / 4.5 means that the power consumption is 1 / 4.5, and therefore, the power consumption is significantly reduced. .

Note that f at the same circuit current as the conventional circuit
If we estimate the _inmax, because it is _{f inmax = I 01 / (2} · C j · V in (t4)) (23), f by substituting each condition _inmax = 228MHz
Get. That is, when the power consumption is the same as that of the conventional circuit, the _finmax is further increased by 4.56 times.

[0060] Moreover, in this embodiment, the base voltage supply voltage source of the transistor Q ₈ (in FIG. 5, the voltage source 7) because it is unnecessary, simplification of the circuit, miniaturization, can be low cost is there.

[0061]

As described above, the sample and hold circuit of the present invention provides an input signal to be sampled and held as a base input to a transistor for controlling the base potential of an output emitter follower transistor. Thus, the change in the base potential of the output transistor when switching from the hold period to the sampling period is reduced so that the base potential of the output transistor follows the change in the input signal during the hold period.

Thus, according to the present invention, it is possible to provide a sample and hold circuit which has a small offset voltage during a sampling period, can operate with a high-speed clock, and has low power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a sample and hold circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing input / output waveforms during operation of the circuit shown in FIG. 1;

FIG. 3 is a circuit diagram of an example of a conventional sample and hold circuit.

FIG. 4 is a diagram showing input / output waveforms during operation of the circuit shown in FIG. 3;

FIG. 5 is a circuit diagram of another example of a conventional sample and hold circuit.

FIG. 6 is a diagram showing input / output waveforms during operation of the circuit shown in FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 power supply terminal 2 input terminal 3 clock terminal 4 ground terminal 5 output terminal 6A, 6B, 6C constant current source 7 voltage source

Claims (3)

[Claims] An input signal to be sampled and held is amplified by an all-feedback differential amplifier whose activation and deactivation is controlled by a differential amplifier whose current path switches according to an external clock, and the amplification is performed. An output is provided with a capacitor for holding a voltage at an output point, and the output is transmitted to an output terminal by an output transistor of an emitter follower whose conduction and non-conduction is controlled by a differential amplifier whose current path is switched according to the clock, A sample-and-hold circuit including a transistor between a power supply terminal and a base electrode of the output transistor for controlling a base potential of the output transistor when in a non-conductive state, wherein the input signal is the full feedback type Input to the differential amplifier and also to the base electrode of the transistor for controlling the base potential. Sample-and-hold circuit the base voltage of the output transistor when in a non-conductive state, characterized in that it has to follow the voltage change of the input signal. 2. An all feedback first differential amplifier for amplifying an input signal to be sampled and held by full feedback, and an output for transmitting an output signal of the first differential amplifier to an output terminal by an emitter follower. By using a transistor and a non-inverted and inverted signal of a clock supplied from the outside as base inputs of transistors forming a differential pair, a current path is switched in accordance with the level of the clock, whereby the first differential amplifier is switched. A second differential amplifier to be activated or deactivated; and a non-inverted / inverted signal of the clock being used as a base input of each of bipolar transistors forming a differential pair, a current path being switched according to the level of the clock. A third transistor for turning on or off the output transistor in response to activation or deactivation of the first differential amplifier. A differential amplifier, a capacitor for storing signal charges output from the output transistor in a conductive state, and a current path between a power supply potential supply point and a base electrode of the output transistor. And a base potential control transistor for providing a base potential for holding the non-conducting state when the transistor is in a non-conducting state, wherein the input signal is input to the first differential amplifier, When the output transistor is in a non-conductive state during a hold period determined by the clock level, the base voltage of the output transistor follows a change in the voltage of the input signal. Sample sample, characterized in that the sample Field circuit. 3. An npn-type first bipolar transistor having a collector electrode connected to a power supply terminal and a base electrode connected to an input terminal, and a collector electrode and a base electrode commonly connected to form a first constant current source. A first differential amplifier having an npn-type second bipolar transistor connected to the power supply terminal through a common terminal and a respective emitter electrode connected in common, and a collector electrode connected to the first and second bipolar transistors. An npn-type third bipolar transistor connected to a common emitter electrode of the transistor and having an external clock signal input to a base electrode; a collector electrode connected to a common collector / base electrode of the second bipolar transistor; An npn-type fourth bipolar transistor whose electrode receives an inverted signal of the clock signal; With an emitter electrode connected in common of said first
A second differential amplifier connected to a ground terminal via a second constant current source for supplying a current twice the current of the constant current source, and a collector electrode connected to the first and second bipolar transistors. An npn-type fifth bipolar transistor connected to a common emitter electrode and having a base electrode to which an inverted clock signal from the outside is input, a collector connected to the output terminal, and np having the base electrode supplied with the clock signal
an n-type sixth bipolar transistor, the emitter terminal of which is connected in common, and a third constant current source for supplying a current twice as large as the current of the first constant current source to the ground terminal. And a collector electrode connected to the power supply terminal, an emitter electrode connected to the collector electrode and the output terminal of the sixth bipolar transistor, and a base electrode connected to the second differential amplifier. An npn-type seventh bipolar transistor connected to a common collector / base electrode of the bipolar transistor; and a capacitor connected between the output terminal and the ground terminal, wherein the power supply terminal and the seventh bipolar transistor are connected. A sample-and-hold circuit having a configuration in which an npn-type eighth bipolar transistor is provided so as to form a current path between base electrodes of the transistors A base electrode of the eighth bipolar transistor is connected to the input terminal, and a base voltage of the seventh bipolar transistor during a period in which the clock is at a low level follows a change in a voltage of the input terminal during the period. A sample-and-hold circuit characterized in that: