JPH1012421A - Multiple chip electronic component and its manufacture - Google Patents

Multiple chip electronic component and its manufacture

Info

Publication number
JPH1012421A
JPH1012421A JP8157231A JP15723196A JPH1012421A JP H1012421 A JPH1012421 A JP H1012421A JP 8157231 A JP8157231 A JP 8157231A JP 15723196 A JP15723196 A JP 15723196A JP H1012421 A JPH1012421 A JP H1012421A
Authority
JP
Japan
Prior art keywords
film
chip
electrode
surface film
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8157231A
Other languages
Japanese (ja)
Inventor
Masanobu Ito
雅信 伊藤
Yoshio Sasaki
好男 佐々木
Eiji Kobayashi
永司 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koa Corp
Original Assignee
Koa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koa Corp filed Critical Koa Corp
Priority to JP8157231A priority Critical patent/JPH1012421A/en
Publication of JPH1012421A publication Critical patent/JPH1012421A/en
Pending legal-status Critical Current

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  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a multiple chip electronic component wherein, when swarf and evaporized materials stick to a part between surface film type electrodes of both sides of a chip substratum which are produced by adjustment or the like of electronic element bodies formed on the chip substratum, bridges or short circuit are not caused at the plating process of an electrode plating layer in the later processes, and a manufacturing method of it. SOLUTION: A plurality of pairs of surface film type electrodes 12 are formed on the surface of an insulating chip substratum 10 along both side edges facing each other. The respective electronic element bodies 13 are formed between the surface film type electrodes 12 of both sides making pairs. Protective films 15, 17 are formed on almost the entire surface containing space parts 14 between the adjacent surface film type electrodes 12, exposing the surface film type electrodes 12 on the surface of the chip substratum 10. Electrode plating layers 18 are formed on the surface film type electrodes 12, on the end surface of the chip substratum 10.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば複数の抵抗
素子体、抵抗素子体とコンデンサ素子体、抵抗素子体ま
たはコンデンサ素子体とコイル素子体などの複数の電子
素子体を組合せた多連型チップ電子部品及びその製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple type combining a plurality of electronic elements such as a plurality of resistor elements, a resistor element and a capacitor element, or a resistor element or a capacitor element and a coil element. The present invention relates to a chip electronic component and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来のこの種の多連型チップ電子部品
は、図8に示すように、絶縁性素体の各チップ基体1の
表面に両側縁に沿って互いに対向して複数対の表面膜状
電極2、端面膜状電極および裏面膜状電極を印刷焼成に
より形成し、この各対をなす両側の表面膜状電極2間に
それぞれ抵抗素子体、コンデンサ素子体、コイル素子体
などの電子素子体3を印刷焼成により形成し、前記チッ
プ基体1の表面に前記表面膜状電極2およびこの隣接す
る表面膜状電極2間の空間部4を露出させて電子素子体
3およびこの隣接する電子素子体3間の空間部5を覆う
第1のガラス保護膜6を印刷焼成により形成し、次い
で、電子素子体3を切削刃、サンドブラストまたはレー
ザ光などにより切削または蒸発させてトリミング溝3aな
どで抵抗値、容量などを調整し、さらに、前記ガラス保
護膜6の表面に第2のガラス保護膜7を印刷焼成により
形成し、さらに、前記絶縁性素体を各チップ基体1ごと
に切断し、この切断したチップ基体1の表面膜状電極、
端面膜状電極および裏面膜状電極から裏面に亘って前記
表面膜状電極2に接続する化学処理による電極メッキ層
8,9を形成する方法が採られていた。
2. Description of the Related Art As shown in FIG. 8, a conventional multi-chip electronic component of this type has a plurality of pairs of surfaces opposing each other along both side edges on the surface of each chip base 1 of an insulating body. The film electrode 2, the end face film electrode, and the back film electrode are formed by printing and baking, and the electronic elements such as a resistor element, a capacitor element, and a coil element are respectively disposed between each pair of the surface film electrodes 2 on both sides. The element body 3 is formed by printing and baking, and the surface film electrode 2 and the space 4 between the adjacent surface film electrodes 2 are exposed on the surface of the chip base 1 so as to expose the electronic element body 3 and the adjacent electrons. A first glass protective film 6 covering the space 5 between the element bodies 3 is formed by printing and baking, and then the electronic element body 3 is cut or evaporated by a cutting blade, sandblast, laser light, or the like, and is trimmed with a trimming groove 3a or the like. Resistance value, capacity, etc. After adjustment, a second glass protective film 7 is formed on the surface of the glass protective film 6 by printing and baking, and the insulative body is cut for each chip substrate 1. Surface membrane electrode,
A method of forming the electrode plating layers 8 and 9 by chemical treatment for connecting to the front surface film electrode 2 from the end surface film electrode and the back surface film electrode to the back surface has been adopted.

【0003】[0003]

【発明が解決しようとする課題】上記従来の多連型チッ
プ電子部品は、チップ基体1の両側縁に沿って形成され
る表面膜状電極2の隣接した表面膜状電極2間は保護膜
6,7が形成されていないため、電子素子体3のトリミ
ングで形成される切削または蒸発によるトリミング溝3a
により発生する切削屑、蒸発物質が隣接した表面膜状電
極2間に飛散してチップ基体の表面に付着することがあ
る。
In the above-mentioned conventional multiple chip electronic component, the protective film 6 is provided between the adjacent surface film electrodes 2 of the surface film electrodes 2 formed along both side edges of the chip base 1. , 7 are not formed, so that the trimming grooves 3a formed by cutting or evaporating the electronic element body 3 are formed.
In some cases, cutting chips and evaporating substances generated by the scattering may be scattered between the adjacent surface film electrodes 2 and adhere to the surface of the chip base.

【0004】この飛散物質には電子素子体3およびガラ
ス保護膜6に、また電子素子体3がコイル素子体の場合
は中心の貫通孔の導電膜に各成分の金属物質、ガラス物
質が含まれ、この飛散物質が付着していると、チップ基
体1の端面から裏面に亘ってメッキなどの化学処理によ
り前記表面膜状電極2に接続した電極を形成する場合、
飛散物質が後工程の電極メッキ層8,9の形成工程でメ
ッキの核または核生成の原因となり、隣接する表面膜状
電極2間のブリッジ若しくは短絡が生じるなどの不良品
発生の原因となり、歩留まりが悪いなどの問題を有して
いた。
[0004] The scattered substance contains a metal substance and a glass substance of each component in the electronic element body 3 and the glass protective film 6, and when the electronic element body 3 is a coil element body, the conductive film in the central through hole. When the scattered substance is attached, when an electrode connected to the surface film electrode 2 is formed by chemical treatment such as plating from the end face to the back face of the chip base 1,
The scattered substance causes plating nuclei or nucleation in the subsequent step of forming the electrode plating layers 8 and 9, and causes defective products such as bridges or short circuits between adjacent surface film-shaped electrodes 2. Had a problem such as bad.

【0005】本発明は上記問題点に鑑みなされたもの
で、チップ基体に形成した電子素子体の調整などにより
生じる切削屑、蒸発物質がチップ基体の両側の表面膜状
電極間に付着しても後工程の電極メッキ層のメッキ処理
時にブリッジ若しくは短絡の原因の発生となることがな
い多連型チップ電子部品及びその製造方法を提供するも
のである。
The present invention has been made in view of the above-mentioned problems. Even if cutting chips and evaporative substances generated by adjustment of an electronic element formed on a chip base adhere to the surface film electrodes on both sides of the chip base. An object of the present invention is to provide a multiple chip electronic component which does not cause a bridge or a short circuit at the time of plating of an electrode plating layer in a later step, and a method of manufacturing the same.

【0006】[0006]

【課題を解決するための手段】請求項1記載の発明の多
連型チップ電子部品は、絶縁性のチップ基体と、このチ
ップ基体の表面に両側縁に沿って互いに対向して形成さ
れた複数対の表面膜状電極と、この表面膜状電極に接続
され前記チップ基体の端面に形成された端面膜状電極
と、この端面膜状電極に接続され前記チップ基体の裏面
に形成された裏面膜状電極と、前記チップ基体の各対を
なす両側の表面膜状電極間にそれぞれ形成された電子素
子体と、前記チップ基体の表面に前記膜状電極を露出さ
せてこの隣接する表面膜状電極間の空間部を含めてほぼ
全面に形成した保護膜と、前記チップ基体の表面膜状電
極、端面膜状電極および裏面膜状電極上に形成された電
極メッキ層とを備えたものである。
According to a first aspect of the present invention, there is provided a multi-chip electronic component comprising: an insulating chip base; and a plurality of chip bases formed on the surface of the chip base and opposed to each other along both side edges. A pair of surface film electrodes, an end film electrode connected to the surface film electrode and formed on the end surface of the chip base, and a back film formed on the back surface of the chip base connected to the end film electrode and connected to the end film electrode Electrode element, an electronic element body formed between each pair of surface film electrodes on both sides of the chip substrate, and an adjacent surface film electrode exposing the film electrode on the surface of the chip substrate. A protective film is formed on substantially the entire surface including the space between the electrodes, and a surface plating electrode, an end plating electrode, and an electrode plating layer formed on the back film electrode of the chip substrate.

【0007】そして、絶縁性チップ基体の両側縁に沿っ
て形成される隣接した表面膜状電極間は保護膜が形成さ
れているため、電子素子体のトリミングなどで抵抗値、
容量などの調整で形成される切削または蒸発溝により発
生する金属物質、ガラス物質などが含まれる飛散物質が
隣接した表面膜状電極間に飛散しても、隣接する表面膜
状電極間の空間部を含めてほぼ全面に形成した保護膜に
より覆われ、後工程の電極メッキ層の形成工程で、隣接
する表面膜状電極間のブリッジ若しくは短絡が生じるな
どの不良品発生の原因となることがない。
Since a protective film is formed between adjacent surface film-like electrodes formed along both side edges of the insulating chip substrate, the resistance value is reduced by trimming the electronic element body.
Even if scattered substances including metal substances and glass substances generated by cutting or evaporation grooves formed by adjusting the capacity etc. scatter between adjacent surface film electrodes, the space between adjacent surface film electrodes Is covered with a protective film formed on almost the entire surface, including the surface, and does not cause defective products such as a bridge or a short circuit between adjacent surface film electrodes in a later step of forming an electrode plating layer. .

【0008】請求項2記載の発明の多連型チップ電子部
品の製造方法は、複数のチップ基体を連接した絶縁性素
板の表面に前記各チップ基体の両側縁に沿って互いに対
向して複数対の表面膜状電極、各チップ基体の両側縁に
貫通した貫通孔の内周面に端面膜状電極および各チップ
基体の裏面に裏面膜状電極を形成する工程と、この各チ
ップ基体表面の前記各対をなす両側の表面膜状電極間に
電子素子体をそれぞれ形成する工程と、前記各チップ基
体の表面に少くとも前記電子素子体を被覆するととも
に、表面膜状電極を露出させて形成した第1の保護膜を
形成する工程と、前記各チップ基体の各電子素子体をト
リミングする工程と、前記各チップ基体の第1の保護膜
の表面に第2の保護膜を形成する工程と、前記絶縁性素
板を各チップ基体ごとに切断する工程と、前記チップ基
体の表面膜状電極、端面膜状電極および裏面膜状電極上
に電極メッキ層を形成する工程とを含むものである。
According to a second aspect of the present invention, there is provided a method of manufacturing a multiple chip electronic component, wherein a plurality of chip bases are connected to each other along a side edge of each of the chip bases on a surface of an insulating plate connected to the plurality of chip bases. Forming a pair of surface film electrodes, an end surface film electrode on the inner peripheral surface of a through hole penetrating through both side edges of each chip substrate, and a back film electrode on the back surface of each chip substrate; A step of forming an electronic element body between the pair of surface film electrodes on both sides, and a step of coating at least the electronic element body on the surface of each chip base and exposing the surface film electrode. Forming a first protective film, trimming each electronic element body of each chip substrate, and forming a second protective film on the surface of the first protective film of each chip substrate. And the insulating base plate is attached to each chip base. It is intended to include a step of cutting, the surface film electrode of the chip substrate, and forming an electrode plated layer on the end face film electrode and the back surface film electrode on.

【0009】そして、複数のチップ基体を連接した絶縁
性素板の表面に各チップ基体の両側縁に沿って互いに対
向して複数対の表面膜状電極、端面膜状電極および裏面
膜状電極を形成する工程に引き続き、この各チップ基体
の表面に各対をなす両側の表面膜状電極間に電子素子体
をそれぞれ形成する工程が行われた後、次の工程で各チ
ップ基体の表面に少くとも電子素子体を被覆するととも
に、表面膜状電極を露出させてこの隣接する膜状電極間
の空間部を含めてほぼ全面に第1の保護膜が形成され、
この工程に次いで行われる各チップ基体の各電子素子体
をトリミングする工程において飛散した切削屑、蒸発物
質が隣接した表面膜状電極間に飛散して第1の保護膜上
に付着しても、この工程の後に行われる工程で形成され
る第2の保護膜にて被覆され、後工程の表面膜状電極、
端面膜状電極および裏面膜状電極上に形成される電極メ
ッキ層を形成する工程で隣接する表面膜状電極間のブリ
ッジ若しくは短絡などの不良品発生の原因となることが
ない。
A plurality of pairs of surface film electrodes, end film electrodes, and back film electrodes are provided on the surface of the insulating base plate having a plurality of chip substrates connected to each other along both side edges of each chip substrate. Subsequent to the forming step, after a step of forming an electronic element body between each pair of surface film-like electrodes on each surface of each chip base is performed on the surface of each chip base, the surface of each chip base is slightly lessened in the next step. In addition to covering the electronic element body, the first protective film is formed on almost the entire surface including the space between the adjacent film electrodes by exposing the surface film electrode,
In the step of trimming each electronic element body of each chip base performed after this step, even if cutting chips scattered and evaporated substances scatter between adjacent surface film electrodes and adhere to the first protective film, This is covered with a second protective film formed in a step performed after this step, and a surface film electrode in a subsequent step is provided.
In the step of forming the electrode plating layer formed on the end surface film-shaped electrode and the back surface film-shaped electrode, a defective product such as a bridge or a short circuit between adjacent surface film-shaped electrodes does not occur.

【0010】[0010]

【発明の実施の形態】次に本発明の多連型チップ電子部
品の一実施の形態について図1に基いて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a multiple chip electronic component of the present invention will be described with reference to FIG.

【0011】図1において、10はセラミックにて形成さ
れた絶縁性のチップ基体で、このチップ基体10の両側縁
に沿って複数箇所に半円弧状の凹部11が所定間隔ごとに
互いに対向して形成されている。そして、このチップ基
体10の表面には両側縁に沿って前記凹部11の位置に互い
に対向して複数対の表面膜状電極12が形成され、また、
この表面膜状電極12に連続して前記凹部11の端面部に端
面膜状電極19が形成され、さらに、この端面膜状電極19
に連続してチップ基体10の裏面に裏面膜状電極が形成さ
れている。この各表面膜状電極12は、例えば銀ーパラジ
ウム系ペーストを印刷して焼成することにより形成され
ている。
In FIG. 1, reference numeral 10 denotes an insulative chip base made of ceramic, and semicircular concave parts 11 are provided at a plurality of positions along both side edges of the chip base 10 at predetermined intervals. Is formed. Then, a plurality of pairs of surface film-like electrodes 12 are formed on the surface of the chip substrate 10 at positions corresponding to the concave portions 11 along both side edges so as to face each other.
An end face film-like electrode 19 is formed on the end face part of the concave portion 11 following the surface film-like electrode 12, and further, the end face film-like electrode 19 is formed.
The back surface film-like electrode is formed on the back surface of the chip substrate 10 continuously. Each surface film electrode 12 is formed by printing and baking a silver-palladium paste, for example.

【0012】また、このチップ基体10の両側縁に沿って
互いに対をなす各両側の表面膜状電極12間には両端部が
この表面膜状電極12に重ねて接続される電子素子体13が
それぞれ形成されている。
An electronic element body 13 whose both ends are overlapped and connected to the surface film-shaped electrodes 12 is formed between the surface film-shaped electrodes 12 on both sides of the chip base 10 along both side edges. Each is formed.

【0013】この電子素子体13は、例えば酸化ルテニウ
ム( RuO2 ) 系ペーストを印刷して焼成により形成した
抵抗素子体、または、チタン酸バリウム( BaTiO2 )系
ペーストを印刷して焼成により形成したコンデンサ素子
体、或いは、金、銀、アルミニウム、クロム、ニッケ
ル、銅またはこれらの合金、好ましくは銅系ペーストを
印刷して焼成にすることによりコイルまたはインダクタ
素子体が形成されている。なお、銅系ペーストを用いる
ときは酸化されやすいため、非酸化雰囲気中にて焼成す
る。
The electronic element body 13 is formed by, for example, printing a ruthenium oxide (RuO 2 ) -based paste and forming it by firing, or a barium titanate (BaTiO 2 ) -based paste by printing and firing. A coil or inductor element is formed by printing and firing a capacitor element body, or gold, silver, aluminum, chromium, nickel, copper or an alloy thereof, preferably a copper-based paste. Note that when a copper-based paste is used, it is easily oxidized, so that it is fired in a non-oxidizing atmosphere.

【0014】そして、抵抗素子体のみを複数並列に形成
した多連型、抵抗素子体とコンデンサ素子体とを組合せ
た多連型、抵抗素子体とコンデンサ素子体とを組合せた
多連型、抵抗素子体とコイルまたはインダクタ素子体と
を組合せた多連型、またはコンデンサ素子体とコイルま
たはインダクタ素子体とを組合せた多連型など適宜の素
子体を組合せたネットワークを構成している。
A multiple type in which only a plurality of resistor elements are formed in parallel, a multiple type in which a resistor element and a capacitor element are combined, a multiple type in which a resistor element and a capacitor element are combined, and a resistor A network is formed by combining appropriate element bodies such as a multiple type combining an element body and a coil or an inductor element body, or a multiple type combining a capacitor element body and a coil or an inductor element body.

【0015】さらに、前記チップ基体10の表面に前記表
面膜状電極12を露出させてこの表面膜状電極12と重なら
ないようにこの隣接する表面膜状電極12間の空間部14を
含めて前記電子素子体13を覆うようにほぼ全面にホウ・
ケイ酸鉛系ガラスをペースト化して印刷した後に焼成し
た第1の保護膜15が形成されている。なお、前記チップ
基板10の両端部には第1の保護膜15は形成されていな
い。
Further, the surface film-like electrode 12 is exposed on the surface of the chip base 10 and includes a space portion 14 between the adjacent surface film-like electrodes 12 so as not to overlap with the surface film-like electrode 12. Almost all over the electronic element body 13
A first protective film 15 is formed by forming a lead silicate-based glass into a paste, printing and firing the paste. Note that the first protective films 15 are not formed on both ends of the chip substrate 10.

【0016】そして、前記電子素子体13には切削刃、サ
ンドブラストまたはレーザ光などにより切削または蒸発
させて抵抗値、容量などがトリミング調整されている。
このとき、電子素子体13は第1の保護膜15にて被覆され
ているため、レーザ光などによるトリミング時に熱損な
どの障害がなく、確実にトリミング調整できる。例え
ば、抵抗素子体の場合には中央部に前記チップ基体10の
表面が露出されるように調整トリミング溝16にて抵抗値
の調整がなされている。
The electronic element 13 is cut or evaporated by a cutting blade, sand blast, laser light, or the like, so that the resistance value, the capacity, and the like are trimmed.
At this time, since the electronic element body 13 is covered with the first protective film 15, there is no obstacle such as heat loss at the time of trimming by laser light or the like, and the trimming can be surely adjusted. For example, in the case of a resistance element body, the resistance value is adjusted in the adjustment trimming groove 16 so that the surface of the chip base 10 is exposed at the center.

【0017】この電子素子体13がトリミング調整された
チップ基体10の表面には、前記表面膜状電極12を露出さ
せてこの表面膜状電極12と重ならないようにこの隣接す
る表面膜状電極12間の空間部14を含めて前記電子素子体
13を覆うようにほぼ全面にホウ・ケイ酸鉛系ガラスをペ
ースト化して印刷した後に焼成した第2の保護膜17が形
成されている。
The surface film electrode 12 is exposed on the surface of the chip base 10 where the electronic element body 13 is trimmed and adjusted so as not to overlap with the surface film electrode 12. The electronic element body including the space 14 between
A second protective film 17 is formed on almost the entire surface so as to cover 13, which is formed by pasting and printing boro-lead silicate glass and then firing.

【0018】なお、前記隣接する表面膜状電極12間およ
び電子素子体13間の前記第1の保護膜15および/または
第2の保護膜17の厚みは表面膜状電極12若しくは端面膜
状電極19の厚みより薄いかまたは同一厚みで、表面膜状
電極12若しくは端面膜状電極19の表面より突出されない
ようになっている。
The thickness of the first protective film 15 and / or the second protective film 17 between the adjacent surface film electrodes 12 and between the electronic element bodies 13 depends on the thickness of the surface film electrode 12 or the end surface film electrode. The thickness is smaller than or equal to the thickness of 19, so that it does not protrude from the surface of the surface film electrode 12 or the end surface film electrode 19.

【0019】次いで、前記チップ基体10の表面膜状電極
12、端面膜状電極19および裏面膜状電極上は電極メッキ
層18が形成されている。
Next, the surface film electrode of the chip base 10
12, an electrode plating layer 18 is formed on the end face film electrode 19 and the back film electrode.

【0020】なお、チップ基体10の端面、裏面にも、必
要に応じて、前記表面膜状電極12に接続された電子素子
体を形成してネットワーク回路を形成することができ
る。
A network circuit can be formed on the end face and the back face of the chip base 10 by forming an electronic element body connected to the surface film electrode 12 as required.

【0021】次に、この実施の形態の作用を説明する。Next, the operation of this embodiment will be described.

【0022】絶縁性のチップ基体10の両側縁に沿って形
成される隣接した表面膜状電極12間は第1および第2の
保護膜15,17が形成されているため、電子素子体13のト
リミングなどで抵抗値、容量などの調整で形成される切
削または蒸発溝により発生する切削屑、蒸発物質が隣接
した表面膜状電極12間に飛散し、第1の保護膜15上に付
着し、第1の保護膜15に各成分の金属物質、ガラス物質
が含まれている飛散物質が付着しても、この第1の保護
膜15の上に表面膜状電極12間の空間部を含めてほぼ前面
に第2の保護膜17が形成されているので、電極メッキ層
18の形成工程で隣接する表面膜状電極12間のブリッジ若
しくは短絡などが生じることがない。
Since the first and second protective films 15 and 17 are formed between the adjacent surface film electrodes 12 formed along both side edges of the insulating chip substrate 10, the Cutting chips and evaporating substances generated by cutting or evaporating grooves formed by adjusting the resistance value, capacity, etc. by trimming or the like are scattered between adjacent surface film electrodes 12 and adhere to the first protective film 15, Even if a scattered substance containing a metallic substance and a glass substance of each component adheres to the first protective film 15, the first protective film 15 including the space between the surface film electrodes 12 is formed on the first protective film 15. Since the second protective film 17 is formed almost on the front surface, the electrode plating layer
In the step of forming 18, no bridge or short circuit between the adjacent surface film-like electrodes 12 occurs.

【0023】なお、前記実施の形態では第1の保護膜15
は表面膜状電極12を露出させてチップ基体10のほぼ全面
に形成したが、少くとも電子素子体13が被覆されておれ
ばよい。
In the above embodiment, the first protective film 15
Is formed on almost the entire surface of the chip base 10 by exposing the surface film-like electrode 12, but it is sufficient that at least the electronic element body 13 is covered.

【0024】次に、本発明の多連型チップ電子部品の製
造方法の一実施の形態について図2ないし図7に基いて
説明する。
Next, an embodiment of a method of manufacturing a multiple chip electronic component according to the present invention will be described with reference to FIGS.

【0025】図2において、20はセラミックにて形成さ
れた絶縁性素板で、多数のチップ基体10を分割形成でき
るように切断溝21が縦横方向に形成されている。このチ
ップ基体10の長手方向となる両側縁の切断溝21に沿って
複数箇所に円状の貫通孔22が所定間隔ごとに互いに対向
して形成されている。この貫通孔22は切断溝21に沿った
切断によって形成されたチップ基体10の両側縁に円弧状
の凹部11となる。
In FIG. 2, reference numeral 20 denotes an insulative base plate formed of ceramic, and has cut grooves 21 formed in the vertical and horizontal directions so that a large number of chip bases 10 can be dividedly formed. Circular through holes 22 are formed at a plurality of locations along the cutting grooves 21 on both side edges which are the longitudinal direction of the chip base 10 so as to face each other at predetermined intervals. The through holes 22 form the arc-shaped concave portions 11 on both side edges of the chip base 10 formed by cutting along the cutting grooves 21.

【0026】そして、第1の工程は、図2に示すように
この複数のチップ基体10を連接した絶縁性素板20の表面
に前記各チップ基体10の両側縁に沿って互いに対向して
複数対の表面膜状電極12を形成するとともに端面膜状電
極19および裏面膜状電極を形成する工程で、このチップ
基体10の表面に両側縁に沿って前記凹部11の位置に互い
に対向して複数対の表面膜状電極12を形成する。この表
面膜状電極12の形成工程で、貫通孔22から吸引して表面
膜状電極12のペーストを貫通孔22に流動させる。次い
で、絶縁性素板20を反転して各チップ基体10の裏面に裏
面膜状電極を形成する。この裏面膜状電極の形成工程
で、貫通孔22から吸引して裏面膜状電極のペーストを貫
通孔22に流動させ、貫通孔22の内周面にて表面膜状電極
12のペーストと裏面膜状電極のペーストとを接続して焼
成することにより端面膜状電極19が形成される。なお、
この表面膜状電極12、端面膜状電極19および裏面膜状電
極は、例えば銀ーパラジウム系ペーストを印刷して焼成
することにより形成される。
In the first step, as shown in FIG. 2, a plurality of chip bases 10 are connected to each other along the side edges of each of the chip bases 10 on the surface of the insulating base plate 20 connecting the plurality of chip bases 10. In the step of forming the pair of surface film-shaped electrodes 12 and forming the end surface film-shaped electrodes 19 and the back film-shaped electrodes, the surface of the chip base 10 is opposed to each other at the position of the concave portion 11 along both side edges. A pair of surface film electrodes 12 is formed. In the step of forming the surface film-like electrode 12, the paste of the surface film-like electrode 12 is sucked from the through-hole 22 and flows into the through-hole 22. Next, the insulating base plate 20 is inverted to form a back film electrode on the back surface of each chip base 10. In the step of forming the back film electrode, the paste of the back film electrode is sucked from the through-hole 22 to flow the paste of the back film electrode into the through hole 22, and the surface film electrode is formed on the inner peripheral surface of the through hole 22.
The end face film-like electrode 19 is formed by connecting the paste of No. 12 and the paste of the back face film-like electrode and firing. In addition,
The surface film electrode 12, the end surface film electrode 19, and the back film electrode are formed, for example, by printing and firing a silver-palladium paste.

【0027】第2の工程は、図3に示すようにこの各チ
ップ基体10の各対をなす両側の表面膜状電極12間に電子
素子体13をそれぞれ形成する工程で、このチップ基体10
の両側縁に沿って互いに対をなす各両側の表面膜状電極
12間に両端部がこの表面膜状電極12に重ねて接続される
電子素子体13をそれぞれ形成する。この電子素子体13
は、例えば酸化ルテニュウム( RuO2 ) 系ペーストを印
刷して焼成により形成した抵抗素子体、または、チタン
酸バリウム( BaTiO2 )系ペーストを印刷して焼成によ
り形成したコンデンサ素子体、或いは、金、銀、アルミ
ニウム、クロム、ニッケル、銅またはこれらの合金な
ど、好ましくは銅系ペーストを印刷して焼成によりコイ
ルまたはインダクタ素子体を形成する。
In the second step, as shown in FIG. 3, an electronic element body 13 is formed between each pair of surface film electrodes 12 on both sides of each chip substrate 10, and the chip substrate 10 is formed.
Surface membrane electrodes on each side paired with each other along both sides of the
An electronic element body 13 whose both ends are connected to the surface film-like electrode 12 is formed between the two. This electronic element body 13
For example, a resistor element formed by printing and firing a ruthenium oxide (RuO 2 ) -based paste, a capacitor element formed by printing and firing a barium titanate (BaTiO 2 ) -based paste, or gold, A coil or inductor element body is formed by printing a silver-based paste, preferably a copper-based paste such as silver, aluminum, chromium, nickel, copper, or an alloy thereof, followed by firing.

【0028】そして、抵抗素子体のみを複数並列に形成
した多連型、抵抗素子体とコンデンサ素子体とを組合せ
た多連型、抵抗素子体とコンデンサ素子体とを組合せた
多連型、抵抗素子体とコイルまたはインダクタ素子体と
を組合せた多連型、またはコンデンサ素子体とコイルま
たはインダクタ素子体とを組合せた多連型など適宜の素
子体を組合せたネットワークを構成する。
A multiple type in which only a plurality of resistor elements are formed in parallel, a multiple type in which a resistor element and a capacitor element are combined, a multiple type in which a resistor element and a capacitor element are combined, a resistor A network is formed by combining appropriate element bodies such as a multiple type combining an element body and a coil or an inductor element body, or a multiple type combining a capacitor element body and a coil or an inductor element body.

【0029】第3の工程は、図4に示すように前記各チ
ップ基体10の表面に前記表面膜状電極12を露出させてこ
の隣接する表面膜状電極12間の空間部14を含めてほぼ全
面に第1の保護膜15を形成する工程で、前記チップ基体
10の表面に前記表面膜状電極12を露出させてこの表面膜
状電極12と重ならないようにこの隣接する表面膜状電極
12間の空間部14を含めて前記電子素子体13を覆うように
ほぼ全面にホウ・ケイ酸鉛系ガラスをペースト化して印
刷した後に焼成した第1の保護膜15を形成する。なお、
前記チップ基板10の両端部には第1の保護膜15は形成し
ない。
In the third step, as shown in FIG. 4, the surface film-like electrodes 12 are exposed on the surface of each of the chip bases 10 and substantially including the space 14 between the adjacent surface film-like electrodes 12. In the step of forming the first protective film 15 on the entire surface, the chip base
The surface film electrode 12 is exposed on the surface of the surface film electrode 10 so as not to overlap the surface film electrode 12.
A first protective film 15 is formed by pasting and printing boro-lead silicate glass over almost the entire surface so as to cover the electronic element body 13 including the space 14 between the 12 and then firing. In addition,
The first protective film 15 is not formed on both ends of the chip substrate 10.

【0030】第4の工程は、前記各チップ基体10の各電
子素子体13をトリミングする工程で、図5に示すよう
に、前記電子素子体13には切削刃、サンドブラストまた
はレーザ光などにより切削または蒸発させて抵抗値、容
量などがトリミング調整されている。このとき、電子素
子体13は第1の保護膜15にて被覆されているため、レー
ザ光などによるトリミング時に熱損などの障害がなく、
確実にトリミング調整ができる。例えば、抵抗素子体の
場合には中央部に前記チップ基体10の表面が露出される
ように調整トリミング溝16にて抵抗値の調整を行う。
The fourth step is a step of trimming each of the electronic element bodies 13 of each of the chip bases 10, and as shown in FIG. 5, the electronic element bodies 13 are cut with a cutting blade, sand blast or laser light. Alternatively, the resistance value and the capacity are trimmed by evaporation. At this time, since the electronic element body 13 is covered with the first protective film 15, there is no obstacle such as heat loss at the time of trimming by a laser beam or the like.
Trimming adjustment can be performed reliably. For example, in the case of a resistance element body, the resistance value is adjusted in the adjustment trimming groove 16 so that the surface of the chip base 10 is exposed at the center.

【0031】第5の工程は、前記各チップ基体の第1の
保護膜15の表面に第2の保護膜17を形成する工程で、こ
の電子素子体13がトリミング調整されたチップ基体10の
表面には、前記表面膜状電極12を露出させてこの表面膜
状電極12と重ならないようにこの隣接する表面膜状電極
12間の空間部14を含めて前記電子素子体13を覆うように
ほぼ全面にホウ・ケイ酸鉛系ガラスをペースト化して印
刷した後に焼成した第2の保護膜17を形成する。
The fifth step is a step of forming a second protective film 17 on the surface of the first protective film 15 of each of the chip substrates. The electronic element body 13 is trimmed and adjusted on the surface of the chip substrate 10. In order to expose the surface film-like electrode 12, the adjacent surface film-like electrode 12 is not overlapped with the surface film-like electrode 12.
A second protective film 17 is formed by pasting and printing boro-lead silicate glass over almost the entire surface so as to cover the electronic element body 13 including the space portion 14 between the layers 12, and then firing.

【0032】そして、前記隣接する表面膜状電極12間お
よび電子素子体13間の第1の保護膜15および/または第
2の保護膜17の厚みは表面膜状電極12若しくは端面膜状
電極19の厚みより薄いかまたは同一厚みで、表面膜状電
極12若しくは端面膜状電極19の表面より突出されないよ
うになっている。
The thickness of the first protective film 15 and / or the second protective film 17 between the adjacent surface film electrodes 12 and between the electronic element bodies 13 is determined by the surface film electrode 12 or the end surface film electrode 19. Is smaller than or equal to the thickness of the surface film-shaped electrode 12 or the end surface film-shaped electrode 19 so as not to protrude.

【0033】第6の工程は、前記絶縁性素板20を各チッ
プ基体10ごとに切断する工程で、図7に示すように、切
断溝21に沿って切断する。このとき、切断溝21に沿って
複数箇所に所定間隔ごとに互いに対向して形成した円状
の貫通孔22が切断溝に沿った切断を容易にし、この貫通
孔22は切断溝21に沿った切断によって形成されたチップ
基体10の両側縁に円弧状の凹部11となる。
The sixth step is a step of cutting the insulative base plate 20 for each chip base 10, and cutting along the cutting grooves 21 as shown in FIG. At this time, circular through-holes 22 formed opposite to each other at predetermined intervals at a plurality of locations along the cutting groove 21 facilitate cutting along the cutting groove, and the through-hole 22 extends along the cutting groove 21. Arc-shaped concave portions 11 are formed on both side edges of the chip base 10 formed by the cutting.

【0034】第7の工程は、前記チップ基体10の表面膜
状電極12、この表面膜状電極12に接続された端子膜状電
極19、およびこの端子膜状電極19に接続された裏面膜状
電極上に化学処理により電極メッキ層18を形成する。
In the seventh step, the surface film-like electrode 12 of the chip base 10, the terminal film-like electrode 19 connected to the surface film-like electrode 12, and the back film-like electrode connected to the terminal film-like electrode 19 are formed. An electrode plating layer 18 is formed on the electrode by a chemical treatment.

【0035】なお、チップ基体10の裏面にも、必要に応
じて、前記表面膜状電極12に接続された電子素子体を形
成してネットワーク回路を形成する。
On the back surface of the chip substrate 10, an electronic element connected to the surface film electrode 12 is formed as necessary to form a network circuit.

【0036】次に、この実施の形態の作用を説明する。Next, the operation of this embodiment will be described.

【0037】複数のチップ基体10を連接した絶縁性素板
20の表面に各チップ基体10の両側縁に沿って互いに対向
して複数対の表面膜状電極12を形成する工程に引き続
き、この各チップ基体10の各対をなす両側の表面膜状電
極12間に電子素子体13をそれぞれ形成する工程が行われ
た後、各チップ基体10の表面に表面膜状電極13を露出さ
せてこの隣接する表面膜状電極13間の空間部14を含めて
ほぼ全面に第1の保護膜15を形成する工程を有し、この
工程に次いで行われる各チップ基体10の各電子素子体13
をトリミングする工程において飛散した切削屑、蒸発物
質が隣接した表面膜状電極12間に飛散して第1の保護膜
15上に付着しても、さらに、この第1の保護膜15上に第
2の保護膜17を形成するため、この工程の後に行われる
チップ基体10の表面膜状電極12、端子膜状電極19および
裏面膜状電極上に電極メッキ層を形成する工程で隣接す
る表面膜状電極12間のブリッジ若しくは短絡が生じるな
どの不良品発生の原因となることがない。
An insulating base plate in which a plurality of chip bases 10 are connected.
Subsequent to the step of forming a plurality of pairs of surface film-like electrodes 12 facing each other along both side edges of each chip substrate 10 on the surface of 20, each pair of surface film-like electrodes 12 After the step of forming the electronic element bodies 13 in between, the surface film-shaped electrodes 13 are exposed on the surface of each chip substrate 10 and substantially include the space 14 between the adjacent surface film-shaped electrodes 13. A step of forming a first protective film 15 on the entire surface, and each electronic element body 13 of each chip base 10 performed after this step.
In the step of trimming the surface, the cutting debris and the evaporant scattered between the adjacent surface film electrodes 12 and the first protective film
Even if it adheres on the first protective film 15, a second protective film 17 is formed on the first protective film 15, so that the surface film electrode 12, the terminal film electrode In the step of forming the electrode plating layer on the film electrode 19 and the back film electrode, defective products such as a bridge or a short circuit between adjacent surface film electrodes 12 do not occur.

【0038】なお、前記実施の形態では、第1の保護膜
15はチップ基体10のほぼ全面に形成したが、少なくとも
電子素子体13を被覆しておればよい。
In the above embodiment, the first protective film is used.
Although 15 is formed on almost the entire surface of the chip base 10, at least the electronic element body 13 may be covered.

【0039】また、前記両実施の形態において、電子素
子体13がコイル素子体の場合、チップ基板10にメッキ、
印刷焼成、真空着膜などにより外周側をチップ基体10の
表面表面膜状電極12および/または端面膜状電極19に接
続された裏面膜状電極に接続して膜状のコイル素子体を
形成し、この膜状コイル素子体を第1の保護膜15で覆
い、この膜状のコイル素子体をレーザ光で螺旋状にスク
ライブし、この螺旋状の膜状のコイル素子体の中心部に
位置してチップ基体に貫通孔を形成し、この貫通孔に膜
状のコイル素子体の中心部に接続した導電膜を形成して
チップ基体10の裏面に形成した裏面膜状電極に接続す
る。
In both of the above embodiments, when the electronic element 13 is a coil element, the chip substrate 10 is plated,
The outer peripheral side is connected to the back surface film electrode 12 connected to the front surface film electrode 12 and / or the end film electrode 19 of the chip base 10 by printing and baking, vacuum deposition, etc. to form a film coil element body. The film-shaped coil element body is covered with a first protective film 15, and the film-shaped coil element body is spirally scribed with a laser beam, and is positioned at the center of the spiral film-shaped coil element body. Then, a through-hole is formed in the chip base, a conductive film connected to the center of the film-shaped coil element body is formed in the through-hole, and the through-hole is connected to the back film electrode formed on the back of the chip base 10.

【0040】なお、前記両実施の形態において、第1お
よび第2の保護膜15,17はエポキシ樹脂を塗布硬化させ
た保護膜とすることもできる。
In both of the above embodiments, the first and second protective films 15 and 17 may be formed by applying and curing an epoxy resin.

【0041】[0041]

【発明の効果】本発明によれば、チップ基体に形成した
電子素子体の調整により生じる切削屑、蒸発物質がチッ
プ基体の両側の電極間に付着してブリッジまたは短絡の
原因となることがなく、製造歩留まりが向上し、また、
膜状電極間距離が短縮することなく、信頼性を高めるこ
とができる。
According to the present invention, cutting chips and vaporized substances generated by adjusting the electronic element formed on the chip base do not adhere to the electrodes on both sides of the chip base to cause a bridge or a short circuit. , Increase the production yield,
The reliability can be improved without shortening the distance between the film electrodes.

【0042】また、各チップ基体の各電子素子体をトリ
ミングする工程において飛散した切削屑、蒸発物質が隣
接した表面膜状電極間に飛散してもこの表面膜状電極間
に第2の保護膜が形成されるので、この工程の後に行わ
れるチップ基体の表面膜状電極上に電極メッキ層を形成
する工程で、隣接する表面膜状電極間のブリッジまたは
短絡が生じるなどの不良品発生の原因となることがな
く、製造歩留まりを向上し、また、膜状電極間距離が短
縮することなく、信頼性が高い多連型チップ電子部品を
容易に製造できる。
Further, even if cutting chips and evaporated substances scattered in the step of trimming each electronic element body of each chip base scatter between adjacent surface film electrodes, a second protective film is formed between the surface film electrodes. Is formed, so that in the step of forming an electrode plating layer on the surface film-like electrode of the chip substrate performed after this step, a cause of defective product generation such as a bridge or a short circuit between adjacent surface film-like electrodes is generated. Thus, a multi-chip electronic component with high reliability can be easily manufactured without increasing the manufacturing yield and without reducing the distance between the film-shaped electrodes.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態を示す多連型チップ電子
部品の一部を切り欠いた平面図である。
FIG. 1 is a plan view, partially cut away, of a multiple chip electronic component showing an embodiment of the present invention.

【図2】本発明の一実施の形態を示す多連型チップ電子
部品の製造方法の膜状電極形成工程を示す絶縁性素板の
平面図である。
FIG. 2 is a plan view of an insulating base plate showing a film-like electrode forming step of the method of manufacturing a multiple chip electronic component according to one embodiment of the present invention.

【図3】同上多連型チップ電子部品の製造方法の電子素
子体形成工程を示す絶縁性素板の平面図である。
FIG. 3 is a plan view of the insulating base plate, showing an electronic element body forming step of the method for manufacturing a multiple chip electronic component according to the first embodiment.

【図4】同上多連型チップ電子部品の製造方法の第1の
保護膜形成工程を示す絶縁性素板の平面図である。
FIG. 4 is a plan view of the insulating base plate, showing a first protective film forming step of the method for manufacturing a multiple chip electronic component according to the first embodiment;

【図5】同上多連型チップ電子部品の製造方法のトリミ
ング工程を示す絶縁性素板の平面図である。
FIG. 5 is a plan view of the insulating base plate, showing a trimming step of the method for manufacturing a multiple chip electronic component according to the first embodiment;

【図6】同上多連型チップ電子部品の製造方法の第2の
保護膜形成工程を示す絶縁性素板の平面図である。
FIG. 6 is a plan view of the insulating base plate showing a second protective film forming step of the method for manufacturing a multiple chip electronic component according to the first embodiment.

【図7】同上多連型チップ電子部品の製造方法の切断工
程を示すチップ基体の平面図である。
FIG. 7 is a plan view of the chip base, showing a cutting step of the method for manufacturing a multiple chip electronic component according to the first embodiment;

【図8】従来の多連型チップ電子部品の一部を切り欠い
た平面図である。
FIG. 8 is a plan view of a conventional multiple chip electronic component with a part cut away.

【符号の説明】[Explanation of symbols]

10 チップ基体 12 表面膜状電極 13 電子素子体 14 空間部 15 第1の保護膜 17 第2の保護膜 18 電極メッキ層 19 端面膜状電極 20 絶縁性素板 22 貫通孔 10 Chip substrate 12 Surface film electrode 13 Electronic element body 14 Space 15 First protective film 17 Second protective film 18 Electrode plating layer 19 End film electrode 20 Insulating base plate 22 Through hole

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性のチップ基体と、このチップ基体
の表面に両側縁に沿って互いに対向して形成された複数
対の表面膜状電極と、この表面膜状電極に接続され前記
チップ基体の端面に形成された端面膜状電極と、この端
面膜状電極に接続され前記チップ基体の裏面に形成され
た裏面膜状電極と、前記チップ基体の各対をなす両側の
表面膜状電極間にそれぞれ形成された電子素子体と、前
記チップ基体の表面に前記膜状電極を露出させてこの隣
接する表面膜状電極間の空間部を含めてほぼ全面に形成
した保護膜と、前記チップ基体の表面膜状電極、端面膜
状電極および裏面膜状電極上に形成された電極メッキ層
とを備えたことを特徴とした多連型チップ電子部品。
1. An insulative chip base, a plurality of pairs of surface film electrodes formed on a surface of the chip base along both side edges to face each other, and the chip base connected to the surface film electrodes. Between the end surface film-shaped electrodes formed on the end surface of the chip substrate, the back surface film-shaped electrodes connected to the end surface film-shaped electrodes and formed on the back surface of the chip substrate, and the surface film electrodes on both sides of each pair of the chip substrate. An electronic element body respectively formed on the chip base; a protective film formed by exposing the film-shaped electrode on the surface of the chip base and forming a substantially entire surface including a space between adjacent surface film-shaped electrodes; A multi-chip electronic component comprising: a surface film electrode, an end surface film electrode, and an electrode plating layer formed on the back film electrode.
【請求項2】 複数のチップ基体を連接した絶縁性素板
の表面に前記各チップ基体の両側縁に沿って互いに対向
して複数対の表面膜状電極、各チップ基体の両側縁に貫
通した貫通孔の内周面に端面膜状電極および各チップ基
体の裏面に裏面膜状電極を形成する工程と、 この各チップ基体表面の前記各対をなす両側の表面膜状
電極間に電子素子体をそれぞれ形成する工程と、 前記各チップ基体の表面に少くとも前記電子素子体を被
覆するとともに、表面膜状電極を露出させて形成した第
1の保護膜を形成する工程と、 前記各チップ基体の各電子素子体をトリミングする工程
と、 前記各チップ基体の第1の保護膜の表面に第2の保護膜
を形成する工程と、 前記絶縁性素板を各チップ基体ごとに切断する工程と、 前記チップ基体の表面膜状電極、端面膜状電極および裏
面膜状電極上に電極メッキ層を形成する工程とを含むこ
とを特徴とする多連型チップ電子部品の製造方法。
2. A plurality of pairs of surface film-like electrodes, which penetrate both sides of each chip base, facing each other along both sides of the chip base on the surface of the insulating base plate in which a plurality of chip bases are connected. Forming an end surface film-like electrode on the inner peripheral surface of the through hole and a back surface film-like electrode on the back surface of each chip base; and an electronic element body between the pair of surface film-like electrodes on both sides of each pair of the chip base surface. Forming a first protective film formed by covering at least the electronic element body on the surface of each chip base and exposing a surface film-shaped electrode; and forming each chip base. Trimming each electronic element body, forming a second protective film on the surface of the first protective film of each chip substrate, and cutting the insulating base plate for each chip substrate. A surface film-shaped electrode of the chip substrate; Forming an electrode plating layer on the end surface film-shaped electrode and the back surface film-shaped electrode.
JP8157231A 1996-06-18 1996-06-18 Multiple chip electronic component and its manufacture Pending JPH1012421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8157231A JPH1012421A (en) 1996-06-18 1996-06-18 Multiple chip electronic component and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8157231A JPH1012421A (en) 1996-06-18 1996-06-18 Multiple chip electronic component and its manufacture

Publications (1)

Publication Number Publication Date
JPH1012421A true JPH1012421A (en) 1998-01-16

Family

ID=15645109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8157231A Pending JPH1012421A (en) 1996-06-18 1996-06-18 Multiple chip electronic component and its manufacture

Country Status (1)

Country Link
JP (1) JPH1012421A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6609009B1 (en) 1999-04-26 2003-08-19 Matsushita Electric Industrial Co., Ltd. Electronic component and radio terminal using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6609009B1 (en) 1999-04-26 2003-08-19 Matsushita Electric Industrial Co., Ltd. Electronic component and radio terminal using the same

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