JPH1013390A - Redundant transmission line switching device - Google Patents

Abstract

(57) [Problem] For example, a redundant transmission line switching device used for a device connected to an SDH network has an object to suppress data delay and reduce a circuit scale. A fixed-length data input from a transmission line is subjected to pre-processing such as clock loss detection, data length monitoring, parity check, unique path signal monitoring, monitoring data detection, and overhead data detection. System pre-processing means, 0 system in which normal data is written / read,
It has a 1-system memory means, and performs a phase comparison of the data read from the 0-system and 1-system memory means to detect coincidence. When a coincidence is detected, the above-mentioned pre-processing can be performed in parallel in a redundant transmission line switching apparatus that performs non-instantaneous switching between system 0 data and system 1 data and then inserts and outputs monitoring data and the like. At the same time, only data for which all the processing results are determined to be valid are written to the memory means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION In recent years, various services and media communications have been widely used in various fields such as social life and industrial activities, so that data has become faster, devices have been made smaller, and power consumption has been reduced. Demands for improved reliability are increasing.

For example, SDH (Synchronous Digital Hier
It is necessary to respond to the above demands in duplex devices connected to an archy (synchronous digital hierarchy) network, duplex switching of network interface devices, and the like.

[0003]

2. Description of the Related Art FIG. 66 is a diagram showing a configuration of a main part of a conventional example, and FIG.
It is a flowchart of FIG. Hereinafter, a description will be given of a conventional example. However, since the operations of the 0 system and the 1 system are the same, only the 0 system will be mainly described.

The data, enable bits, and parity bits input to the 0-system and 1-system redundant transmission line switching device shown in FIG. 66 are duplicated to improve data reliability. The system is switched according to the failure,
When switching systems, it is necessary to change the data phases and clocks of system 0 and system 1, so the memory (FI
FO) 31 is used to absorb the phase difference between the two systems and perform clock transfer.

[0005] Here, the duplex transmission line switching device uses a clock (C) for detecting the disconnection of the clock (hereinafter abbreviated as CLK).
LK) disconnection detection unit 101, a data length monitoring unit 102 that monitors the data length of fixed-length data, a parity check unit 103 that performs a parity check on data, a unique path filter unit 104 that performs filtering of a unique path signal, and a unique path. Eigenpath cycle monitoring unit 105 for monitoring a signal cycle; monitoring data detection unit 106 for detecting monitoring data; OH data detection unit for detecting overhead (hereinafter abbreviated as OH) data
107, a parity adding unit 111 for adding a parity to normal data by using the preprocessing result, and the like are connected in series to a writing side of a memory unit (hereinafter, referred to as FIFO) 31.

On the other hand, a parity check unit 201a for performing a parity check of data read from the FIFO is provided on the FIFO read side, and invalid data is used to confirm that switching between the 0-system and the 1-system operates normally. A check pattern insertion unit 202 that inserts a pseudo pattern into the data and a parity addition unit 210a that adds parity to input data are connected in series, and a match detection / match protection unit 204 that detects phase match and protects phase match. Is connected to the input side.

The other input side of the match detection / match protection section 204 is connected to a series of pre-processing means connected in series as shown in FIG. The output side of the match detection / match protection unit 204 should output a parity check unit 201b that performs a parity check of input data via a switching control unit 205 that performs system switching and the like and a selector monitoring unit 206. Parts 208 and 209 for inserting monitoring data and OH data into data, and a parity adding part for adding parity
It is connected to a data output unit consisting of 210b.

FIG. 67 is a flow chart showing the above processing in the form of a processing flow. That is, whether or not there is a clock input, whether or not the data length is normal, whether or not the result of the parity check is normal, whether or not the specific path filter has extracted the desired path signal, and whether or not the cycle of the extracted path signal is normal Checking whether or not monitoring data could be detected and whether or not OH data could be detected were sequentially and serially checked, and if normal data, that is, valid data, parity was added to the FI.
Write to FO (see S1 to S7). If not, the data is determined to be invalid data.

A parity check is performed by reading from the FIFO, a check pattern is inserted for invalid data, and parity is added to this pattern to add
Send to match protection unit. Since data read from the FIFO of the other system and subjected to the same processing as above is also added here, it is detected whether or not the phases match, and if they match, the data is transferred to the other system. Switch, do not switch if they do not match.

The data output from the coincidence detector / coincidence protector is inserted with monitoring data and OH data, and transmitted with added parity (see S8 to S17).

[0011]

In order to perform duplex switching of a transmission line, first, a duplicated transmission line (0 system / 1
In order to match the phase of (system), the system switches to the common clock for both system 0 and system 1 and then compares the phases. After the phases match, switching is performed according to the switching request.

Further, in order to monitor the validity of data input from the transmission line, input clock disconnection detection, input data length monitoring, unique path monitoring, parity check, OH data detection, monitoring data detection, and the like are performed.

For monitoring the internal operation, a clock transfer
Monitors the FIFO and monitors the selector. Conventionally, these monitoring functions are processed in series, and the data delay is large,
Along with that, the circuit scale and power consumption were also large. Also,
Even if abnormalities are detected by detecting OH data and monitoring data,
There is a drawback that the data is transferred in an abnormal state, and there is a problem that the monitoring function is strengthened to improve reliability.

An object of the present invention is to suppress data delay and reduce the circuit scale.

[0015]

A first aspect of the present invention is to detect input clock cutoff for monitoring the validity of input data, monitor the data length of input data, monitor a unique path, check the parity of input data, and check OH. Pre-processing for writing to FIFO, such as data monitoring and monitoring data monitoring, is now performed in parallel. In the "second aspect of the present invention", only the valid data is the data for which the clock transfer is performed, and the clock transfer is not performed for the invalid data and the data determined to be abnormal based on the monitoring result. In other words, data that is determined to be invalid in the monitoring
Do not write to FO.

However, if the data to be written to the FIFO is kept waiting until the monitoring is completed, the data delay increases. Therefore, (1) Writing to the FIFO is started at the same time as monitoring the data, and if the data is valid, the writing is completed as it is. If the monitoring result indicates that the writing is invalid, a write completion notification is not issued and the data is discarded. It was made to be. The method of discarding data is as follows: (2) The data storage area of the clock transfer FIFO is divided into addresses in data units to form a surface configuration.

When writing data to the FIFO, the second
As in item (1) of the present invention, the data is monitored and the writing to the FIFO is started at the same time. However, if the monitoring result indicates that the data is invalid, the surface switching is not performed.

Then, the invalid data is discarded by overwriting the next received valid data with the invalid data. This method eliminates the need to wait for data when writing data to the FIFO, thereby reducing data delay. (3) When controlling the clock transfer FIFO, writing starts regardless of whether the received data is valid or invalid. At the same time, the received data is monitored, and the monitoring result is assigned to the last bit of the additional data.

Then, by controlling the writing to the FIFO, the monitoring result is reflected on the writing end flag, and it is determined whether or not the writing is completed. As a result, whether to write data to the FIFO is determined by the last bit of the data, so that it is not necessary to make the data wait, thereby improving the throughput, reducing the circuit scale, and reducing the power consumption. (4) When the clock transfer FIFO is controlled as a plane configuration, writing starts regardless of whether the received data is valid or invalid.

At the same time, the received data is monitored, and the monitoring result is assigned to the last bit of the additional data. And FIFO
In the write control, the monitoring result is used as a surface switching condition. If the monitoring result is normal, the surface is switched. If the monitoring result is abnormal, the surface is not switched, and the next received normal data is overwritten.

As a result, since whether to write data to the FIFO is determined at the end of the data, it is not necessary to make the data wait, thereby improving the throughput, reducing the circuit scale, and reducing the power consumption. In the "third present invention", OH data indicating the head of a data group included on a transmission path is also subjected to duplex switching. When paths are multiplexed, OH data continues for the number of multiplexed paths. When performing duplex switching of the transmission line, the reliability and reliability are improved by monitoring the cycle and continuity of the OH data.

Conventionally, a counter for monitoring a period,
An independent counter for monitoring continuity was provided. In the present invention, the circuit size and the power consumption can be reduced by sharing the counter for monitoring the period and the counter for monitoring the continuity. In the "fourth invention", when separating multiplexed data for four paths, filtering is performed for each path and data of only the own path is taken in. At this time, the data other than the own path becomes invalid data, and thus the valid data is one out of four data. Also, as for the unique path signal included in the header part of the data, the signal of the same path becomes one of the four data.

Conventionally, in order to monitor the period of the eigenpath signal, monitoring is performed using only the eigenpath signal. In the present invention, the reliability of the path cycle detection is improved by comparing the cycle of the eigenpath signal with the cycle of the valid data. The "fifth invention" monitors OH data with continuity and cycle. Since the OH data is also a target of the duplex switching, the clock transfer is performed by the FIFO.

Conventionally, when the OH data is determined to be abnormal, a clock change is performed, so that the abnormal state is transferred as it is. In the present invention, (1) Only the first OH data of the continuous OH data is written to the FIFO. At the same time, monitor the continuity and cycle of OH data
The data monitoring result is notified to the FIFO reading side.

On the reading side, if the monitoring result is normal, OH
The continuity is realized by reading the data and copying the read OH data for four data. In addition, when the normal OH data is read, a cycle of the OH data is generated, and when the abnormal OH data is received, the OH data is transferred at a cycle generated by the normal OH data.

According to this method, the reliability is improved because the OH data is not transferred in an abnormal state, and only the first OH data of the continuous OH data is clock-switched by the FIFO, so that the circuit scale can be reduced. Power consumption can be reduced. (2) When transferring OH data, only the first OH data of the continuous OH data is written to the FIFO in the same manner as in the fifth aspect of the present invention (1). On the reading side, continuity is realized by reading the OH data four times consecutively.

The cycle of the OH data is the same as the effective OH
By generating the data in advance, it is possible to prevent the transfer of the abnormal cycle. According to the "sixth aspect of the present invention", when OH data is transferred, the OH data is not written into the FIFO, but the OH data is detected and notified to the FIFO reading side in the manner of flag transfer.

On the FIFO reading side, OH data is inserted and transferred based on the received flag. In this way,
Since OH data is not written / read by the FIFO, power consumption can be reduced. "Seventh invention" is as follows: (1) When transferring OH data, the OH data itself is FIFO
OH data is detected and the detection bit is set and assigned to additional data.

Then, the additional data is clock-switched by the FIFO, and when a detection bit is detected on the read side, OH data is inserted into the data read from the FIFO and transferred. According to this method, since the OH data is clock-switched using only the detection bit, power consumption can be reduced. (2) When transferring monitoring data for monitoring transmission equipment,
The monitoring data itself is not written in the FIFO, and when monitoring data is detected, a detection bit is set and assigned to additional data.

Then, the additional data is clock-switched by the FIFO, and when the detection bit is detected on the read side, the monitoring data is inserted into the data read from the FIFO and transferred. According to this method, the monitoring data is clock-switched using only the detection bit, so that power consumption can be reduced. "Eighth
According to the present invention, when monitoring monitoring data, monitoring and transfer are performed independently.

First, monitoring is performed based on whether monitoring data can be detected within a monitoring period indicated by a timing signal at a stage preceding the FIFO. The detected monitoring data is invalidated and is not written to the FIFO. Further, the rise of the timing signal indicating the monitoring period is differentiated and assigned to additional data. Then, the clock change of the additional data is performed by the FIFO.

Next, the monitoring data is transferred by detecting a timing signal in the additional data, inserting the monitoring data into the first invalid data position after the detection, and transferring the monitoring data. In this way,
Since the monitoring data itself is not written and transferred to the FIFO, power consumption can be reduced.

Further, since the transfer is performed using a reference timing signal as a trigger, even if the received monitoring data is abnormal, the data is not transferred as it is, but is transferred to a correct position and transferred, thereby improving reliability. . The ninth invention is as follows: (1) When writing data to a FIFO, a serial number is added as position information for each data, and the serial number is assigned to additional data.

Then, clock switching is performed on the additional data in the same manner as the data, and the reading side of the FIFO reads the serial number.
Check the FIFO reading order. At the same time, phase comparison is performed by comparing the serial numbers of the 0 system and 1 system.

Thus, reliability is improved by comparing the read order of the FIFO and the phase. The following method is also available as a phase comparison method. (2) When performing duplex switching of the transmission path, the circuit scale becomes large when all the data of the 0 system and 1 system are compared and the phases are compared.

Therefore, phase comparison is performed using the unique path signal assigned to the header portion of the data as position information.
The eigenpath signal is a signal assigned to each path, and after being multiplexed, the same eigenpath signal does not continue. Therefore, it is possible to monitor the phase only with the eigenpath signal.

As a result, instead of comparing all data as in the related art, it is possible to perform a phase comparison on a part of the data. (3) The phase comparison between the 0 system and the 1 system when performing the duplex switching is performed by counting the number of "1" in the data of each system and comparing the count values. The unit for comparison is one data length unit.

According to this method, the phase comparison can be performed more easily than the conventional all-bit comparison, so that the circuit scale can be reduced. (4) The phase comparison between system 0 and system 1 when performing duplex switching
A vertical parity is added to the data of each system, and the parity
This is done by comparing the bits.

According to this method, the phase comparison requires only parity bits, so that the circuit scale is reduced. (5) The phase comparison between the 0 system and the 1 system at the time of performing the duplex switching is performed by using both the items (3) and (4) of the ninth invention. That is, the comparison is performed by comparing the number of "1" of the data of each system with the vertical parity bit. Accordingly, it is possible to cope with a case where data, which is a weak point of the parity, is inverted even number bits.

With this method, the circuit scale can be reduced and the reliability can be improved. (6) The data consists of a header area containing various control signals and a payload for transferring information such as audio and images. The header may be replaced when various controls are performed, but the payload is transferred transparently.

Therefore, in each system, a CRC code is added to the payload of the input data as phase information, and after the clock transfer and the duplexing are switched, the CRC code is checked.

That is, the transparency of the payload is checked by generating / checking the CRC code at both ends of the functional block. In addition, since it is a CRC code, error correction is possible, and reliability is improved. The "tenth present invention" is as follows: (1) When writing data to a FIFO, a serial number is added as position information for each data, and the serial number is assigned to additional data.

Further, a parity is added to the data and the additional data as error detection information. Then, clock switching is performed for the additional data and the parity in the same manner as the data.
On the FIFO reading side, the FIFO reading order is checked by the parity check and the serial number. At this time, the serial number is cross-checked in the manner of crossing system 0 / system 1.

That is, the system 1 is checked with the serial number of the system 0, and the system 0 is checked with the serial number of the system 1.
By comparing the phase of the 0 system / 1 system with this method,
At the same time, the write / read of the FIFO is checked, and the reliability is improved.

The following method is also available as a phase comparison method. (2) A CRC code is used as position information as a phase comparison method between system 0 and system 1 when performing duplex switching.

In each system, a CRC code is added before the FIFO, the CRC code is allocated to additional data, and clock transfer is performed by the FIFO. Then, the CRC code is checked at the latter stage of the FIFO. At this time, the crossing is performed between the 0 system and the 1 system in a crossing manner.

That is, the system 1 data is checked by the system 0 CRC code, and the system 0 data is checked by the system 1 CRC code. By comparing the phases of the 0-system and the 1-system with this method, the write / read of the FIFO is checked at the same time, and the reliability is improved. (3) Parity is used as a phase comparison method between system 0 and system 1 when performing duplex switching. In each system, parity is added at the stage preceding the FIFO, and clock transfer is performed in the same manner as data.

Then, the parity check is performed at the subsequent stage of the FIFO. At this time, the 0 system / 1 system is crossed in a crossing manner. That is, the system 1 data is checked by the 0 system parity bit, and the system 0 data is checked by the 1 system parity bit.

Thus, by comparing the phases of the 0 system and the 1 system, the write / read of the FIFO is checked at the same time, and the reliability is improved. (4) BIP2 is used as a phase comparison method between system 0 and system 1 when performing duplex switching. BIP2 is Bit Interleaved Parity 2 (Bit Interleaved Party 2)
Is shown.

In each of the systems, BIP2 is added at the preceding stage of the FIFO, and clock transfer is performed in the same manner as data. And after the FIFO
The BIP2 is checked, but at that time, the 0 system / 1 system is crossed in a crossing manner. That is, 1 in BIP2 of 0 system
Check the system and check the 0 system with BIP2 of 1 system.

Thus, by comparing the phases of the 0 system and the 1 system, the write / read of the FIFO is checked at the same time, and the reliability is improved. In the "eleventh invention", when the clock transfer FIFO is configured as a plane, the conventional read control includes a plane counter for counting planes and a read address for counting bits in data.
It is performed by a counter, and provided separately for the 0 system / 1 system.

In the present invention, the read address counter is shared by the 0 system / 1 system, and the plane counter is separately provided by the 0 system / 1 system. This is because data is discarded on the transmission path or in each monitoring function, and the validity / invalidity of the data may not match between the 0 system and the 1 system. On the other hand, since the bits cannot be shifted between the 0 system and the 1 system, they are shared.

That is, by sharing the read address counter, the phase shift of the 0 system / 1 system can be prevented, the reliability is improved, and the circuit scale can be reduced. "Twelfth invention" is as follows: (1) When the clock transfer FIFO has a plane configuration,
The writing side causes the surface counter to count regardless of valid / invalid data.

However, in the case of invalid data, only the surface counter is counted up, and the data itself is not written in the FIFO. The validity / invalidity of data is notified from the writing side to the reading side by providing a flag.

Next, the read side shares both the surface counter and the read address counter. The surface counter counts up regardless of valid / invalid data. However, in the case of invalid data, only the surface counter is counted up and no reading is performed.

Thus, the 0 system / 1 system is identified not by the address but by the read enable (RE). Further, the read address counter can be shared because the bits cannot be shifted between the 0 system and the 1 system.

Thus, by sharing the plane counter and the read address counter, it is possible to prevent the phase shift between the 0 system and the 1 system, thereby improving the reliability and reducing the circuit scale. (2) Conventionally, as a method of monitoring a FIFO, parity is added to data to be written, and a check is performed on the read side.

The term (2) of the twelfth invention is the same as that of the twelfth invention.
In the case of the configuration of the item (1), since the 0-system / 1-system controls the FIFO with the common read address, the parity is added to the data and the address and the data and the address are written to the FIFO.

On the reading side, after performing the duplex switching,
Perform parity check. According to this method, it is not necessary to separately provide a parity check circuit for the 0 system / 1 system unlike the related art, so that the circuit scale can be reduced.

Further, since the address is monitored by the parity, the reliability is improved. The thirteenth invention is as follows: (1) Data enable (EN) and the start address of the surface to be written next are assigned to additional data, and the data is written irrespective of valid / invalid data.

However, at the time of invalid data, only the data enable and the head address are written. Reading side is also valid /
Read regardless of invalid. At the time of invalid data, only the data enable and the start address are read.

Then, the read address is generated by loading the read counter with the head address for each data. According to this method, it is not necessary to transfer the write end flag between the write side and the read side of the FIFO unlike the related art, so that the circuit scale can be reduced. (2) When performing duplex switching, read the first three bits in both systems.

A data enable (1 bit) and a head address, that is, surface information (2 bits) are assigned to these 3 bits. Then, phase comparison is performed by comparing these three bits in the 0 system / 1 system, and the comparison result is used as a condition for instantaneous interruption / non-instantaneous interruption switching of duplex switching.

As a result, the phase comparison can be performed more easily than in the prior art, so that the circuit scale can be reduced. (3) In the case of performing the duplex switching in the item (2) of the thirteenth aspect of the present invention, both systems read the first bit. A data enable and a head address are assigned to the one bit. Since the start address is a fixed value, prediction is possible.

Therefore, the predicted address is compared with the head address read from the FIFO, and the result of the comparison is used as a condition for the instantaneous interruption / non-instantaneous interruption switching of duplex switching. By performing duplex switching in this manner, the circuit scale can be reduced. (4) As shown in paragraphs (1) and (2) of the thirteenth invention, when data clock transfer is performed without flag control, 3-bit data is written to / read from the FIFO when invalid data is present. There is a need to.

This is because, for the additional data of the serial data,
This is because it is necessary to transfer a total of 3 bits of 2 bits of the data enable and the plane information. According to the present invention, 1-bit delivery is performed by writing surface information to a main signal that is not used at the time of invalid data. That is, at the time of invalid data, one bit can be passed by assigning the data enable to the head of the additional data and the two bits of the surface information to the head of the main signal.

This eliminates the need for flag control when changing clocks, so that the circuit scale can be reduced.
At the time of invalid data, only one bit needs to be transferred, so that power consumption can be reduced. "The fourteenth invention" is defined as follows: (1) As shown in the items (1) and (2) of the thirteenth invention, when data clock transfer is performed without flag control, 3 It is necessary to write / read bit data to / from the FIFO.

This is because, for the additional data of the serial data,
This is because it is necessary to transfer a total of three bits, one bit of data enable and two bits of surface information. In the present invention, FIFOs are separately provided for the main signal and the additional data.

On the write side, both the main signal and the additional data are written at the same address, and on the read side, the additional data is read out first, and then the main signal is read out. That is, the additional data is pre-read by one data from the main signal.

According to this method, it is possible to determine in advance whether the next main signal to be read is valid data or invalid data based on the additional data. Therefore, if the main signal to be read next is invalid data, no bit is read.

As a result, the flag control is not required at the time of clock transfer, so that the circuit scale can be reduced. In addition, at the time of invalid data, it is not necessary to access even one bit of the FIFO, so that the power consumption can be reduced. (2) Conventionally, control of the clock transfer FIFO has been performed by flag control. In this method, when the FIFO has a surface configuration, as the number of surfaces increases, the circuit scale of flag control increases in proportion to the number of surfaces.

In the present invention, the write / read of the FIFO is controlled by the adder. The write side generates a write address by the data enable of the input data, and starts writing. Then, the final address of the FIFO surface is decoded and +1 is added to the adder. If the output of the adder is 1 or more, the read side starts reading, decodes the last address on the read address side, and adds -1 to the adder.

That is, when writing is completed, +1 is added to the adder.
When reading is completed, -1 is added to the adder. If the output of the adder is +1 or more, it indicates that data is stored in the FIFO, so that reading is continued. Since this method does not use a flag for clock transfer control, the circuit scale can be reduced.

[0074]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
FIG. 2 is a basic configuration diagram of a FIFO control unit, FIG. 3 is a configuration diagram of main parts of the first embodiment of the present invention, FIG. 4 is a time chart of FIG.
FIG. 6 is a configuration diagram of a main part of the second embodiment of the present invention (part 1), FIG.
FIG. 7 is a time chart of FIG. 5, FIG. 7 is a main part configuration diagram (part 2) of the second embodiment of the present invention, and FIG. 8 is a time chart of FIG.

FIG. 9 is a block diagram showing a main part of the second embodiment of the present invention.
(Part 3), FIG. 10 is the time chart of FIG. 9, and FIG.
FIG. 12 is a main part configuration diagram of an embodiment of the present invention (part 4), and FIG.
13 is a main part configuration diagram of the third embodiment of the present invention, and FIG. 14 is a time chart of FIG.

FIG. 15 is a diagram showing a main part of a fourth embodiment of the present invention, FIG. 16 is a time chart of FIG. 15, and FIG. 17 is a diagram showing a main part (part 1) of a fifth embodiment of the present invention. 18 is a time chart of FIG. 17, FIG. 19 is a main part configuration diagram (part 2) of the fifth embodiment of the present invention, FIG. 20 is a time chart of FIG. 19, and FIG.
FIG. 22 is a time chart of FIG. 21.

FIG. 23 is a block diagram (part 1) of a main part of a seventh embodiment of the present invention, FIG. 24 is a time chart of FIG. 23, and FIG.
FIG. 26 is a main part configuration diagram of an embodiment of the present invention (part 2), and FIG.
27 is a main part configuration diagram of the eighth embodiment of the present invention, 28 is a time chart of FIG. 27, FIG. 29 is a main part configuration diagram (part 1) of the ninth embodiment of the present invention, FIG. 30 is a time chart of FIG.

FIG. 31 is a view showing a main part (part 2) of the ninth embodiment of the present invention, FIG. 32 is a view showing a main part (part 3) of the embodiment of the present invention in FIG. 9, and FIG. FIG. 34 is the ninth time chart.
FIG. 35 is a main part configuration diagram of an embodiment of the present invention (part 4), and FIG.
36 is a main part configuration diagram (part 5) of the ninth embodiment of the present invention, and FIG. 37 is a time chart of FIG.

FIG. 38 is a block diagram (part 6) of a ninth embodiment of the present invention, FIG. 39 is a time chart of FIG. 38, and FIG.
FIG. 41 is a configuration diagram of a main part (part 7) of the embodiment of the present invention, and FIG.
42 is a main part configuration diagram (part 1) of the tenth embodiment of the present invention, FIG. 43 is a time chart of FIG. 42, and FIG.
FIG. 45 is a main part configuration diagram (part 2) of the tenth embodiment of the present invention;
44 is a time chart of FIG. 46 is a main part configuration diagram (part 3) of the tenth embodiment of the present invention, FIG. 47 is a time chart of FIG. 46, and FIG. 48 is a main part configuration diagram of the tenth embodiment of the present invention (
Part 4), FIG. 49 is a time chart of FIG. 48, FIG. 50 is a block diagram of an essential part of an eleventh embodiment of the present invention, FIG. 51 is a time chart of FIG. 50, and FIG. FIG. 53 is a time chart of FIG. 52.

FIG. 54 is a block diagram showing a main part of a twelfth embodiment of the present invention.
(Part 2), FIG. 55 is the time chart of FIG. 54, and FIG.
FIG. 57 is a main part configuration diagram of the embodiment of the present invention (No. 1), and FIG.
FIG. 58 is a main part configuration diagram of the thirteenth embodiment of the present invention (part 2), FIG. 59 is a time chart of FIG. 58, and FIG.
FIG. 61 is a configuration diagram of a main part of the thirteenth embodiment of the present invention (part 3);
61 is a time chart of FIG.

FIG. 62 is a block diagram showing a main part of a fourteenth embodiment of the present invention.
(Part 1), FIG. 63 is the time chart of FIG. 62, and FIG.
FIG. 64 is a diagram showing a main part of an embodiment of the present invention (part 2), and FIG.
It is a time chart.

The same reference numerals denote the same objects throughout the drawings. Further, the reference numerals on the left side of the time chart indicate the operations of the same reference numerals in the corresponding main configuration diagrams. Hereinafter, FIG. 1 to FIG.
The operation of the present invention will be described with reference to 65, but the parts that have been described in detail in the conventional example will be briefly described, and the parts of the present invention will be described in detail. Since the operations of the 0 system and the 1 system are the same, the description will be mainly given of the 0 system.

First, an overall block diagram of the present invention will be described with reference to FIG. As shown in Fig. 1, the input data is duplicated to improve the reliability of the data. In order to switch the system, it is necessary to change the data phases and clocks of the 0 system and 1 system. , Using a memory (FIFO) to perform phase absorption and clock transfer for both systems.

The input data is supplied to a CLK disconnection detection unit 101, a data length monitoring unit 102, a parity check unit 103, a unique path filter unit 104, a unique path cycle monitoring unit 105, a monitoring data detection unit 106, and an OH data detection unit 107. Be monitored. The portion from the CLK disconnection detecting section 101 to the OH data detecting section 107 is called a preprocessing section.

The data that has passed all of the preprocessing sections is added as parity by the parity adding section 111 as valid data, and is written into the FIFO 31 by the FIFO control section 4. Then, data is read from the FIFO 31 at the timing of a system frame pulse (SYS FP) not shown.

The data read from the FIFO 31 is monitored by the parity check unit 201a. In addition, a check pattern insertion unit that uses invalid data to check whether or not the selector has operated normally during data switching.
02, a parity adding unit 210a for adding a parity to the data read from the FIFO, a match detection / match protection unit 204 for matching and monitoring the phases of the 0-system data and the 1-system data, and a switching control unit for switching the data 205, selector monitoring unit that checks the output from the check pattern insertion unit 202
206, a parity check unit 201b that performs a parity check on the selected data,
OH that inserts data and monitoring data and adds parity
It comprises a data insertion unit 208, a monitoring data insertion unit 209, and a parity addition unit 210b.

Next, the basic configuration of the FIFO control unit will be described with reference to FIG. The write control unit 41 includes a write address generation unit 414, a start address generation unit 411, a surface counter 412 on the write side, and a write enable (EN) generation unit 413, and only when the input data enable (EN) is valid, The write address generation unit 414, the surface counter 412, and the start address generation unit 411 enter an operable state.

The surface counter 412, for example, allocates surfaces when the FIFO has a three-surface configuration, and generates three surface information here. The start address generation unit 411 includes the surface counter 41
2 indicates the head address of the surface information, which is the initial value of the counter of the write address generation unit 414.

The write address generator 414 generates a write address for the FIFO 31 using the surface information and the head address of the surface information. The flag control 42 includes flag generation, flag control, and a flag CLR (clear) / generation unit 423.

The flag generation unit 421 generates a write information flag for the FIFO, and the flag CLR / generation unit 423 generates a read information flag from the FIFO and writes the write information flag to the CLR.
To generate a signal. The flag control section 422 controls the flag generation section 421 and the flag CLR / generation section 423.

The read control unit 43 includes a read address generation unit
434, a read start address generation unit 431, a surface counter 432 on the read side, and a read enable (EN) generation unit 433.

The read enable (EN) generation unit 433 generates an enable (EN) of the surface read from the FIFO 31 based on the signal from the flag CLR / generation unit 423. Surface counter
432 generates surface information for reading the allocated FIFO surface in the same manner as the surface counter 412 of the write control unit 41, and the read head address generation unit 431 indicates the head address of the surface information and generates the read address. The initial value of the counter of the section 434 is obtained.

The read address generation unit 434 generates the surface information, the head address of the surface information, and the system frame pulse (
A read address is generated using a signal from the master timing generator 44 based on SYSFP).

Here, the signal flow of FIG. 2 will be described. That is, when data is input, the write address generator 414 starts operating. The plane counter 412 has three FIFO memory areas.
Since it is divided, for example, 0 is output from the divided surface information 0, 1, and 2. Start address generation unit 411
Generates the head address of the transmitted surface information and sends it to the write address generation unit 414.

Thus, when the data FP (frame pulse) is input, the write address generation unit 414 fetches the head address, starts the counting operation, and sends it out to the FIFO 31 as the write address (WA). Write data to the specified address.

Note that the write address generation unit 414 decodes the count value when, for example, about 3 bytes of data have been written into the FIFO, and sends the count value to the flag generation unit 421 with the decoded output as a trigger.

The flag generation unit 421 latches the trigger to operate the flag control unit 422, and outputs the flag from the flag CLR / generation unit 423 by the output of the flag control unit 422. Therefore, the read enable generation unit 433 sets the read enable (R
E), and the read address generator 434 outputs the read address to the FIFO 31, so that data is read from the FIFO. When reading is completed, the read address generation unit 43
4 sends the end of reading to the flag CLR / generation unit 423, so the flag CLR / generation unit 423 resets the flag control unit 422.

Thus, the flag CLR / generation unit 423 is reset by the output of the flag control unit 422, and the reading is stopped. Therefore, the flag CLR / generation unit 423
Reset.

When the data FP is applied again, the read address generator 434 starts the operation and outputs the plane information 1 as described above. Hereinafter, the above operation is repeated. "Explanation of the First Embodiment of the Present Invention" See FIGS. 3 and 4. When performing duplex switching of a transmission line, a common clock (eg, system clock) is used to match the phases of both systems before switching. It is necessary to transfer to.

This processing is indispensable for performing instantaneous interruption switching. The means for realizing the clock transfer uses a FIFO. Only the valid data is used for clock transfer, and invalid data is discarded. Further, in order to monitor normal reception of valid data, clock disconnection detection, data length monitoring, unique path monitoring, parity check, and the like are performed.

Only the data determined to be normal are FI
The data is written to the FO and the clock is changed. However, it takes time to determine that the data is normal, and it is necessary to make the data wait for that time. The data determined to be abnormal is discarded as invalid data.

Conventionally, as described above, data monitoring is performed serially in the order of clock loss detection, data length monitoring, parity check, and unique path monitoring. For this reason, it is necessary to wait time data for the total time required for each process.

In the present invention, the clock loss detection unit 101, the data length monitoring unit 102, the parity check unit 103, and the unique path monitoring unit 105 perform predetermined processing on input data in parallel, and enable control of the processing result. Add to part 108.

In addition to the above processing results, a data enable and a fixed-length data frame pulse (FP) are applied to the enable control unit 108. When it is determined that all of them are valid, for example, "1" The determination result is sent to the writing control unit 41. Thus, under the control of the write control unit 41, the data determined to be normal is written to the FIFO 31.

The FIFO 31 is controlled by the write controller 41, the flag controller 42, and the read controller 43, as described above.
Further, by performing the parallel processing, it is only necessary to make the data wait according to the processing that takes the longest time. For example, in the case of FIG. 4, the determination result of the data length monitoring takes the longest first, so it is necessary to delay the input data until the determination result of the data length monitoring. "Explanation of Second Embodiment of the Present Invention (Part 1)" FIGS. 5 and 6
Reference In the same way as in the first embodiment of the present invention, when performing clock transfer, reading from the FIFO is performed at the time when writing is completed for one data length. The FIFO (not shown) is controlled by the write end flag.

That is, when the memory area of the FIFO is divided for each data length to have a capacity of 3 data lengths and a three-plane configuration,
The write address generator 414 generates a write address of the FIFO 31 and writes the FIFO and the write end flag / trigger generator 41.
Send to 5.

The write end flag / trigger generation unit 415
By decoding the last address of each face of the input write address, a write end flag / trigger indicating that writing for one data length is completed is generated and sent to the write end flag control unit 416.

The write end flag control unit 416 generates a write end flag using a write end flag trigger,
The fact that reading is possible is sent to the reading start address generation unit 431 on the reading side.

Upon detecting the write end flag, read head address generation section 431 generates a read head address and loads it into read address generation section 434. As a result, the read address generator 434 generates a read address.

The write end flag / clear generator 43
7 decodes the last address of each surface of the read address sent from the read address generation unit 434,
A write end flag / clear indicating that the reading for one data length has been completed is generated, and the write end flag control unit 41 is generated.
Clear the write end flag sent by 6. The FIFO read control is performed by this repetition.

That is, in the present invention, the writing to the FIFO is started regardless of the validity / invalidity of the data, and the data is monitored at the same time. If the result of the data monitoring is normal, the AND gate 230 is turned on. Therefore, a write end flag is set, and reading is performed as writing is completed.

However, if the result of the data monitoring is abnormal, the AND gate is turned off, and as shown in FIG. 6, the write end flag is not set, so that the read operation is not performed, and the data is overwritten by the next write data. The invalid data is discarded.

According to this method, it is not necessary to make the data wait when writing the FIFO, so that the throughput can be improved and the circuit size can be reduced. "Explanation of Second Embodiment of the Present Invention (Part 2)" FIGS. 7 and 8
The FIFO for clock transfer (not shown) has a capacity of three data lengths. The FIFO is divided into A, B, and C planes, and the capacity for one data length is assigned to each side, and a three-sided configuration is used. I do.
Incidentally, reference numeral 417 in the figure denotes a decoder.

Now, even if the effective data is continuous, by repeating the switching of the A-side writing, the A-side reading, the B-side writing, the B-side reading, the C-side writing, and the C-side reading, the switching is performed.
The FIFO performs clock transfer without overflow.

In the second description of the present invention (part 2), the writing to the FIFO is started regardless of the validity / invalidity of the data, and the data is monitored at the same time. If the result of the data monitoring is normal, the plane switching counter 410 switches the plane and starts writing the next received data. However, if the result of the data monitoring is abnormal, the counter enable from the final address decoding unit 418 is not sent to the plane switching counter 410 (see FIG. 8).

For this reason, the plane switching counter 410 stops the counting operation and does not perform the plane switching, but discards invalid data by writing the next received data on the same plane.
The operation of the write end flag / trigger generator 415 is also stopped because the counter enable is not added.

According to this method, it is not necessary to make data wait when writing data to the FIFO, so that an improvement in throughput, a reduction in circuit scale, and a reduction in power consumption can be realized. "Explanation of Second Embodiment of the Present Invention (Part 3)" FIGS. 9 and 10
Reference As described in the description of the second embodiment of the present invention (part 1),
A write end flag was used for reading control of the clock transfer FIFO.

In the description of the second embodiment of the present invention (part 3), the generation of the write end flag is performed by using the additional data.
Performs FIFO control. The FIFO 31 has a three-plane configuration as shown in the second embodiment of the present invention (No. 2).

The received data starts writing to the FIFO 31 irrespective of valid data / invalid data. At the same time, clock loss detection by clock loss detection unit 101, data length monitoring by data length monitoring unit 102, parity check by parity check unit 103, eigenpath monitoring unit 1
The monitoring result of the unique path monitoring by 05 and the valid / invalid data information (data enable) are ORed with the OR circuit 12.
The OR output obtained in 4 is ORed, and the OR output is multiplexed in the multiplexing section 118 to the last bit of the additional data.

Then, a write end flag is generated based on the last address of the write surface and the condition of the monitoring result allocated to the last bit of the additional data. The FIFO is controlled by a write control unit 41, a read control unit 43, and a flag control 42.

As a result, whether data is written to the FIFO is determined by the last byte of data, so that there is no need to wait for data as in the prior art, thereby improving throughput, reducing the circuit scale, and reducing power consumption. realizable. "Explanation of Second Embodiment of the Present Invention (Part 4)" FIGS. 11 and 12
Reference As shown in the second embodiment of the present invention (part 2),
In the case where clock switching is performed by performing surface switching as a three-surface configuration, this is performed by effectively utilizing the additional data described in the embodiment (part 4).

The input data starts writing to the FIFO irrespective of valid data / invalid data. At the same time, clock loss detection by the clock loss detection unit 101, data length monitoring by the data length monitoring unit 102, parity check by the parity check unit 103, and unique path monitoring by the unique path monitoring unit 105 were performed on the input data. The monitoring result and the information of valid data / invalid data are ORed by the OR circuit 124, and the OR output is multiplexed by the multiplexing unit 118 to the last bit of the additional data. The last bit is used to enable the plane switching counter 410.

Further, the final write address sent by the write address generation unit 414 is
The write end flag / trigger generator 415 generates a write end flag / trigger signal by using the final address / decoded output decoded and transmitted by the decoder and the decoded output obtained by decoding the output of the plane switching counter 410 by the decoder 417. It is sent to the write end flag control unit 416.

Therefore, the write end flag control section 416 performs the following write end flag control based on the trigger signal. That is, when the data is valid, the plane switching is performed and the data is written into the FIFO 31, and when the data is invalid, the invalid data is discarded by overwriting the data without performing the plane switching.

In response to the input of the write end flag, read start address generation section 431 generates the read start address and adds it to read address generation section 434. The read address generation section writes the read address to write end flag / clear generation section 437. To send a write end flag
The clear generation unit 437 clears the write end flag and completes reading.

Thus, whether data is written to the FIFO is determined by the last byte of the data, so that it is not necessary to wait for the data as in the prior art, thereby improving the throughput, reducing the circuit scale, and reducing the power consumption. it can. "Description of Third Embodiment of the Present Invention" See FIGS. 13 and 14. In general, an overhead indicating the head of a normal data group (hereinafter referred to as "head") is separate from normal data for transferring data on a transmission path.
(Abbreviated as OH) There is data, and one data is included in 53 normal data for each pass. Data length is the same as normal data (for example, corresponding to SOH, POH, etc. of SDH frame)
.

The OH data is also subjected to the duplex switching, and one of the 53 data must have a fixed period, so that this period needs to be monitored. For example, assuming that four paths are multiplexed on a transmission path, a 212-base counter with 4 paths × 53 data is required to monitor this period.

Further, since the phases of the respective paths need to be matched, it is also necessary to monitor that four OH data are continuous. Conventionally, a 212 counter for monitoring the cycle and a counter for monitoring the continuity of the OH data are provided independently.

In the present invention, the continuity of the OH data is monitored by the quaternary counter 109 as a means. That is, as described in the fourth invention, the eigenpath signals are 0, 1,
Since the period is fixed to 2, 3, this period is predicted by a quaternary counter, and the value of the path latched from the input data by the specific path latch 115 is compared with the predicted value by the comparator 110a, so that the input specific path signal is obtained. Check for errors.

The carry of the quaternary counter is converted to a decoder.
The decoding is performed by 417, the decoded output is counted by the 53-base counter 112, and the carry is sent to the comparing unit 110b. on the other hand,
The OH data in the input data is detected by the OH data detection unit 107, and the OH data cycle can be monitored by comparing the carry of the 53-base counter with the comparison unit 110b. Furthermore, the continuity check unit
At 114, check the continuity of the OH data.

As a result, by combining the monitoring function of the continuity of the OH data and the monitoring function of the period, the circuit scale can be reduced. "Explanation of the Fourth Embodiment of the Present Invention" See FIGS. 15 and 16. When separating multiplexed data for four passes, filtering is performed for each pass by the unique pass filter 104, and only data for the own pass alone is extracted. . As a result, data other than the own path is converted from valid data to invalid data. Identification of valid data / invalid data is performed by a data enable transmitted in parallel with the data.

Therefore, after the data separation, out of the four data,
Only one valid data is received. For example, pass 0
The function block that takes in the data of (1) receives one of the four data as valid data.

According to the present invention, when monitoring the unique path period, the comparison unit 110 uses the characteristic that only one of the four data receives valid data and the valid data is always the unique path signal of the own path. The unique path signal of the own path and the two timings of the data enable are compared and monitored.
For example, as shown in the middle of FIG. 15, since the two timings of the unique path signal and the data enable are different, the unique path error is output from the comparing unit 110 at this timing. As a result, the reliability is improved as compared with the case where the cycle is monitored with the unique path signal alone. "Explanation of Fifth Embodiment of the Present Invention (No. 1)" FIGS. 17 and 18
The monitoring of the OH data described in the third aspect of the present invention is performed in four consecutive data and its cycle.

The monitoring is arranged before the FIFO for changing clocks. Then, the OH data is transferred to the next functional block (such as a terminating device). Conventionally, in order to realize the function of monitoring / transferring the OH data, the received OH data is written to the clock transfer FIFO and transferred in the same manner as the normal data. With this method, even if the received OH data is abnormal, it was transferred as abnormal. Therefore, once an error occurred, the error was transferred after that.

In the present invention, by writing / reading only the first data of the four consecutive data to / from the FIFO,
Notify only the head position of OH data. That is, the OH data detection unit 107 detects the OH data from the input data,
6 Differentiates the OH data and detects the start position of the OH data. At the same time, the OH data detection unit 107 monitors the OH data, and the multiplexing unit 118 multiplexes the OH data with the additional data and writes the multiplexed data into the FIFO 31.

The FIFO is controlled by the write controller 4 as described above.
1, the flag control 42 and the read control unit 43 perform this. And FIF
The additional data read from O is separated by the separating unit 215, and the OH data is copied four times using the separated OH data head signal.
Copy the OH data four times with 216.

Further, the OH data period generation unit 217 generates an OH data period using the determination result of the OH data monitoring unit 117 with respect to the detection output of the OH data detection unit 107, and the OH data insertion unit 208 generates the OH data period. Insert

Even if the monitoring result of the OH data is abnormal, if the OH data cycle is generated in the normal phase, the abnormality is not transferred. Thus, in the present invention, the transfer of the OH data abnormality is prevented, and the power consumption is reduced because only the head data of the continuous OH data is written in the FIFO. "Explanation of Fifth Embodiment of the Present Invention (Part 2)" FIGS. 19 and 20
Reference As in the description of the fifth embodiment of the present invention (part 1), when monitoring / transfer of OH data is realized, in the present invention, only the first data of four consecutive data is written to the FIFO.

The result of monitoring the OH data in the OH data monitoring unit 117 is notified as additional data to the reading side of the FIFO 31. If the monitoring result is normal, the OH written to the FIFO is written.
By reading the data four times repeatedly, four data continuations are realized.

By maintaining this cycle,
Even if the monitoring result of the OH data is abnormal, it can be realized by reading it out in the normal cycle. As a result, the received
Even if the monitoring result of the OH data is abnormal, it is prevented from being transferred as abnormal.

Further, the OH data written in the FIFO is
Since continuous data can be realized by performing continuous reading, the circuit scale can be reduced. "Explanation of the sixth embodiment of the present invention" See FIGS. 21 and 22. When monitoring / transfer of OH data is realized in the same manner as in the fifth embodiment, the OH data itself is not written in the FIFO but is written in the present invention. In response to the OH data reception in the same procedure as the end flag, the flag is changed from the write-side phase of the FIFO to the read-side phase according to the flag.

OH data detecting section 107 which has detected OH data
Sends the detection result to the OH flag / trigger generation unit 119, so that the OH flag / trigger generation unit 119 generates an OH flag / trigger and sends it to the OH flag control unit 120. So, OH
The flag control unit 120 sets the OH flag.

The OH flag is transferred to the reading side. When the OH flag is detected by the reading side OH data inserting unit 208, the OH flag inserting unit 208 inserts the built-in OH data into the position of the OH flag. Clear 121.

For input data, the write controller 41, the flag controller 42, and the read controller 43 control the FIFO 31 to perform clock transfer. As a result, the transfer can be realized without writing the OH data to the FIFO, thereby reducing the power consumption. "Explanation of Embodiment 7 of the Present Invention (Part 1)" FIGS. 23 and 24
Reference When realizing monitoring / transfer of OH data as in the fifth invention, in the present invention, OH data itself is not written in the FIFO but is used by using additional data.

The additional data notifies various control information by a signal passed in parallel with the data. OH data reception information is provided in the additional data, and when the OH data detection unit 107 detects the OH data, an OH data detection bit is set.

The OH data detection bit sent from the OH data detection unit 107 is multiplexed with additional data by the multiplexing unit 118, and the FIFO 31 changes the clock. In addition, FIFO
31 is controlled by the write address generator 41, the flag controller 42, and the read address generator 43 in the same manner as described above.

Then, the OH data detection bit is separated from the additional data read by the separation unit 215, and is added to the OH data insertion unit 208. The OH data insertion unit 208 inserts OH data at the timing of the OH data detection bit.

As a result, the transfer can be realized without writing the OH data to the FIFO, thereby reducing the power consumption. "Explanation of Seventh Embodiment of the Present Invention (Part 2)" FIGS. 25 and 26
In the transmission device, monitoring data is sent within a certain period to monitor the inside of the device. And each section (each functional block)
To monitor the inside of the apparatus based on whether monitoring data can be detected within the period.

The monitoring data is also detected by the transmission line duplex switching function, but the detection position is determined by the clock transfer FI.
Perform before the FO. Also, like the OH data, it is necessary to transfer monitoring data for the next functional block.

Conventionally, the received monitoring data has been detected and transferred via a clock transfer FIFO while being received at the same time. In the seventh aspect of the present invention, the monitoring data is transferred in the same procedure as the OH data processing in the description of the embodiment (part 1). That is, the monitoring data monitoring unit 122 monitors the monitoring data, and the monitoring data detection unit 106 detects the monitoring data. The monitoring data itself is not written to the FIFO,
The multiplexing unit 118 multiplexes the additional data.

The monitoring data reception information is provided in the additional data, and a bit is set when the monitoring data is received. And
Clock transfer of the additional data via FIFO 31
When the monitoring data reception information is separated by the separation unit 215 on the reading side of the FIFO, the reception information is sent to the monitoring data insertion unit 209 as monitoring data timing. Therefore, the monitoring data insertion unit 209 inserts monitoring data at the monitoring data timing.

The FIFO is controlled by the write address generator 41, the flag controller 42, and the read address generator 43 in the same manner as described above. As a result, the transfer can be performed without writing the monitoring data to the FIFO, thereby reducing power consumption. "Eighth Embodiment of the Present Invention" See FIGS. 27 and 28 The monitoring data transfer method of the present invention is performed by using a monitoring cycle of monitoring data.

The monitoring data monitoring unit 122 only needs to detect the monitoring data by the monitoring data detection unit 106 within a certain period.
It does not monitor the period of the monitoring data. During the monitoring period of the monitoring data, the monitoring data is received as a timing signal in parallel with the data.

In the present invention, detection and transfer of monitoring data are performed independently. Detection of monitoring data is performed by the FIFO 31
The determination is made based on whether or not the detection can be performed within a certain period in the preceding stage of the operation. Also,
All detected monitoring data is invalid data in FIFO 31
Is not written to And a rising edge detector
At 123, a rising edge of the timing signal indicating the monitoring period is detected, and this edge detection signal is
Multiplexes in the additional data, and performs clock transfer via the FIFO 31.

After separating the edge detection signal in the additional data, the separation unit 215 on the reading side adds this signal to the monitoring data insertion unit 209 and monitors the signal at this timing (indicating the position of the first invalid data after detection). Insert data and transfer.

In this method, since the monitoring data is inserted by using the rising edge of the timing signal indicating the monitoring period as a trigger, the monitoring data can be reliably detected within the monitoring period in the next functional block.

In addition, since the monitoring data can be transferred without writing to the FIFO, power consumption can be reduced. "Description of Ninth Embodiment of the Invention (No. 1)" FIGS. 29 and 30
When performing duplex switching of the transmission path, according to the present invention, when data is written into the FIFOs 31 ₀ and 31 ₁ for clock change, a serial number (No) is added as phase information for each data. FI
FO write / read control is carried out in the write controller 41 _0, 41 _1, the read control unit 43 _0, 43 _1.

The serial number is assigned to the additional data, and the data is written / read to / from the FIFOs 31 ₀ and 31 _{1 in the same} manner as the data, and the serial numbers are compared by the serial number comparing unit 223 provided on the FIFO reading side. .

By this method, the reading order of the FIFO can be checked. At the same time, the phase can be compared by comparing the serial numbers of the 0 system and the 1 system on the reading side of the FIFO.

An example of the serial number is shown in the lower part of FIG. As a result, the FIFO reading order check and the phase comparison can be performed simultaneously, so that the reliability is improved and the circuit scale can be reduced. "Description of Ninth Embodiment of the Present Invention (No. 2), (No. 3)" See FIGS. 31, 32, and 33. When performing duplex switching of the transmission line, the phases of the 0 system and the 1 system must match. It cannot respond to instantaneous interruption switching.

Therefore, conventionally, phase monitoring has been performed by comparing all bits of the data of the 0 system and the data of the 1 system. In the present invention,
The phase is monitored using the unique path signal included in the header part of the data.

As shown in FIG. 31, the eigenpath signal is a signal fixedly assigned to each path, and the sequence of data on the transmission path after the data is multiplexed by the multiplexing unit 118 is as follows.
A fixed cycle is set to pass 0, pass 1, pass 2, and pass 3. Therefore, phase monitoring is performed using this fixed cycle.

Since this cycle is a fixed cycle, even when invalid data is received, it can be easily predicted from previously received valid data. In FIG. 32, the unique path signal (for example, path 0) in the data read from the FIFOs 31 ₀ and 31 ₁ of the 0-system and the 1-system is converted into the unique-path latch / prediction unit 211 _{0 of the 0-} system and the 1-system. unique Pasuratchi / respectively latched by the prediction unit 211 ₁ compares the latched results match comparison unit 212, and sends to the control unit 205 switches the comparison result if the match.

The switching control unit 205 sends a switching signal to the selector 214 when a switching request is input, and switches the system. That is, as shown in FIG. 33, switching is not performed in a portion where the phases do not match.

In this method, only part of the data needs to be monitored, so that the circuit scale and the processing time can be reduced as compared with the conventional method. "Description of Ninth Embodiment of the Present Invention (No. 4)" FIGS. 34 and 35
When performing duplex switching of the reference line, the clocks must be switched in the FIFO, then the phases of the 0 system and 1 system must be compared and the phases must match.

Conventionally, when this phase comparison is performed, 0 system, 1 system
All bits of system data were compared. In the present invention, 0
The phase comparison is performed by counting "1" counters 220 ₀ and 220 ₁ which count the number of “1” of the data of the system 1 and the system ₁ and comparing the count value by the match comparison unit 212. Is one data length unit.

When the comparison result of the coincidence is obtained and the switching request is input, the switching control unit 205
Perform the switching of 4. That is, a counter can be provided for each of the 0-system and 1-system, and the counter is incremented each time data "1" is received, and the phase can be easily compared by comparing the count value in data units. "Description of Ninth Embodiment of the Present Invention (No. 5)" FIGS. 36 and 37
Reference As described in the ninth embodiment of the present invention (part 4),
In the case of performing the duplex switching of the transmission line, in the ninth invention, the FI
After the data is clock-switched by the FOs 31 ₀ and 31 ₁ , the parity adders 210 ₀ and 210 ₁ add the vertical parity to each of the data of the 0 system and 1 system, and the coincidence comparing unit 212 outputs the data frame pulse. Each time (FP) is applied, a comparison is made. When the comparison results match and a switching request is input, a switching control signal is sent from the switching control unit 205 to the selector 214 to switch the system.

According to this method, the phase comparison between the 0 system and the 1 system requires only parity bits, so that the circuit scale can be reduced. "Description of Ninth Embodiment of the Present Invention (No. 6)" FIGS. 38 and 39
When performing duplex switching of a transmission line, the description of the ninth embodiment of the present invention (No. 5) and (No.
A phase comparison of the system and the system is realized.

That is, after the clocks are changed by the FIFOs 31 ₀ and 31 ₁ , the “1” counters 220 ₀ and 220 ₁ compare the count results obtained by counting the number of data “1” of the corresponding system, and add the parity. The comparison of the parity bits added by the units 210 ₀ and 210 ₁ is performed by the coincidence comparing unit 212. For comparison, data
Performed every time a frame pulse (FP) is input.

The switching control unit 205 sends a control signal to the selector 214 in response to the comparison result at the time when the switching request is input, and switches the system. In this way,
It is possible to cope with a case where data, which is a weak point of parity, is inverted even number bits. "Explanation of Ninth Embodiment of the Present Invention (No. 7)" FIGS. 40 and 41
When checking the transparency of data at the time of switching the transmission line duplex, a CRC generation unit 125a is provided at the entrance of the functional block, and a CRC check unit 221 is provided at the output unit.

Then, on the input side, the CRC for the input data
Generates a code, inserts it into additional data, and writes it to FIFO 31.
4 and read the CR
This is achieved by checking the C code.

[0172] Incidentally, the data clock transfer, the write control unit 41 performs and controls the writing / reading of FIFO 31 ₀ by the read control unit 43. Normal data may be rewritten because various processes are performed on the write side and the read side for the header part, but the payload part is transmitted transparently. Therefore, the permeability can be monitored by checking at the entrance and the exit.

In addition, if a CRC is used, a one-bit error can be corrected, so that an improvement in reliability can be realized. This also means that the switching of the system using the selector 214 is monitored, which further improves the reliability. "Explanation of Tenth Embodiment of the Present Invention (No. 1)" FIGS. 42 and 43
When the duplex switching of the transmission line is performed, when the serial number is added as in the ninth embodiment of the present invention, the FIFO is used.
The parity addition units 210 ₀ and 210 ₁ provided on the write side of the data further add parity to the data and the serial number (additional data).

_On the read side of the FIFOs 31 _{0 and} 31 ₁ , the serial numbers are crossed in the manner of crossing between the 0-system and 1-system, and the serial numbers are checked by the serial-number checking units 219 ₀ and 219 ₁ and the parity check is performed. Parities are checked by the units 201 ₀ and 201 ₁ respectively.

The writing of the FIFO is performed by the writing control sections 41 ₀ , 4
1 _1, reading is carried out in the read control unit 43 _0, 43 _1. Then, the match comparison unit 212 compares the check results, adds the comparison result to the selector 214, and switches the system.

That is, the serial number and parity of system 0 are 1
The system data is checked, and the system 0 data is checked with the system 1 serial NO and parity. By this method, the reliability of the phase comparison and the read order of the FIFO can be improved. "Explanation of Tenth Embodiment of the Present Invention (No. 2)" FIGS. 44 and 45
When performing duplex switching of the reference transmission line, the present invention uses an error detection signal, for example, a CRC code.

The clock transfer FIFOs 31 ₀ , 31 ₁
CRC adding sections 125 ₀ and 125 ₁ add the CRC codes generated for both system 0 and system 1. The FIFO write control unit 41 _0, 41 ₁ flag control 42 _0, 42 _1, controlled by the read control unit 43 _0, 43 _1. The CRC code also writes / reads data to / from the FIFO in the same manner as the data, and a CRC check section 221 ₀ , 221 ₁ provided after the FIFO.
Check the CRC code with. At this time, the CRC code is checked by crossing the system 0 and system 1 in a crossing manner.

That is, the system 1 data is checked by the system 0 CRC code, and the system 0 data is checked by the system 1 CRC code. Then, the check result is compared by the coincidence comparison unit 212, and the comparison result is sent to the switching control unit 205. Therefore,
The switching control unit 205 switches the system by driving the selector 214 when there is a switching request and the comparison results match.

By comparing the phases of the 0-system and the 1-system with this method, the write / read of the FIFO is checked at the same time, and the reliability can be improved. "Explanation of Tenth Embodiment of the Present Invention (Part 3)" FIGS. 46 and 47
When performing duplex switching of a transmission line, the present invention uses parity to perform the switching.

Clock Transfer FIFO 31₀, 31₁Write side of
Parity adding unit 210₀, 210₁And set both system 0 and system 1
Add the credibility. FIFO 31₀, 31₁Control is write control
Part 41 _0, 41₁, Flag control 42_0,42₁, Read control unit 43₀, 43
₁Do with.

The parity bit is written / read from / to the FIFO in the same manner as the data, and the parity check 201 ₀ , 201 ₁ provided on the read side of the FIFO performs the parity check. At this time, the parity check is performed by crossing the 0 system and the 1 system in a crossing manner.

That is, the system 1 data is checked by the 0 system parity bit, and the system 0 data is checked by the 1 system parity bit. Then, the parity check result is compared by the coincidence comparison unit 212, and the comparison result is sent to the switching control unit 205.

Therefore, the switching control unit 205 drives the selector 214 to switch the system when there is a switching request and the comparison results match. By comparing the phase of the 0 system and the phase of the 1 system in this manner, the write / read of the FIFO is checked at the same time, and the reliability can be improved. "Explanation of Tenth Embodiment of the Present Invention (Part 4)" FIGS. 48 and 49
When performing duplex switching of the transmission line, in the present invention, BIP2 (B
This is done by using it Interieaved Parity 2).

Clock Transfer FIFO 31₀, 31₁Write side of
In addition, BIP2 addition unit 126₀, 126₁BIP2 for both system 0 and system 1
Add a bit. FIFO 31₀, 31₁Control is write control
Part 41 _0, 41₁, Flag control 42_0,42₁, Read control unit 43₀, 43
₁Do with.

The BIP2 also writes / reads data to / from the FIFO in the same manner as the data, and checks the BIP2 using BIP2 checks 222 ₀ and 222 ₁ provided on the FIFO reading side. At that time, the check of BIP2 is performed by crossing the 0 system and 1 system in a crossing manner.

That is, the system 1 data is checked by the system 0 BIP2, and the system 0 data is checked by the system 1 BIP2. Then, the comparison result generated by comparing the check results in the coincidence comparison unit 212 is sent to the switching control unit 205.

The switching control unit 205 drives the selector 214 to switch the system when there is a switching request and the comparison results match. By comparing the phases of the 0-system and the 1-system with this method, the write / read of the FIFO is checked at the same time, and the reliability can be improved. "Description of the eleventh embodiment of the present invention" See FIGS. 50 and 51. The clock transfer FIFOs 31 ₀ and 31 ₁ have a surface configuration as shown in the second embodiment of the present invention (No. 2). In this case, the FIFO read control includes a read address counter for counting the data length of the data and a surface counter 432 for counting the surface.
₀ , 432 ₁ and the counter value is the FIFO read address,
Used for flag control.

Conventionally, the read address counter and the surface counter are provided separately for the 0 system and the 1 system. In the present invention, the read address counter is shared by the 0 system and the 1 system, and the surface counters are separately provided by the 0 system and the 1 system.

That is, in FIG. 50, the differentiator 116 differentiates the input system frame pulse (FP) to detect the rising point of this pulse, and outputs the detection result to the 27-base counter 22.
4 is initialized. Therefore, the 27-ary counter starts counting operation with an input clock (not shown). The count value 27 corresponds to one data having a fixed data length.

Now, the count value of the 27-ary counter is applied to AND ₁ , and the carry is AND ₂ and 0 system, 1 system plane counter 432 ₀ ,
432 ₁ AND ₂ generates 0-system and 1-system flag control /
When a flag of "1" from the CLR units 440 ₀ and 440 ₁ (indicating that reading has been completed since writing has been completed) is detected, the output of AND ₂ (
(Read address) is applied to the FIFOs 31 ₀ and 31 ₁ , and the written data is read.

Note that the 0-system and 1-system flag control generation / CLR unit
When the carry from the 27-ary counter 224 is input, 440 ₀ and 440 ₁ set the flag of “1” to “0”. As a result, the read enable (RE) becomes "0" and the data reading stops.

The AND ₁ receives a carry from the 27-ary counter 224 and generates a 0-system / 1-system flag control generation / CLR unit 44.
If the flags of 0 ₀ and 440 ₁ are “1”, the surface of the system 0 advances by one and the read surface is raised by one.

That is, by sharing the read address counter, the read position in the fixed length data does not shift. However, since the 0-system and 1-system must operate independently, in order to realize this, the 0-system and 1-system surface counters are provided and operated independently. "Description of the Twelfth Embodiment of the Invention (No. 1)" FIGS. 52 and 53
If the clock transfer FIFOs 31 ₀ , 31 ₁ have a plane configuration as shown in the second embodiment of the present invention (part 2), a read address counter for counting the data length of data and a plane count It consists of a surface counter.

Conventionally, the read address counter and the surface counter are provided separately for the 0-system and the 1-system. However, in the present invention, these two types of counters are shared, and the input data becomes valid data / invalid data. Regardless, the counter counts up.

In the case of valid data, writing / reading to / from the FIFO is performed using the counter value as an address.
In the case of invalid data, the writing / reading is stopped by setting the surface as an empty surface.

That is, the data frame pulse (data FP)
Is input, the 0-system and 1-system write address generation units 41
4 ₀ and 414 ₁ start the operation, send the count value as a read address, and change the last write address to the 0-system and 1-system flag control unit 42 at the time of the last write address of each surface.
2 ₀ , 422 ₁

On the other hand, the 0-system and 1-system flag control units 422 ₀ , 422 ₁
Sends the write enable (WE) to the FIFOs 31 ₀ and 31 ₁ if the data enable (EN) is valid, and does not send the write enable (WE) if the data enable (EN) is invalid. If the data enable and the final write address are set, read enable
(RE) generated by 0-system and sent to the 1-system FIFO 31 _0, 31 _2.

Note that the common read address for the 0-system and 1-system
Since the address generation unit 438 generates a read address,
Readout enable (RE) applied 0-system, 1-system FIFO 3
1₀, 31 _TwoData can be read from the.

That is, an address to the FIFO is generated regardless of valid data / invalid data.
FIFO write enable (WE) / read enable (RE)
Stop writing to control writing / reading.

Further, the flag control units 422 ₀ and 422 ₁ include the 0 system,
Provided separately for one system. With this method, the read address counter and the surface counter of the FIFO can be shared by the 0 system and the 1 system, and the 0 system and the 1 system are enabled and distinguished.

As a result, phase shifts of the 0 system and the 1 system can be prevented, and the circuit scale can be reduced. "Description of the Twelfth Embodiment of the Present Invention (Part 2)" FIGS. 54 and 55
When the phases of the reference 0 system and the 1 system are coincident, the same data is stored in the same address in the clock transfer FIFOs 31 ₀ and 31 ₁ .

In the present invention, as a check method, a FIFO
The parity is added to the data and the write address on the write side, and writing / reading to / from the FIFO is performed in the same manner as the data.

The parity check on the read side is performed after duplex switching has been performed, and includes the read address. That is, as shown in FIG.
_On the write side of the FOs 31 ₀ and 31 ₁ , the 0-system and 1-system write address generators 414 ₀ and 414 ₁ and the 0-system and 1-system parity generator 20
3 _0, 203 parity checker 201 _1, after dual switching
Are provided.

Then, the clock transfer FIFOs 31 ₀ , 31 ₁
Add the parity to the same write address as the data on the input side of. On the read side, since the read address is the same (using a common 0/1 address generator), the same data and parity should be read from the same address.

Therefore, even if parity is added in the 0 system and the 1 system, the check result should be the same before and after the selector 214. Therefore, only one parity check unit 201 is provided after the selector.

That is, since the parity check including the address is performed, the jump of the address can be checked.
With this method, it is not necessary to provide a parity check unit for each of the 0-system and the 1-system as in the related art. Also,
Since the parity check includes an address, reliability is also improved. "Description of the thirteenth embodiment of the present invention (No. 1)" FIGS. 56 and 57
Reference (1) In the present invention, additional data includes a data enable,
The start address of each surface of the FIFOs 31 ₀ and 31 ₁ is assigned, and the data is written to the FIFO regardless of valid / invalid data. 0 series,
When the 1-system write enable (EN) generation units 413 ₀ and 413 ₁ generate an enable, the output of the pre-processing result unit 128 in the previous stage of the FIFO is reflected.

[0207] Here, the start address assigned to the additional data (head address generator 411 ₀ is generated), the head address of a plane writing surface counter 412 ₀ next. Further, the initial control unit 127 is provided, the write address generator 414 ₀
Separately, initial control for initializing the FIFO data at POWER ON is performed.

[0208] Next, when invalid data writes data enable and the start address from the write enable generator 413 _0, allocated 1 byte only. Like the write side, the read side of the FIFO also reads regardless of valid / invalid data. However, in the case of invalid data, only one byte of the data enable and the head address is written, so that only one byte is read.

That is, on the writing side, the head address written in the FIFO is the head address of the next surface to be written.
On the reading side, it becomes the head address of the next surface to be read as it is.

The read additional data is transferred to the switching control unit 20.
Switching is performed by the selector 214 controlled according to the switching control from step 5, S / P conversion is performed by the S / P conversion unit 225, the additional data is separated, and latched by the latch unit 226.

Using the separated enable signal, a read address is generated by the read address generator 434, and an enable for data is generated by the enable generator 35. Then, the head address of the next surface read from the FIFO is loaded for each data as a load value of the read address generation unit 434.

The read frame pulse (FP) serving as the time reference of the read address generation section 434 is generated by the master timing generation section 231 from the system-frame pulse (SYS-FP).

[0213] It should be noted that, when performing the dual switching, FIFO 31 _0,
31 ₁ of reading is performed only from the system selected by the switching control unit 205. Also, since the data read from the FIFO is a single system, the output of the 0-system / 1-system FIFO can be wired-OR (the portion marked with * in FIG. 56). This eliminates the need for a selector function for duplex switching.

In other words, the FIFO has three sides as before,
When the power is turned on, the contents of the FIFO are all set to "0" (initialization control). After this is completed, FIFO is the manner to select an address from the write address generation unit 414 _0. According to the present invention, information on a surface being written in additional data while data is being written on surface 0 (surface information next to the surface currently being written)
And write data enable into FIFO.

On the read side, a read address generator 434
Of the read FP, the load value is naturally "0", so the read address generation unit 434 counts up from "0". As a result, additional data (data enable is inserted above) is read from the read address 0 of the FIFO.

The read additional data is supplied to the selector 214
And is converted in parallel by the S / P converter 225,
Latched. At this time, if the data enable (EN) is invalid, the read address from the read address generator 434 is not output. The surface information is decoded by the decoder 417 and enters the read address generation unit 434. Therefore,
When reading the “0” plane, additional data contains surface information
It is "1".

Then, when the next data FP enters the read address generation unit 434: “1” of the latched plane information is taken into the read address generation unit, and the plane information is read from here.
The read address of "1" is output.

By repeating this, when one surface is being read, the surface information of two surfaces is sent to the read address generator. Thus, while reading, it is possible to determine which side is to be read next.

If invalid, the reading is stopped at that time. According to this method, it is not necessary to transfer the write end flag between the write side and the read side of the FIFO unlike the related art, and the circuit can be reduced. (2) When the switching control unit 205 in FIG. 56 performs the duplex switching control, the first three bits are read from both systems. As shown in the thirteenth embodiment of the present invention (part 1), the data enable and the start address are allocated to the three bits, and the data enable and the start address of the 0-system and the 1-system are compared with the coincidence comparison unit 212 The phase comparison is performed by comparing with.

The result of the phase comparison is used as a condition for instantaneous interruption / non-instantaneous interruption switching of duplex switching. That is, by comparing the additional data of the 0 system and the 1 system with the coincidence comparing unit 212,
The phases of the system 0 and the system 1 are monitored. The switching control unit 205 switches the system when both the comparison result of the coincidence comparing unit and the 0/1 system switching request are input.

According to this method, the phase comparison can be performed more easily than in the conventional case, so that the circuit scale can be reduced. "Description of the thirteenth embodiment of the present invention (No. 2)" FIGS. 58 and 59
Reference When duplex switching control is performed in the thirteenth embodiment of the present invention, the first byte is read from both systems.

As shown in the description of the thirteenth embodiment of the present invention (part 1), a data enable and a head address are allocated to the one byte. Since the start address is a fixed value, it can be predicted by the encoder 228.

For example, if the FIFOs 31 ₀ and 31 ₁ have a three-sided configuration, there are three types of head addresses.
Can be realized. Data read from FIFO is latched by 22
6 _0, and latched in 226 _1, in accordance with switching control of the switching control unit 205 performs switching of the system by the selector 214, the output of the selector to generate a load value of decodes ternary counter 227 in the decoder 417.

The generated load value is converted to a ternary counter.
Load to 227. As a result, the ternary counter repeatedly reads out the three types of addresses and adds them to the encoder 228.

The encoder 228 encodes the address to be added and sets the encoded address as the predicted head address.
Apply to 2 ₀ and 212 ₁ . The match comparison units 212 ₀ and 212 ₁ compare the encoder prediction data with the start addresses of the 0-system and 1-system actually read and latched from the FIFO, and protect units 229 ₀ and 229 to improve reliability. Take protection with ₁ . Then, the comparison result is used as a condition for the instantaneous interruption / non-instantaneous interruption switching control of the duplex switching as in the related art.

[0226] That is, latches read data from the FIFO to the latch unit 226 _0, 226 _1. The ternary counter 227 becomes operable when the fixed-length data FP is input, and starts counting from 0 when one of the head addresses 0 latched by the latch unit is decoded by the decoder 417 and input.

This cant value is encoded by the encoder 228 and added to the coincidence comparing sections 212 ₀ and 212 ₁ as a predicted head address. These comparators receive a latch output at the predicted timing and detect a match / mismatch.

If N times do not match consecutively, the system is switched to another system. When switching to another system, set the start address of the other system to 1
It is loaded into the ternary counter only once and counts. After that, the counter runs by itself.

According to this method, the circuit scale can be reduced as compared with the related art. "Description of the thirteenth embodiment of the present invention (No. 3)" FIGS. 60 and 61
Reference In the case where clock switching of data is realized without using a flag as shown in the embodiment of the present invention in FIG. 60, it is necessary to write / read 3 bytes of data to / from the FIFO 31 even in the case of invalid data.

This is because the additional data is serial data, and the data to be transferred is a total of 3 bits, that is, data enable and 2 bits of surface information indicating the head address.

[0231] In the present invention, in order to reduce the number of bytes to transfer in FIFO 31 ₀ during invalid data, when invalid data by using selectors 129a _0, is the main signal instead of 2 bits showing a surface information additional data FIFO assigned to beginning of data
Delivery at 31 ₀ . This is because there is no need to transfer the main signal data during invalid data.

That is, selectors 129a ₀ and 129b ₀ and selectors 214a and 214b are provided on the write and read sides of the FIFO.
On the writing side, when valid data is input data, the selector 12
Via 9a _0, additional data through the multiplexer 118, respectively, written to the FIFO.

[0233] When the invalid data, the result data EN preprocessing, and sends a 0-system EN generator 35 ₀ corresponds to the invalid data "0" to the selector 129a _0. From this, the 0 system surface counter
412 output (surface information) is written to the select has been FIFO 31 ₀ selector 129a _0.

On the read side, when the data is valid, the data is output as it is as the main signal, and the additional data is supplied to the selector 214a, the serial / parallel (S / P) converter 225, the latch 226, and the selector 214b for selecting the lower side. The signal is input to a decoder (DEC) and decoded. Then, the decoded output is loaded into the read address generation unit 434 as surface information.

In the case of invalid data, data enable (EN)
Becomes "0", the selector 214b selects the upper side. At this time, the surface information written in the data is latched by the latch unit 226 via the selector 214a.

Then, the selector 214b selecting the lower side
After that, the data is decoded by a decoder (DEC), and is applied to a read address generator 434 to load the surface information.
Since the data enable (EN) is "0" (indicating invalid data), reading is stopped only by reading one column.

By performing the clock transfer in this manner, flag control becomes unnecessary and the circuit scale can be reduced, and access to the FIFO at the time of invalid data can be made by only one bit, so that power consumption can be reduced. "Description of the Fourteenth Embodiment of the Invention (Part 1)" FIGS. 62 and 63
Reference As shown in the embodiment of the present invention shown in FIG. 62, when data clock switching is realized without using a flag, it is necessary to write / read 3-bit data to / from the FIFO even when invalid data is present. . That is, the additional data is serial data, and the data enable passed to it,
This is because the total of the two bits of the surface information indicating the start address is 3 bits. In the present invention has a FIFO 36 ₀ of FIFO 31 ₀ and for additional data for the main signal separately. Further, since the address for the additional data is performed in the ternary of the surface information, the FIFO for the additional data can be composed of three flip-flops.

First, the data on the write side is stored in the surface counter 41.
It writes the surface information from the 2 _0, the output from the write address generator 414 ₀ as the address. Data EN from the surface information of the additional data and an enable generator 35 ₀ writes the same surface information as the data as an address.

Next, the read side starts with the read address of the additional data and the data as the initial value 0. The additional data starts at the initial value 0, latches the read surface information in the latch unit 226, and continues reading as additional addresses. The main signal is read out one data delay after the surface information of the additional data.

That is, the surface information and the data enable of the additional data are read ahead of the main signal. Here, the signal flow in FIG. 62 will be specifically described.

As shown, another FIFO 3 for additional data
6 ₀ provided, then reads the surface information of the surface and data enable
Write (EN). This makes it possible to determine whether the surface to be read next and the data are valid or invalid. Therefore, if the data is invalid, no reading is performed.

[0242] Then, surface counter 412 _0, when the data FP is input, go to count the surface. Start address generator
411 ₀ is loaded into the write address generation unit 414 ₀ and generates the start address by using the surface information. As a result, the write address generation unit generates a write address and outputs the FIFO 31 ₀
Add to Reference numeral 128 denotes a preprocessing result section.

[0243] On the other hand, FIFO 36 ₀ writes plane information and data enabled by the face information from the face counter 412 ₀ to the address. The read side uses the read FP
(The value obtained by decoding the surface information latched by the latch unit 226)
Is loaded into the read address generation unit 434 to generate a read address.

In the case of additional data, the read surface information is latched in the latch section 226 and becomes the read address as it is. Also, the validity / invalidity of the surface information and the data is extracted using the applied read address.

As described above, the read address generation section 434 operates regardless of the validity / invalidity of data, but is read out from the FIFO only when data is valid. By reading additional data by this method, it is possible to identify whether the next main signal to be read is valid data or invalid data. Therefore, if the main signal is valid data, it is read, but if it is invalid data, no byte is read.

Thus, at the time of data clock transfer,
Since the flag control of the FIFO is not required, the circuit size can be reduced, and the access to the FIFO is not required at the time of invalid data, so that the power consumption can be reduced. "Description of Fourteenth Embodiment of the Present Invention (Part 2)" FIGS. 64 and 65
The control of the clock transfer FIFO is conventionally performed by flag control.

In this case, since the flag is controlled in units of planes using a FIFO as a plane configuration, the circuit scale increases in proportion to the number of planes. In the present invention, to control the number of FIFO 31 ₀ write / read by adder 131.

First, on the write side, a write address is generated by the write address generator 414 by enabling data of input data. And the final address decoding unit
Decode the last address of each side of the FIFO with 418 and adder 1
+1 is added to 31.

Then, on the read side, the output of the adder 131 is latched by the latch section 226, and the latch output is
If the value is 1 or more, it is determined that data is stored in the FIFO, and the output of the OR circuit is sent to the read address generation unit 434. Therefore, the read address generation unit generates a read address and starts reading.

The final address on each side of the FIFO is also decoded by the final address decoding unit 418 on the read side.
Adder 131 is decremented by one. That is, the write address generation unit
414 outputs the write address to the FIFO 31. The final address is decoded by the final address decoding unit 418, the decoding result is added to the adder 131, and the output of the adder is set to +1.

After latching the output of the adder 131, the latch unit 226 performs an OR operation and adds it to the read address generation unit 434. If the data applied to the E terminal is "1" or more, the read address generation unit 434 starts generating a read address and outputs it to the FIFO.

When the FIFO is read out from one side, it is decoded by the final address decoding unit 418 and -1 is added to the adder to lower the output of the adder by one. The timing generation unit 13
In the case of “0”, using the input system frame pulse (SYS-FP), the read-side fixed-length data FP is generated and added to the read address generation unit 434.

That is, when the writing is completed, the adder is incremented by 1, so that the reading is started, and when the reading is completed, the adder is decremented by 1. The generation of the head address of each side is performed by decoding the address by the head address decoding unit 439 on both the writing side and the reading side.

Thus, by accessing the adder on the write side and the read side and controlling the FIFO, the circuit scale can be reduced as compared with the related art without being affected by the number of FIFO surfaces.

[0255]

As described in detail above, according to the first aspect of the present invention, clock cutoff monitoring, data length monitoring, parity
By performing checks and unique path monitoring in parallel processing,
Data delay and circuit scale can be reduced, and throughput can be improved.

According to the second aspect of the present invention, according to (Part 1), writing to the FIFO is started regardless of the validity / invalidity of the data, the monitoring result of the data is reflected in the write end flag, and the clock of the data is read. By performing the transfer, the data delay and the circuit scale can be reduced, and the throughput can be improved. According to (Part 2), validity of data /
Regardless of the invalidity, writing to the FIFO is started, the data monitoring result is reflected in the switching of the writing control of the FIFO, and the clock is changed, the data delay and the circuit scale can be reduced, and the throughput can be reduced. Improvement can be realized. According to (Part 3), writing to the FIFO is started regardless of the validity / invalidity of data, data is monitored at the same time, the monitoring result is assigned to additional data, and the monitoring result assigned to the additional data is written. By performing write control as a condition for generating a flag, an improvement in data throughput and a reduction in circuit scale can be realized. According to (Part 4), regardless of whether the data is valid or invalid, the writing to the FIFO is started, the data is monitored at the same time, the monitoring result is allocated to the additional data, and the monitoring result allocated to the additional data is switched. By performing the write control under the condition (1), an improvement in data throughput and a reduction in circuit size can be realized.

According to the third invention, the overhead (O
H) By using the quaternary counter for monitoring the continuity of data as the 212-ary counter for monitoring the cycle of the OH data, the 212-ary counter can be reduced to a 53-ary counter.

According to the fourth aspect of the present invention, by monitoring the period of the eigenpath signal with the period of the valid data, the reliability is improved as compared with the case of monitoring the fixed path signal alone. According to the fifth aspect of the present invention, according to (Part 1), when transferring OH data, only the first data of the continuous OH data is FIFO
On the reading side, the read OH data is copied and transferred as continuous OH data, and at the same time, a cycle of the OH data is generated by reflecting the monitoring result of the OH data.

When abnormal OH data is received, it is transferred at the cycle of the normally generated OH data. This can reduce the power consumption of the FIFO and improve the reliability of the OH data transfer. According to (Part 2), in the same manner as (Part 1) of the fourth aspect of the present invention, only the first data of the continuous OH data is written into the FIFO, and the read side repeatedly reads the data to read the continuous OH data. And at the same time, generates the cycle of the OH data by reflecting the monitoring result of the OH data. Then, when abnormal OH data is received, the data is transferred at the cycle of the normally generated OH data. As a result, it is possible to reduce the circuit scale and improve the reliability of the OH data.

According to the sixth aspect of the present invention, when OH data is transferred, when the OH data is detected, the transfer of the clock is performed in response to the flag notification. As a result, the FIFO
, Power consumption can be reduced.

According to the seventh aspect of the present invention, according to (Part 1), when OH data is detected when transferring OH data,
The OH data detection bit is set and assigned to additional data, and the additional data is clocked through the FIFO. When additional data is read from the FIFO and the OH data detection bit is detected, OH data is inserted. As a result, the OH data itself can be transferred without being written to the FIFO, so that power consumption can be reduced. According to (Part 2), when monitoring data is transferred, power consumption can be reduced by performing clock transfer using additional data in the same procedure as (Part 1) of the seventh aspect of the present invention. .

According to the eighth aspect of the present invention, when transmitting the monitoring data, the timing signal indicating the monitoring period of the monitoring data is transmitted by using the additional data in the same procedure as (the first) of the seventh aspect of the present invention. By changing the clock and transferring the OH data in accordance with the edge of the timing signal, power consumption can be reduced without transmitting at an abnormal monitoring data period.

According to the ninth aspect of the present invention, according to (Part 1), when the phase comparison of the 0-system / 1-system is performed, a serial number is added to the data on the writing side of the FIFO and assigned to the additional data. Then, the data is written into the FIFO, and the reading side checks the reading order based on the serial number. Further, the phase comparison is performed by comparing the read serial numbers with the 0 system / 1 system.

Thus, the reading order of the FIFO can be checked at the same time as the phase comparison, so that the reliability can be improved. According to (No. 2), the circuit scale can be reduced by performing the phase monitoring at the time of performing the duplex switching of the transmission path using the unique path signal which is a part of the data. According to (Part 3), when performing the phase comparison of the 0 system / 1 system, “1” in the data is used.
By comparing the numbers in data units, the phase can be easily compared. As a result, the circuit scale can be reduced.
According to (Part 4), when performing the phase comparison of the 0 system / 1 system,
Adds vertical parity to the data,
By comparing the bits, the phase can be easily compared.
As a result, the circuit scale can be reduced. (Part 5)
According to the ninth aspect, by adding (No. 3) to (No. 4) of the ninth aspect of the present invention, it is possible to cope with a case where data, which is a weak point of parity, is inverted even number bits. As a result, it is possible to improve the reliability in the phase comparison and reduce the circuit scale.
According to (Part 6), when checking data transparency, a CRC code is added to the payload of received data, duplex switching is performed in the same manner as data, and the CRC code is checked at the data output stage. . As a result, the duplication switching is monitored at the same time as the data transparency, and the reliability can be improved.

According to the tenth aspect of the present invention, according to (Part 1), when performing the phase comparison of the 0-system / 1-system, a serial number is added to the data on the writing side of the FIFO and allocated to additional data. . Further, a parity is added to the data and the additional data. Then, the reading side checks the reading order based on the serial number.

At this time, the read order is checked for 0 system / 1
Phase comparison is performed by checking the system by crossing it. In this method, the write / read of the FIFO is checked at the same time, and the reliability can be improved.
According to (Part 2), when performing the phase comparison of the 0 system / 1 system,
The CRC code is added to the data on the write side of the FIFO, and the CRC code is checked on the read side. At this time, the CRC code is checked by crossing the system 0 / system 1 for phase comparison. In this method, the write / read of the FIFO is checked at the same time, and the reliability can be improved. According to (Part 3), when performing the phase comparison of the 0-system / 1-system, the parity is added to the data on the write side of the FIFO and the parity is checked on the read side.
At this time, the parity is checked by crossing the 0 system / 1 system and performing a phase comparison. This method
At the same time, writing / reading of the FIFO is checked, and reliability can be improved. According to (Part 4), when performing the phase comparison of the 0 system / 1 system, BIP2 is added to the data on the writing side of the FIFO, and BIP2 is checked on the reading side. At this time, the BIP2 is checked by crossing the 0 system / 1 system and performing a phase comparison. In this method, the write / read of the FIFO is checked at the same time, and the reliability can be improved.

According to the eleventh aspect of the present invention, clock transfer
When the FIFO has a plane configuration, the plane counter for read control is 0
By having the system / system 1 separately and sharing the read address counter with the system 0 / system 1, phase shift of the system 0 / system 1 can be prevented and the circuit scale can be reduced.

According to the twelfth aspect of the present invention, according to (Part 1), when the clock transfer FIFO has a plane configuration, the counter counts up regardless of valid / invalid data in write control, and the invalid data In some cases, the writing is stopped by using the writing enable.

The reading side also counts up the counter irrespective of valid / invalid data, and stops reading by using the read enable when the data is invalid. The data enable is notified from the writing side to the reading side by a flag.

According to this method, since the read-side surface counter and the read address counter can be shared by the 0-system / 1-system, a phase shift of the 0-system / 1-system can be prevented, and the circuit scale can be reduced. According to (Part 2), when the configuration of (Part 1) of the twelfth aspect of the present invention is adopted, the same data is written to the same address in the 0-system / 1-system FIFO.

Therefore, on the write side of the FIFO, a parity is added to the data and the address, the data is read from the FIFO, and the parity is checked after duplex switching. According to this method, it is not necessary to separately provide a parity check circuit for the 0-system / 1-system, and the circuit scale can be reduced. In addition, since the parity includes an address in addition to the data, the reliability can be improved. . According to the thirteenth aspect of the present invention, according to (No. 1), when the clock transfer FIFO has a plane configuration, the start address and data enable of each plane are notified from the write side to the read side via the FIFO. By doing
Since it is not necessary to control writing / reading of the FIFO with the writing end flag as in the related art, the circuit scale can be reduced.

Since the reading of the FIFO at the time of performing the duplex switching is performed only from the system selected by the switching control, the output of the 0-system / 1-system FIFO can be configured in a wired-OR manner. And the circuit scale can be reduced. Also, since the data read from the FIFO is always one-sided, power consumption can be reduced. According to (Part 2), when a configuration similar to (Part 1) of the thirteenth aspect of the present invention is adopted, only the first byte of each surface is valid /
The FIFO is written / read regardless of the invalid data, and the phase comparison is performed by comparing the first byte between the 0 system and the 1 system, which is the condition for duplex switching. According to this method, phase comparison can be easily performed, so that the circuit scale can be reduced. According to (Part 3), when a configuration similar to (Part 1) of the thirteenth aspect of the present invention is adopted, only the first byte of each surface is valid /
Write / read FIFO regardless of invalid data. Further, since the contents of the first byte to be read can be predicted, the predicted data and the read data are compared in the 0 system / 1 system respectively, and the comparison result is set as the duplex switching condition.
Since the phase comparison can be performed easily, the circuit scale can be reduced. According to (Part 4), as shown in (Part 1) and (Part 2) of the thirteenth aspect of the present invention, in the case where the flag is not used for controlling the clock transfer FIFO, invalid data is 3
Although access to the byte FIFO is required, the main signal is not used in the case of invalid data, so that only one byte access is required by allocating a part of the control signal to the first byte of the main signal.

That is, according to this method, the circuit size can be reduced because the flag control is not required, and the power consumption can be reduced because the access to the FIFO at the time of invalid data is only one byte. Regarding the fourteenth invention, according to (Part 1), according to the thirteenth invention, (Part 1) and (Part 2)
As shown in the above, in the case of a configuration that does not use a flag to control the clock transfer FIFO, it is necessary to have the FIFO separately for the main signal / individual data, and to pre-read additional data from the main signal on the FIFO reading side Since it is possible to identify whether the next data to be read is valid data or invalid data,
At the time of invalid data, access to the main signal FIFO can be stopped.

Since flag control is not required, the circuit scale can be reduced, and access to the main signal FIFO is stopped in the case of invalid data, thereby reducing power consumption.
According to (Part 2), an adder is used without controlling the clock transfer FIFO with a flag, and the adder is incremented by 1 when writing is completed, and decremented by 1 when reading is completed. If the output of the adder is +1 or more, the reading is continued.

As a result, since flag control is not required,
The circuit size can be reduced.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a main part of the present invention.

FIG. 2 is a basic configuration diagram of a FIFO control unit.

FIG. 3 is a configuration diagram of a main part of the first embodiment of the present invention.

FIG. 4 is a time chart of FIG. 3;

FIG. 5 is a configuration diagram of a main part of a second embodiment of the present invention (part 1);
It is.

FIG. 6 is a time chart of FIG. 5;

FIG. 7 is a configuration diagram of main parts of a second embodiment of the present invention (part 2);
It is.

FIG. 8 is a time chart of FIG. 7;

FIG. 9 is a configuration diagram of a main part of the second embodiment of the present invention (part 3);
It is.

FIG. 10 is a time chart of FIG. 9;

FIG. 11 is a configuration diagram (part 4) of a main part of the second embodiment of the present invention;

FIG. 12 is a time chart of FIG. 11;

FIG. 13 is a configuration diagram of a main part of a third embodiment of the present invention.

FIG. 14 is a time chart of FIG.

FIG. 15 is a configuration diagram of a main part of a fourth embodiment of the present invention.

FIG. 16 is a time chart of FIG.

FIG. 17 is a configuration diagram (part 1) of a main part of a fifth embodiment of the present invention;

18 is a time chart of FIG.

FIG. 19 is a diagram (part 2) of a main part of a fifth embodiment of the present invention;

FIG. 20 is a time chart of FIG.

FIG. 21 is a configuration diagram of a main part of a sixth embodiment of the present invention.

FIG. 22 is a time chart of FIG.

FIG. 23 is a configuration diagram (part 1) of a main part of a seventh embodiment of the present invention;

FIG. 24 is a time chart of FIG.

FIG. 25 is a configuration diagram (part 2) of a main part of the seventh embodiment of the present invention;

FIG. 26 is a time chart of FIG. 25.

FIG. 27 is a configuration diagram of a main part of an eighth embodiment of the present invention.

FIG. 28 is a time chart of FIG.

FIG. 29 is a configuration diagram (part 1) of a main part of a ninth embodiment of the present invention;

30 is a time chart of FIG. 29.

FIG. 31 is a diagram (part 2) of a main part of a ninth embodiment of the present invention;

FIG. 32 is a diagram (part 3) of a main part of a ninth embodiment of the present invention;

FIG. 33 is a time chart of FIG. 32;

FIG. 34 is a diagram (part 4) of a main part of a ninth embodiment of the present invention;

FIG. 35 is a time chart of FIG. 34;

FIG. 36 is a configuration diagram (part 5) of a main part of the ninth embodiment of the present invention;

FIG. 37 is a time chart of FIG. 36.

FIG. 38 is a diagram (part 6) of a main part of a ninth embodiment of the present invention;

FIG. 39 is a time chart of FIG. 38.

FIG. 40 is a configuration diagram (part 7) of a main part of the ninth embodiment of the present invention;

FIG. 41 is a time chart of FIG. 40.

FIG. 42 is a configuration diagram (part 1) of main parts of a tenth embodiment of the present invention;

FIG. 43 is a time chart of FIG. 42.

FIG. 44 is a main part configuration diagram (part 2) of the tenth embodiment of the present invention;

FIG. 45 is a time chart of FIG.

FIG. 46 is a main part configuration diagram (part 3) of the tenth embodiment of the present invention;

FIG. 47 is a time chart of FIG. 46.

FIG. 48 is a diagram (part 4) of a main part of a tenth embodiment of the present invention;

FIG. 49 is a time chart of FIG.

FIG. 50 is a configuration diagram of a main part of an eleventh embodiment of the present invention.

FIG. 51 is a time chart of FIG. 50;

FIG. 52 is a configuration diagram (part 1) of a main part of a twelfth embodiment of the present invention;

FIG. 53 is a time chart of FIG. 52.

FIG. 54 is a main part configuration diagram (part 2) of the twelfth embodiment of the present invention;

FIG. 55 is a time chart of FIG. 54.

FIG. 56 is a diagram (part 1) of a main part of a thirteenth embodiment of the present invention;

FIG. 57 is a time chart of FIG. 56.

FIG. 58 is a configuration diagram (part 2) of essential parts of a thirteenth embodiment of the present invention;

FIG. 59 is a time chart of FIG. 58;

FIG. 60 is a main part configuration diagram (part 3) of a thirteenth embodiment of the present invention;

FIG. 61 is a time chart of FIG. 60;

FIG. 62 is a diagram (part 1) of a main part configuration of a fourteenth embodiment of the present invention;

FIG. 63 is a time chart of FIG. 62.

FIG. 64 is a diagram (part 2) of an essential part of a fourteenth embodiment of the present invention;

FIG. 65 is a time chart of FIG. 64;

FIG. 66 is a configuration diagram of a main part of a conventional example.

FIG. 67 is a flowchart of FIG. 66.

[Explanation of symbols]

 31 FIFO 35 Enable generation unit 36 FIFO unit for additional data 41 Write control unit 42 Flag control 43 Read control unit 44 Master timing generation unit 101 Clock (CLK) disconnection detection unit 102 Data length monitoring unit 103 Parity check unit (write side) ) 104 Eigenpath filter unit 105 Eigenpath cycle monitoring unit 106 Monitoring data detection unit 107 OH data detection unit 108 Enable control unit 109 Quaternary counter 110 Comparison unit (write side) 111 Parity addition unit (write side) 112 53-base counter 114 Continuity check unit 115 Unique path latch 116 Differentiator 117 OH data monitor 118 Multiplexer 119 OH flag / trigger generator 120 OH flag controller 121 OH flag clear unit 122 Monitor data monitor 123 Rising edge detector 124 OR circuit 125 CRC addition unit 125a CRC generation unit 126 BIP2 addition unit 127 Initial control unit 128 Preprocessing result unit 129 Selector (writing side) 130 Timing generation unit 131 Adder 201 Parity check section (read side) 202 Check pattern insertion section 203 Parity generation section 204 Match detection section / match protection section 205 Switching control section 206 Selector monitoring section 208 OH data insertion section 209 Monitoring data insertion section 210 Parity addition section 211 Unique Path latch / prediction unit 212 Match comparison unit 214 Selector 215 Separation unit 216 OH data 4 times copy unit 217 OH data cycle generation unit 219 Serial number check unit 220 "1" count unit 221 CRC check unit 222 BIP2 check unit 223 Serial number comparison unit 224 27-ary counter 225 S / P converter 226 Latch 227 ternary counter 228 Encoder 229 Protector 411 230 AND gate 231 Master / timing generator 410 Surface switching counter 411 Start address generator 412 Surface counter (write side) 413 Write Enable generator 414 Write address generator 415 Write end flag / trigger generator 416 Write end flag Control unit 417 Decoder 418 Last address decoding unit 421 Flag generation unit 422 Flag control unit 423 Flag CLR / generation unit 431 Read start address generation unit 432 Surface counter (read side) 433 Read enable generation unit 434 Read address generation unit 437 Write end flag・ Clear generation unit 438 Common read address generation unit 439 Start address decode 440 Flag control generation / clear unit

Claims (14)

[Claims] 1. A system for performing pre-processing such as clock loss detection, data length monitoring, parity check, unique path signal monitoring, monitoring data detection, and overhead data detection on fixed-length data input from a transmission line. 1-system preprocessing means, 0-system where normal data is written / read,
A system 1 memory unit is provided. When a phase is compared between data read from the system 0 and system 1 memory units and a match is detected, instantaneous switching between system 0 data and system 1 data is performed. Then, in a redundant transmission line switching device that inserts and outputs monitoring data and the like, the above pre-processing can be performed in parallel, and only data for which all processing results are determined to be valid are written to the memory means. A redundant transmission line switching device, characterized in that it has a configuration. 2. Writing to the memory means is started before a result of determining whether the input data is valid is obtained. If the monitoring result is valid, the writing is completed.
A redundant transmission line switching device characterized in that it is configured to discard if invalid. 3. If overhead data can be detected from input data at the next overhead data prediction timing predicted by the overhead detection means using a detection output of a unique path signal period, the detected overhead data is determined to be valid. 2. The duplex transmission line switching device according to claim 1, wherein the duplex transmission line switching device is configured to perform the following. 4. A configuration in which the unique path signal monitoring means determines that the extracted unique path signal is valid when the timing of extracting the unique path signal of the own path from the input data matches the input data enable timing. 2. The duplex transmission line switching device according to claim 1, wherein: 5. When detecting / transferring overhead data in input data, the overhead data detecting means detects only the first overhead data of the multiplexed overhead data and monitors the period of the first overhead data. In the configuration in which the monitoring result obtained as described above is sent to the memory means as additional data, the overhead inserting means is used to generate multiplexed overhead data using head data of the overhead data read from the memory means, and 2. The duplex transmission line switching device according to claim 1, wherein the overhead data period used is generated to reproduce the overhead data and insert the data into the data read from the memory means. 6. When detecting / transferring overhead data in input data, the overhead data detecting unit sets an overhead flag when detecting overhead data and transfers the overhead data to a read-side overhead data inserting unit. 2. The duplex transmission path switching device according to claim 1, wherein said overhead data insertion means is configured to insert overhead data at a position of the overhead flag when the transferred overhead flag is detected. 7. When detecting / transferring overhead data in input data, the overhead detecting means is configured to, when overhead data is detected, insert an overhead detection bit into additional data and send it to the memory means. 2. The duplex transmission line switching device according to claim 1, wherein the overhead insertion unit is configured to read the overhead data and insert it into the data at the timing of the overhead detection bit read from the memory unit. 8. When detecting / transferring monitoring data in input data, the monitoring data monitoring means detects a rising point of a monitoring timing signal to be input, and inserts the detection result at the head of additional data to perform the detection. 2. The duplex transmission line switching device according to claim 1, wherein the monitoring data insertion means is configured to insert monitoring data at a rising point of a monitoring timing signal read from the memory means. 9. A method for writing / writing input data to / from said memory means.
At the time of reading, position information is added for each data, the added position information is written in the memory means, and the read order of data is checked using the read position information.
2. The duplex transmission line switching device according to claim 1, wherein a phase comparison of the data read using the system position information is performed. 10. Writing of input data to said memory means
/ When reading, add position information for each data, add error detection information to the added position information and data, write the position information and error detection information in 2. The redundant transmission line switching device according to claim 1, wherein a check of information and a cross check of positional information of system 0 and system 1 are performed. 11. When reading data from the 0-system and 1-system memory means, the reading side starts a count operation in synchronization with a system reference pulse and outputs a count value. A read counter is provided, and when the 0-system and 1-system memory means are in a readable state, the input count value of the common read counter is used as a read address, and a specific count value is used as an output for increasing the count value of the surface counter. 2. The duplex transmission path switching device according to claim 1, wherein the transmission is performed to each of the memory means. 12. When reading data from the memory means of the 0-system and the 1-system, a common read counter common to the 0-system and the 1-system and writing when the data enable input to the 0-system and the 1-system indicates valid. A flag control unit which sends an enable to the write side of the memory means and sends a read enable to the read side of the memory means when the final write address is input, but does not send a write enable when the input data enable indicates invalid. 2. The redundant transmission line switching device according to claim 1, wherein the system is provided separately for the system 0 and the system 1, and the writing / reading of data is controlled by the separately provided flag control unit. 13. When writing / reading data to / from one surface of a memory means composed of a plurality of surfaces, the writer adds surface information to be written next to the surface currently being written and data enable to the additional data. When the data enable is detected by reading the additional data and the data enable is detected, the read side continues reading the data written on the surface if the data enable is valid, and stops reading the data if the data enable is invalid. 2. The duplex transmission line switching device according to claim 1, wherein if the data enable sent by the additional data is valid, the data of the surface specified by the surface information whose reading has been stopped is read. 14. When writing / reading input data and additional data to / from a memory means, an additional data memory means is provided as a memory means in addition to the input data memory means.
When the next data is read from the input data memory means, the surface information and the validity / invalidity of the data to be read are written. When the next data is read from the input data memory means,
2. The duplex transmission path switching device according to claim 1, wherein access to the input data memory means is stopped when data to be read next is invalid.