JPH10143264A - Constant voltage circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit, of which output voltage is not changed even in the case of power supply voltage fluctuation, by extracting the output voltage from the node of a PMOS transistor and resistor at a voltage generating part. SOLUTION: A constant current generating part 21 for generating a reference current is composed of PMOS transistors 1, 2 and 8 consisting of a current mirror, NMOS transistors 3 and 4 commonly connecting their gates, a resistance 5, parasitic PNP transistors 6 and 7 having the emitter area ratio of N:1, and the voltage/current converting block 9. Besides, a voltage generating part 22 for generating a voltage is composed of a PMOS transistor 12 constituting the current mirror together with the PMOS transistors 1, 2 and 8 and outputting an X-fold current, a resistance 13, and a parasitic PNP transistor 14. Then, the output voltage is extracted from the node of the PMOS transistor 12 and the resistance 13. Thus, a stable voltage can be obtained with respect to any fluctuation at a power source 15 or temperature fluctuation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage circuit using a parasitic transistor generated in a CMOS structure formed on the same substrate.

[0002]

2. Description of the Related Art First, a CMO formed on the same substrate
A case where a P-type substrate is used for a parasitic transistor generated in the S structure will be described with reference to FIG. In a CMOS structure using a P-type substrate, a P ⁺ diffusion layer in a drain / source region of a PMOS transistor serves as an emitter and a PMOS transistor serves as a PMOS transistor.
A parasitic PNP transistor in which the N-Well layer of the transistor is the base and the P-type substrate is the collector is generated. This parasitic PNP transistor has a restriction that the collector is fixed to the lowest potential.

Next, as a configuration example of a conventional constant voltage circuit using a parasitic transistor, FIG. 8 shows a constant voltage circuit disclosed in Japanese Patent Application Laid-Open No. Hei 2-1509. In FIG. 8, reference numerals 1 and 2 denote PMOS transistors constituting a current mirror, and reference numerals 3 and 4 denote NMOs whose gates are connected in common.
S transistors, 5 and 13 are resistors, 6 and 7 are parasitic PNP transistors having an emitter area ratio of N: 1 (N is an arbitrary integer), and 12 constitutes a current mirror with the PMOS transistors 1 and 2 and generates an X-fold current. A PMOS transistor for outputting, 14 is a parasitic PNP transistor, 15 is a power supply, 16 is a ground potential, and 17 is a constant voltage output terminal. A block composed of components 1 to 7 includes a constant current generator 21 that generates a reference current I _REF, and a block composed of components 12 to 14 includes a voltage generator 22 that generates a voltage. Each is composed.

Next, the operation of the constant voltage circuit configured as described above will be described. Since the gates of the NMOS transistors 3 and 4 are commonly connected, the following equation (1) holds. Also, the base-emitter voltages V _{BE (6)} , V _{BE (7)} , N of the parasitic PNP transistors 6 and 7
Gate-source voltage V of MOS transistors 3 and 4
_{GS (3)} and V _{GS (4)} are given by the following equations (2), (3) and
(4), (5). The current flowing through the PMOS transistor ₁ to the NMOS transistor 3 to the resistor 5 to the parasitic PNP transistor 6 is represented by I _{DS (1)} , and the current flowing to the PMOS transistor 2 to the NMOS transistor 4 to the parasitic PNP transistor 7 is represented by I _{DS (2)} . R1 is the resistance value of the resistor 5, V _T is the thermal electromotive force, N represents the emitter area ratio of the parasitic PNP transistor 7 against parasitic PNP transistor 6, lambda is 0.03 V ^-1 ~ constant (typically representative of the channel length modulation effect of the MOS transistor 0.005 V ^-1 ), β / 2 is a constant determined by the manufacturing method and the gate size of the MOS, and V _th is the MO
It is assumed that the threshold value of the S transistor, I _S , represents the saturation current of the parasitic PNP transistor, respectively. V _{BE (6)} + I _{DS (1)} R1 + V _{GS (3)} = V _{BE (7)} + V _{GS (4)} (1) V _{BE (6)} = V _T ln (I _{DS (1)} / _{NI S) ············· (2) V} BE (7) = V T ln (I DS (2) / I S) ············・ ・ (3)

[0005]

(Equation 1)

[0006]

(Equation 2)

In the above equation (1), the above equations (2), (3),
By substituting the equations (4) and (5), the following equation (6) is obtained.

[0008]

(Equation 3)

Here, the PMOS transistors 1 and 2 and the NMOS transistors 3 and 4 are transistors having the same characteristics / size, and the source-drain voltages V _{DS (1)} , V _{DS (2)} , And the source-drain voltage V _{DS (3) of} the NMOS transistors 3 and 4,
Assuming that V _{DS (4)} is substantially equal, since the PMOS transistors 1 and 2 are current mirror connected, PM
The drain currents I _{DS (1)} , I of the OS transistors 1 and 2
_{DS (2)} has the same value. Therefore, this is referred to as reference current I
_{If REF} , the following equation (7) holds. I _REF = I _{DS (1)} = I _{DS (2)} (7) Therefore, the above equation (6) is expressed as the following equation (8). I _REF = V _T lnN / R1 (8) At this time, the reference current I _REF is supplied to the PMOS transistor 12.
To flow X times the current of the temperature dependency ∂V _OUT / ∂T the output voltage V _OUT and V _OUT are the following equations (9),
It is represented by (10). V _OUT = (X × R2) / R1 · V _T lnN + V _{BE (14)} (9) ∂V _OUT / ∂T = (X × R2) / R1 · lnN · ∂V _T / ∂T + ∂V _{BE (14)} / ∂T (10) where R2 is the resistance value of the resistor 13, and V _{BE (14)} is the base-emitter voltage of the parasitic PNP transistor 14. ing.
Here, the temperature dependence of the first and second terms on the right side of the above equation (10) is expressed by the following equations (11) and (12). ∂V _T /∂T=0.085 mV / deg. (11) ∂V _{BE (14)} / ∂T = -2 mV / deg. (12) Therefore, R1 and R1 are set so as to satisfy the following expression (13).
By setting 2, N, an output voltage V _OUT having no temperature dependency can be obtained. (X × R2) / R1 · lnN = (2 mV / deg.) / (0.085 mV / deg.) ≒ 23.53 (13)

[0010]

However, the constant voltage circuit shown in FIG.
Since the source-drain voltage V _{DS (2) of the} S transistor 2 depends on the power supply 15, when the power supply 15 increases, the source-drain voltage V _{DS ( 1)} and the PMO expressed by the following equation (15)
Source-drain voltage V of S transistor 2
_The difference ΔV _{DS (PMOS) of DS (2)} expressed by the following equation (16) increases. V _{DS (1)} = V _{GS (1)} (14) V _{DS (2)} = V _DD − (V _{BE (7 )} + _{VGS (4)} ) (15) ΔVDS _(PMOS) = _{VDS (2)} −VDS ₍₁₎ = _VDD− ( _{VBE (7)} + V _{GS (4)} )-V _{GS (1)}・ ・ ・ ・ ・ ・ ・ (16)

Then, the drain current I _{DS (2) of the} PMOS transistor 2 becomes larger than the drain current I _{DS (1)} of the PMOS transistor 1 due to the channel length modulation effect. At this time, as shown in the following equation (17), I _{DS (1)}
Assuming that = I _REF , I _{DS (2)} becomes the following equation (18). I _{DS (1)} = β / 2 · (V _{GS (1)} −V _th ) ² (1 + λV _{DS (1)} ) = I _REF (17) I _{DS (2)} = β / 2 · (V _{GS (1)} −V _th ) ² [1 + λ (V _{DS (1)} + ΔV _{DS (PMOS)} )] = β / 2 · (V _{GS (1)} −V _th ) ² (1 + λV _{DS (1)} ) + Β / 2 · (V _{GS (1)} −V _th ) ² (λΔV _{DS (PMOS)} ) = I _REF + α (18) where α = β / 2 (V _{GS ( 1)} −V _th ) ² (λΔV
_{DS (PMOS)} ).

Also, since the drain current I _REF of the PMOS transistor 1 flows through the NMOS transistor 3 and the drain current (I _REF + α) of the PMOS transistor 2 flows through the NMOS transistor 4, the drain current of the NMOS transistor 3 <the drain current of the NMOS transistor 4. It becomes the drain current. Further, since the drain-source voltage V _{DS (3) of} the NMOS transistor 3 has a power supply dependency as shown in the following equation (19), when the voltage V _{DD of the} power supply 15 increases, the source-source voltage of the NMOS transistor 3 increases. The drain voltage V _{DS (3)} and the NMOS transistor 4 expressed by the following equation (20)
, The difference ΔV _{DS (NMOS)} of the source-drain voltage V _{DS (4)} expressed by the following equation (21) increases. V _{DS (3)} = V _DD -V _{GS (1)} -(V _{BE (6)} + R1I _REF ) (19) V _{DS (4)} = V _{GS (4)} ... (20) ΔV _{DS (NMOS)} = V _{DS (3)} −V _{DS (4)} = V _DD −V _{GS (1)} − (V _{BE ( 6)} + R1I _REF ) -V _{GS (4)} (21)

From the above equations (4) and (5), the gate-source voltage of the MOS transistor increases as the drain current I _DS increases and as 1 / V _DS increases (as V _DS decreases). Become. Therefore, if the power supply 15 becomes large, I _{DS (1)} <
Since I _{DS (2)} and V _{DS (3)} > V _{DS (4)} from the above equation (21), the gate-source voltage of the NMOS transistor 4 is larger than the gate-source voltage V _{GS (3) of the} NMOS transistor _3.
The source-to-source voltage V _{GS (4)} increases, and the difference ΔV _{GS (NMOS)} between the source-gate voltages of the NMOS transistors 3 and 4 is expressed by the following equation (22).

[0014]

(Equation 4)

Note that V _{DS (3)} > V _{DS (4)} , I _REF + α>
From I _REF , the difference ΔV _{GS (NMOS)} between the source-gate voltages of the NMOS transistors 3 and 4 is positive. Therefore, the power supply
In consideration of the case where 15 has increased, the above equation (1) can be arranged as the following equation (23). I _REF R1 = V _T ln ｛N (I _REF + α) / I _REF ｝ + (V _{GS (4)} −V _{GS (3)} ) = V _T ln ｛N (I _REF + α) / I _REF ｝ + ΔV _{GS (} ( _NMOS) (23) Here, α includes power supply-dependent ΔV _{DS (PMOS)} . Therefore, when the power supply 15 increases, the first value on the right side of the above equation (23) becomes The term increases (see the above equations (14) to (18)). Furthermore, ΔV _{GS (NMOS)} has α and ΔV
_{Since DS (NMOS)} is included, if the power supply 15 becomes large,
The second term on the right side of the above equation (23) also increases (from the above (19) to
(See equation (22)). Therefore, the current I _REF generated by the constant current generator 21 has a power supply voltage dependency that the power supply 15 increases as the power supply 15 increases, and the output voltage V _OUT also varies depending on the power supply 15.

As described above, the conventionally proposed constant voltage circuit does not consider the effect of the output voltage on the fluctuation of the power supply. The present invention has been made in view of this point, and has as its object to provide a constant voltage circuit in which the output voltage does not change even when the power supply voltage changes.

[0017]

In order to solve the above-mentioned problems, the invention according to claim 1 is directed to a CM formed on the same substrate.
In a constant voltage circuit configured using a parasitic transistor generated in an OS structure, a first and second first conductivity type MOS transistors having a source connected to a first power supply and a gate connected in common, and a drain. A first second conductivity type MOS transistor having a gate connected to the drain of the first first conductivity type MOS transistor; a drain connected to the drain of the second first conductivity type MOS transistor; A second second conductivity type MOS transistor connected to the gate of the second conductivity type MOS transistor, a first resistor connected at one end to the source of the first second conductivity type MOS transistor, and an emitter The first
A first parasitic transistor connected to the other end of the first resistor and having a base and a collector connected to a second power supply, and an emitter area of which is one of an emitter area of the first parasitic transistor.
/ N (N is an arbitrary integer), a second parasitic transistor whose emitter is connected to the source of the second MOS transistor of the second conductivity type and whose base and collector are connected to the second power supply, and whose source is the second. A third first-conductivity-type MOS transistor having a gate and a drain connected to the gate of the first first-conductivity-type MOS transistor, and an input terminal connected to the second first-conductivity-type MOS transistor. The output terminal of the transistor is connected to the third first conductivity type MO.
A voltage-current conversion block connected to the drain of the S transistor and outputting a current corresponding to a difference voltage between the input terminal and the second power supply; a source connected to the first power supply and a gate connected to the first first conductive layer A fourth first conductivity type MOS transistor connected to the gate of the type MOS transistor;
A second resistor having one end connected to the drain of the fourth first conductivity type MOS transistor, a second resistor having an emitter connected to the other end of the second resistor, and a base and a collector connected to a second power supply. And a third parasitic transistor.
The output voltage is extracted from the connection point between the first conductivity type MOS transistor and the second resistor.

In the constant voltage circuit thus configured, the gate is common and the drains are the first and second.
The source and drain voltages of the first and second first conductivity type MOS transistors connected to the second conductivity type MOS transistor, the drain potential of the first and second first conductivity type MOS transistors depends on the power supply. Since the configuration does not have the characteristic, even if the power supply voltage fluctuates, there is no difference between the source-drain voltages of the first and second first conductivity type MOS transistors, and the first and second first MOS transistors are not changed. The current flowing through the one conductivity type MOS transistor has a constant value. Therefore,
X of the current flowing through the first first conductivity type MOS transistor
The output voltage using the double current also becomes a constant value independent of the power supply voltage. Further, in the present invention, even when the temperature is changed, there is almost no difference between the source-drain voltages of the first and second first conductivity type MOS transistors connected in a current mirror, so that the voltage is stable over a wide temperature range. Output voltage can be obtained.

According to a second aspect of the present invention, in the constant voltage circuit according to the first aspect, the voltage-current conversion block includes a second conductivity type MOS transistor.
The gate and drain of the transistor are used as an input terminal and an output terminal, respectively, and the source is connected to a second power supply. Thus, the voltage-current conversion block is connected to the second conductivity type M
By using only OS transistors, a very simple circuit can be obtained. Therefore, a stable output voltage can be obtained without increasing the circuit scale.

According to a third aspect of the present invention, in the constant voltage circuit according to the first aspect, the voltage-current conversion block includes a second conductivity type MOS transistor and a parasitic transistor, and a gate of the second conductivity type MOS transistor. And a drain, respectively, as an input terminal and an output terminal, a source is connected to an emitter of the parasitic transistor, and a base and a collector of the parasitic transistor are connected to a second power supply. Thus, the voltage-current conversion block is connected to the second conductivity type M
By using an OS transistor and a parasitic transistor, a very simple circuit can be obtained. In addition, the temperature dependence of the drain potential of the first second conductivity type MOS transistor and the drain potential of the second second conductivity type MOS transistor can be improved. Temperature dependence becomes equal, and therefore, a very stable output voltage can be obtained in a wide temperature range without increasing the circuit scale.

According to a fourth aspect of the present invention, in the constant voltage circuit according to the first aspect, the voltage-current conversion block includes a second conductivity type MOS transistor and a resistor, and a gate of the second conductivity type MOS transistor is connected to the gate. The drain is an input terminal and an output terminal, respectively, and the source is connected to a second power supply via the resistor. In this way, by configuring the voltage-current conversion block with the second conductivity type MOS transistor and the resistor, a very simple circuit is obtained, and a gate potential of the second conductivity type MOS transistor which obtains a stable output voltage is obtained. The condition for equalizing the gate potential of the first second conductivity type MOS transistor can be easily set, so that the condition for obtaining a stable output voltage can be easily set without increasing the circuit scale. it can.

[0022]

Next, an embodiment will be described. FIG. 1 is a circuit configuration diagram showing a first embodiment of a constant voltage circuit according to the present invention. Components corresponding to those of the conventional example shown in FIG. 8 are denoted by the same reference numerals. In FIG. 1, PMOS transistors 1, 2 and 8 constitute a current mirror.
Transistors 3 and 4 have NMOs whose gates are connected in common.
S transistors, 5 and 13 are resistors, 6 and 7 are parasitic PNP transistors having an emitter area ratio of N: 1, 9 is a voltage-current conversion block, 10 and 11 are input and output terminals of the voltage-current conversion block, and 12 is a PMOS. PMOS that forms a current mirror with transistors 1, 2 and 8 and outputs X times the current
A transistor, 14 is a parasitic PNP transistor, 15 is a power supply, 16 is a ground potential, and 17 is an output terminal. And 1 to
9 constitutes a constant current generating section 21 for generating a reference current I _REF , and the components indicated by 12 to 14
It constitutes a voltage generator for generating a voltage. The voltage-current conversion block 9 outputs a current corresponding to the difference voltage between the input terminal 10 and the ground potential 16.
The larger the difference voltage of 16, the more current is drawn.

Next, the operation of the first embodiment configured as described above will be described. The constant current generator 21
As in the case of the conventional example shown in FIG.
The condition that satisfies the expression and the expression (6) obtained by substituting the expressions (2) to (5) into the expression is a stable point. V _{BE (6)} + I _{DS (1)} R1 + V _{GS (3)} = V _{BE (7)} + V _{GS (4)} ... (1)

[0024]

(Equation 5)

Here, the input terminal of the voltage / current conversion block 9
Potential V of child 10_{G (10)}Is the gate of the NMOS transistor 3.
Potential V_{G (3)}Is set to be equal to
Source-drain voltage of transistors 1 and 2
V_{DS (1)}, V_{DS (2)}Are equal, the PMOS transistor
Drain current I of transistors 1 and 2_{DS (1)}, I_{DS (2)}Equal
K (I _{DS (1)}= I_{DS (2)})Become. In addition, NMOS transistors
Source-drain voltage V of transistors 3 and 4_{DS (3)}, V
_{DS (4)}Is also equal (V_{DS (3)}= V_{DS (4)})Become. Accordingly
The reference current I generated by the constant current generator 21_REFFIG. 8
Similarly to the conventional example shown in FIG.
It will be. I_REF= V_TlnN / R1 (8)

When the current of the constant current generator 21 becomes larger than the stable point current I _REF , feedback is performed as shown below, and the stable point is settled. When the drain currents I _{DS (1)} and I _{DS (2) of the} PMOS transistors 1 and 2 increase to I _REF + ΔI, the gate potential VG _{(3) of the} NMOS transistor 3 and NM
The gate potential VG _{(4) of the} OS transistor 4 rises, and the drain current I _{DS (4) of the} NMOS transistor 4 becomes I
_REF + ΔI + γ (NMOS transistors 4 to
The current change in the line of the parasitic PNP transistor 7 is NM
It becomes larger than the current change in the line of the OS transistor 3 to the resistor 5 to the parasitic PNP transistor 6). I _{DS (2)} = I _REF + ΔI <I _{DS (4)} = I _REF + ΔI +
From γ, the drain potential V _{D (4) of the} NMOS transistor 4
(Accordingly, the potential VG ₍₁₀₎ of the input terminal 10 of the voltage-current conversion block 9 also decreases). Thereby, the output current I of the voltage / current conversion block 9
_{D (9)} decreases. Therefore, the drain currents I _{DS (1)} and I _{DS (2) of} the PMOS transistors 1 and ₂ decrease.

Even if the power supply 15 rises, PM
Source-drain voltage V of OS transistors 1 and 2
_{Since DS (1)} and V _{DS (2)} are equal, the drain currents I _{DS (1)} and I _{DS (2)} of the PMOS transistors 1 and ₂ are equal (I
_{DS (1)} = I _{DS (2)} . Further, since the source-drain voltages V _{DS (3)} and V _{DS (4)} of the NMOS transistors 3 and 4 have no power supply voltage dependency, they have a constant value regardless of the power supply 15. Therefore, the reference current I _REF generated by the constant current generator 21 is constant even if the power supply 15 changes.

If the temperature dependence of the gate potential V _{G (3)} of the NMOS transistor 3 is made equal to the temperature dependence of the input terminal 10 of the voltage-current conversion block 9, the PMOS transistors 1 and 2 will not be affected even if the temperature fluctuates. Source-drain voltages V _{DS (1)} , V _{DS (2)} , and NMOS transistors 3,
No difference voltage occurs between the source-drain voltages V _{DS (3)} and V _{DS (4)} of No. ₄ and the reference current I _REF does not change.

Therefore, a current X times the reference current I _REF flows through the PMOS transistor 12, so that the output voltage V
The temperature dependence of _OUT and V _OUT is expressed by the following equations (9) and (10). V _OUT = (X × R2) / R1 · V _T lnN + V _{BE (14)} (9) ∂V _OUT / ∂T = (X × R2) / R1 · lnN · ∂V _T / ∂T + ∂V _{BE (14)} / ∂T (10) Here, the temperature dependence of the first and second terms on the right side of the above equation (10) is shown again below ( It is expressed as in equations (11) and (12). ∂V _T /∂T=0.085 mV / deg. (11) ∂V _{BE (14)} / ∂T = -2 mV / deg. (12) Therefore, by setting R1, R2, and N so as to satisfy the following expression (13), an output voltage _VOUT having no temperature dependency can be obtained. (X × R2) / R1 · lnN = (2 mV / deg.) / (0.085 mV / deg.) ≒ 23.53 (13)

As described above, according to the present embodiment, it is possible to obtain a voltage that is very stable against fluctuations in the power supply 15 and fluctuations in temperature. Further, it has an advantage that it can be easily integrated with a processing unit such as a CPU, which is advantageous for cost reduction.

Next, a second embodiment will be described with reference to FIG. In this embodiment, the voltage-current conversion block 9 in the first embodiment shown in FIG.
The NMOS transistor 18 is configured by connecting the gate to the input terminal, the drain to the output terminal, and the source to the ground potential 16, and the other configuration is the same as that of the first embodiment. The operation is the same as that of the first embodiment.

In the second embodiment, the temperature dependence of the gate potential VG ₍₃₎ of the NMOS transistor 3 and the NMOS
The temperature dependence of the gate potential VG ₍₁₈₎ of the transistor 18 differs, and the source-drain voltages _{VDS (1)} , _{VDS (2)} , and NM of the PMOS transistors 1 and 2 vary depending on the temperature.
Source-drain voltage V of OS transistors 3 and 4
_A difference may occur between _{DS (3)} and _{VDS (4)} , and the balance may be lost. However, the generated difference voltage is about several hundred mV, and the source-drain voltages V _{DS (1)} and V _{DS (2) of} the PMOS transistors 1 and 2 and the source-drain voltage V _DS of the NMOS transistors 3 and 4 are different. _{DS (3)} , V _{DS (4)}
The change of the reference current I _REF due to the difference voltage ΔV _{DS (PMOS)} and ΔV _{DS (NMOS)} generated at the time is very small. Therefore, according to the present embodiment, the voltage-current conversion block is
Since it is composed only of transistors, a stable output voltage can be obtained without increasing the circuit scale.

Next, a third embodiment will be described with reference to FIG. In this embodiment, the voltage-current conversion block 9 in the first embodiment shown in FIG.
A transistor comprising a transistor 18 and a parasitic PNP transistor 19, wherein the gate of the NMOS transistor 18 is an input terminal, the drain is an output terminal, and the source is connected to the ground potential 16 via the diode-connected parasitic PNP transistor 19. The other configuration is the same as that of the first embodiment, and the operation is the same as that of the first embodiment.

In the third embodiment, the reference current I
_REF is not affected by the power supply 15 and of course, even when the temperature fluctuates, the gate potential V
The temperature dependence of _{G (3)} and the gate potential VG ₍₁₈₎ of the NMOS transistor 18 are the same, and the source-drain voltages V _{DS (1)} and V _{DS (1)} of the PMOS transistors 1 and 2 are the same.
_{Since DS (2)} and the source-drain voltages V _{DS (3)} and V _{DS (4 )} of the NMOS transistors 3 and 4 become equal, the difference voltages ΔV _{DS (PMOS)} and ΔV _{DS ( NMOS)}
Does not occur, intrinsic temperature dependence (temperature dependence of the resistance 5 and V _T) than the impact is not subjected.

Therefore, according to the present embodiment, the voltage-current conversion block includes the NMOS transistor and the parasitic PNP.
Since it is composed of transistors, it is possible to obtain a voltage that is very stable against power supply fluctuations and temperature fluctuations without increasing the circuit scale.

Next, a fourth embodiment will be described with reference to FIG. In this embodiment, the voltage-current conversion block 9 in the first embodiment shown in FIG.
It is composed of a transistor 18 and a resistor 20, with the gate of the NMOS transistor 18 as an input terminal and the drain as an output terminal,
The configuration is such that the source is connected to the ground potential 16 via the resistor 20, and the other configuration is the same as that of the first embodiment, and the operation is also the same as that of the first embodiment.

In the fourth embodiment, the condition for obtaining a stable output voltage by changing the value of the resistor 20, that is, the gate potential of the NMOS transistor 18 and the NMOS
The condition for making the gate potential of the transistor 3 equal can easily be set. Therefore, according to the present embodiment, since the voltage-current conversion block is composed of the NMOS transistor and the resistor, it is possible to easily set conditions for obtaining a stable output voltage.

This embodiment can be variously modified and changed. For example, as shown in FIG.
A capacitor 23 for stabilizing the circuit operation can be connected between the gate and the drain of the transistor 4. Or PMOS
The current mirror constituted by the transistors 1, 2, 8, and 12 can be constituted by a cascode type or a Wilson type.

Next, a description will be given of a fifth embodiment in which the constant voltage circuit according to the present invention is configured using an N-type substrate. In a CMOS structure using an N-type substrate, as shown in FIG. 5, an N ⁺ diffusion layer in a drain / source region of an NMOS transistor serves as an emitter and a P +
A parasitic NPN transistor having a Well layer as a base and an N-type substrate as a collector occurs. This parasitic NPN transistor has a restriction that the collector is fixed to the power supply.

Next, a fifth embodiment will be schematically described with reference to FIG. 31, 32 and 38 are NMOS transistors constituting a current mirror, 33 and 34 are PMOS transistors whose gates are connected in common, 35 and 43 are resistors, 36 and 37
Is a parasitic NPN transistor having an emitter area ratio of N: 1,
39 is a voltage-to-current conversion block, 40 and 41 are input and output terminals of the voltage-to-current conversion block 39, 42 is an NMOS transistor that forms a current mirror with the NMOS transistors 31, 32, and 38 and outputs X times the current, and 44 is A parasitic NPN transistor, 45 is a power supply, 46 is a ground potential, and 47 is an output terminal. The components indicated by 31 to 39 are the reference current I _REF
, And the components indicated by reference numerals 42 to 44 constitute a voltage generator that generates a voltage. Here, the voltage-current conversion block 39 outputs a current corresponding to the difference voltage between the input terminal 40 and the power supply 45, and is configured to flow out more current as the difference voltage between the input terminal 40 and the power supply 45 increases. ing. In the case of a constant voltage circuit configured using an N-type substrate, a constant voltage is generated between the power supply 45 and the output terminal 47.

[0041]

As described above with reference to the embodiments, according to the first aspect of the present invention, a constant voltage circuit which can obtain a stable output voltage over a wide temperature range without depending on a power supply voltage. Can be realized. According to the second aspect of the present invention, a stable output voltage can be obtained with a very simple circuit, and according to the third aspect of the present invention,
A stable output voltage can be obtained over a wide temperature range without increasing the circuit scale, and according to the invention as set forth in claim 4, conditions for obtaining a stable output voltage without increasing the circuit scale can be set. It can be done easily.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a constant voltage circuit according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit configuration diagram showing a fourth embodiment of the present invention.

FIG. 5 is a schematic sectional view showing a CMOS structure using an N-type substrate.

FIG. 6 is a circuit configuration diagram showing a fifth embodiment of the present invention.

FIG. 7 is a schematic sectional view showing a CMOS structure using a P-type substrate.

FIG. 8 is a circuit configuration diagram showing a configuration example of a conventional constant voltage circuit.

[Explanation of symbols]

 1,2,8,12,33,34 PMOS transistor 3,4,18,31,32,38,42 NMOS transistor 5,13,35,43 Resistance 6,7,14 Parasitic PNP transistor 9,39 Voltage-current conversion Block 10, 40 Input terminal 11, 41 Output terminal 15, 45 Power supply 16, 46 Ground potential 17, 47 Output terminal 21, 51 Constant current generator 22, 52 Voltage generator 36, 37, 44 Parasitic NPN transistor

Claims (4)

[Claims] 1. A constant voltage circuit using a parasitic transistor generated in a CMOS structure formed on the same substrate, wherein a first power source is connected to a first power supply and a gate is commonly connected. 2 of the first conductivity type MOS transistor, and the drain and the gate thereof are of the first first conductivity type M.
A first second conductivity type MOS transistor connected to the drain of the OS transistor; and a drain connected to the second first type MOS transistor.
A second second conductivity type MOS transistor having a gate connected to the drain of the first conductivity type MOS transistor and a source connected to one end of the first second conductivity type MOS transistor; , A first parasitic transistor having an emitter connected to the other end of the first resistor, a base and a collector connected to a second power supply, and an emitter having an area equal to the first resistor.
The emitter is connected to the source of the second second conductivity type MOS transistor and the base and the collector are connected to the second power supply at 1 / N (N is an arbitrary integer) of the emitter area of the parasitic transistor. And a source connected to the first power supply, and a gate and a drain connected to the first power supply.
A third first conductivity type MOS transistor connected to the gate of the first conductivity type MOS transistor, an input terminal connected to the drain of the second first conductivity type MOS transistor, and an output terminal connected to the third first MOS transistor. A voltage-current conversion block connected to the drain of the conductivity type MOS transistor and outputting a current corresponding to a difference voltage between the input terminal and the second power supply; a source connected to the first power supply and a gate connected to the first power supply; A fourth first conductivity type MOS transistor connected to the gate of the one conductivity type MOS transistor;
A second resistor connected to the drain of the first conductivity type MOS transistor, a third resistor having an emitter connected to the other end of the second resistor, and a base and a collector connected to a second power supply.
And the fourth first conductivity type M
A constant voltage circuit configured to extract an output voltage from a connection point between an OS transistor and a second resistor. 2. The voltage-current conversion block comprises a second conductivity type MOS transistor. The gate and the drain of the second conductivity type MOS transistor have an input terminal and an output terminal, respectively, and a source is connected to a second power supply. The constant voltage circuit according to claim 1, wherein 3. The voltage-current conversion block includes a second conductivity type MOS transistor and a parasitic transistor.
The second conductive type MOS transistor has a gate and a drain as input and output terminals, respectively, a source connected to the emitter of the parasitic transistor, and a base and a collector of the parasitic transistor connected to a second power supply. 2. The constant voltage circuit according to claim 1, wherein: 4. The voltage-current conversion block includes a second conductivity type MOS transistor and a resistor. The second conductivity type MOS transistor has a gate and a drain as input and output terminals, respectively, and a source via the resistor. Second
2. The constant voltage circuit according to claim 1, wherein the constant voltage circuit is connected to a power supply.