JPH10144902A - Solid-state imaging device - Google Patents

Abstract

[PROBLEMS] To reduce the linearity of sensitivity when signal charge in an amplification type solid-state imaging device is small, and to suppress fixed pattern noise due to its variation. A light-receiving element having a function of performing photoelectric conversion by incident light, accumulating signal charges obtained by the photoelectric conversion, and outputting a signal voltage in accordance with the amount of the accumulated signal charges is provided on the same substrate. , A channel length at the center of the pixel gate 30 for controlling the operation of the light receiving element 41 is shorter than that of the other parts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, in particular, to perform photoelectric conversion by incident light, accumulate signal charges obtained by the photoelectric conversion, and output a signal voltage according to the amount of the accumulated signal charges. The present invention relates to an amplification-type solid-state imaging device including pixels (light-receiving elements) having a function of performing the same. More specifically, the present invention relates to a sensitivity linearity of a pixel output at low illuminance (a small signal) and an improvement of fixed pattern noise due to a variation in the sensitivity linearity in the amplification type solid-state imaging device.

[0002]

2. Description of the Related Art A function of performing photoelectric conversion by incident light, storing signal charges obtained by the photoelectric conversion, and outputting a signal voltage in accordance with the amount of the stored signal charges. 2. Description of the Related Art An amplification type solid-state imaging device having a pixel structure having a combination is known.

In a conventional amplification type solid-state image pickup device, for example, in an amplification type solid-state image pickup device in which a pixel is constituted by a MOS transistor having a ring-shaped gate, the surface potential of the ring gate is affected by the interface state and impurity concentration. If it is partially or locally changed due to uniformity, the source-
Pixels having a non-uniform interface state or impurity concentration because a surface channel through which a drain current (a so-called channel current) flows partially conducts, and signal charges are easily accumulated in a portion different from the conducting channel. In particular, the sensitivity characteristics of pixels that are not so differ from each other especially when the signal charge amount is small (ie, at low illuminance).

For example, the incident light quantity versus signal output characteristic of a pixel having a uniform interface state and impurity concentration is as large as when the signal charge is small even when the signal charge is small. And pixels with non-uniform impurity concentrations,
When the signal charge is small, the accumulated signal charge is partially collected, so that the degree of modulation applied to the part where the channel is conductive is small, and the slope of the low illuminance output with little signal charge is low. It will be smaller.

As a result, the linearity of the incident light quantity versus signal output characteristic at low illuminance is deteriorated, and the sensitivity unevenness due to the non-uniformity of the linearity of each pixel at low illuminance,
This causes so-called fixed pattern noise.

This situation will be further described in detail with reference to the drawings. First, the photoelectric conversion, signal charge accumulation, and charge-
For an amplifying solid-state imaging device having a pixel structure that also has a voltage conversion function, the basic operation of what principle the pixel outputs a signal will be described with reference to FIG. The figure will be described with reference to FIG.

The pixel 1 shown in FIG. 11 is composed of a MOS transistor. A source region 2 is formed at the center of the pixel. A gate electrode 3 is formed in a ring shape around the source region 2 via a gate insulating film. The drain region 4 is formed on the outer periphery of the drain region 4 and also serves as an element isolation between pixels. In the example of the pixel 1, the n-channel MO
Based on an S transistor, a source region 2 and a drain region 4 are formed of n ⁺ diffusion regions, and a gate electrode 3
A p-type semiconductor region 5 is formed underneath such that signal charges (that is, holes) 8 can be accumulated, and an overflow barrier region formed on the p-type silicon semiconductor substrate 7 as a whole pixel,
That is, it is formed on the n-type semiconductor well region 6 which serves as an overflow barrier region for determining the amount of signal charge and overflowing excess charge.

The ring-shaped gate electrode 3 is formed of, for example, a thin polycrystalline silicon layer through which light can pass. When light passes through the gate electrode 3 and enters the p-type semiconductor region 5 below the gate electrode 3, signal charges (holes in this example) 8 due to photoelectric conversion are generated and accumulated in the p-type semiconductor region 5. .

The signal charge (hole) 8 changes (modulates) the potential of the surface channel 9 of the pixel in accordance with the amount thereof, so that the drain region 4 is connected to a power supply and the source region 2 is connected to a constant voltage source. Then, when the source-drain current changes, or when the source region 2 is connected to a constant current source,
The source voltage changes, and in either case, a current or voltage signal output is obtained from the source region 2. Reference numeral 10 denotes a signal line connected to the source region 2. The above is the basic operation of the pixel structure having the functions of photoelectric conversion, signal charge accumulation, and charge-voltage conversion.

In the conventional example, in an amplifying solid-state image pickup device having a pixel structure having functions of photoelectric conversion, signal charge accumulation, and charge-voltage conversion, a signal charge of the pixel is accumulated and converted into a signal voltage. If the gate electrode is wide
Or a MOS whose gate electrode is formed in a ring shape
In the case of the pixel type pixel structure (example of FIG. 11), if the potential under the gate electrode is uniform along the circumference,
As shown in A, the signal charge 8 due to the incident light is uniformly distributed (accumulated) along the circumference below the ring-shaped gate electrode 3, and the channel current 11 as a signal output from the source region 2 is also uniformly distributed around the circumference. .

As a result, the signal charge 8 uniformly modulates the surface channel of the pixel, and the signal output is output according to the amount of the signal charge 8 stored in the pixel.

However, as shown in FIG. 12B, when the interface state on the channel surface, the fixed charge in the gate insulating film (eg, oxide film) and the impurity concentration in the semiconductor are not locally uniform, If the potential is not uniform along the circumference, for example, the potential at the point B is high and the potential at the remaining portion (point A) is low, the signal charge (hole) 8 is other than the point B while the signal charge is small. And the channel current 11 flows only to the point B portion.

Then, the small signal charge 8 is changed to the point B
The effect of modulating the channel current that flows intensively is small. If the signal charge is small, the signal output is small, that is, the sensitivity is low.

To explain this phenomenon, FIG.
FIG. 13 shows a one-dimensional potential distribution in the vertical direction below the gate electrode 3 at point A and point B. Due to the non-uniformity of the interface state between the gate insulating film and the semiconductor, the fixed charge in the gate insulating film, and the impurity concentration in the semiconductor, the respective surface channel potentials (φ ^A _CH , φ ^B _CH), and the potential accumulated in part of the signal charges _{^{8 (φ a SN, φ B}} SN) is 13
When the relationship of φ ^A _CH <φ ^B _CH φ ^A _SN <φ ^B _SN is satisfied, the small signal charge 8 is accumulated in a portion other than the point B, and the channel current 11 Flows intensively.

In other words, it means that the place where the small amount of signal charge 8 is stored and the place where the channel current 11 flows are two-dimensionally separated, and the degree to which the signal charge modulates the channel current 11 becomes small.

For these reasons, as shown in FIG.
When the potential is uniform in the circumferential direction of the ring-shaped gate electrode 3 and when the potential is non-uniform as shown in FIG. 12B, the characteristics of the accumulated signal charge amount and signal output are as shown in FIG. Is shown.

In FIG. 14, in the case of a pixel having a uniform potential shown in FIG. 12A, the signal output rises linearly from a portion where the accumulated charge amount is small (see graph I), whereas the potential shown in FIG. In the case of a pixel having a small amount of accumulated charge, the signal output rises slowly at 13 where the accumulated charge amount is small, and the linearity is poor (see graph II).

As a result, in an image pickup device in which pixels are arranged one-dimensionally or two-dimensionally, pixels as shown in FIGS. 12A and 12B are randomly arranged with different degrees of non-uniformity. In a state where the accumulated charge amount is small, that is, in a state of low illuminance, fixed pattern noise appears strongly.

In view of the above, the present invention has a function of performing photoelectric conversion with incident light, storing signal charges obtained by photoelectric conversion, and outputting a signal voltage according to the amount of the stored signal charges. Amplification type solid-state imaging device composed of pixels that have combined pixels, improved solid-state imaging at low illuminance, that is, fixed signal noise due to pixel signal sensitivity linearity degradation and sensitivity linearity variation at small signals An element is provided.

[0020]

According to the present invention, there is provided a solid-state imaging device including a light receiving element having functions of photoelectric conversion, signal charge accumulation, and outputting a signal voltage in accordance with a signal charge amount.
It has an element isolation electrode for electrically separating adjacent light receiving elements, and has a configuration in which the channel length at the center of the pixel gate for controlling the operation of the light receiving element is shorter than that of other parts.

According to this structure, the adjacent light receiving elements, that is, the pixels are electrically separated by the element isolation electrode (that is, the element isolation region of the MOS structure), so that the light receiving element can be planarized by the narrow channel effect by the element isolation electrode. In view of this, the portion where the signal charge is easily accumulated and the portion where the surface channel current easily flows are at the same position without being separated. That is, the surface channel current and the signal charge storage portion can be brought closer to the center of the pixel gate of the light receiving element. Further, the surface channel current can be more concentrated on the central portion of the pixel gate by making the channel length of the central portion of the pixel gate for controlling the operation of the light receiving element shorter than that of the other portion. Therefore, even when the signal charge is small, the linearity of the incident light amount versus the signal output characteristic is improved, and the generation of fixed pattern noise due to the variation in linearity between pixels can be controlled.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A solid-state imaging device according to the present invention performs photoelectric conversion by incident light, accumulates signal charges obtained by the photoelectric conversion, and outputs a signal voltage according to the amount of the accumulated signal charges. A solid-state imaging device in which a plurality of light-receiving elements having the same function as one another are arranged on the same substrate, and have element separation electrodes for electrically separating adjacent light-receiving elements, and control the operation of the light-receiving elements. The channel length at the center of the pixel gate to be formed is shorter than that at the other portion.

According to the present invention, in the solid-state imaging device, the channel length of the pixel gate is gradually increased from the center of the channel toward the end.

An embodiment of the present invention will be described below with reference to the drawings.

The solid-state image pickup device according to the present embodiment, that is, the amplification type solid-state image pickup device has a portion in which signal charges are accumulated and a surface channel current in response to non-uniformity of potential in the pixel as described above. It has a new pixel structure that suppresses linearity degradation and fixed pattern noise by keeping the flowing part from separating, and in particular, uses an element isolation gate that applies a MOS structure gate to element isolation between adjacent pixels. The configuration is fundamental.

First, the basic structure of an amplifying solid-state imaging device according to the present invention, in particular, its pixels will be described with reference to FIGS. 1 is a plan view, FIG. 2 is a cross-sectional view taken along line AA of FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB of FIG.

In this embodiment, a second conductivity type, ie, an n-type semiconductor well region 23 serving as an overflow barrier region is formed on a first conductivity type, for example, a p-type silicon semiconductor substrate 22.
Is formed on the n-type semiconductor well region 23, and an i-type or similar semiconductor well region (for example, a p ⁻ region), in this example, an i-type semiconductor (so-called intrinsic semiconductor) well region 24
Is formed in the i-type semiconductor well region 24. A MOS transistor as a pixel (light receiving element) 21 having functions of photoelectric conversion, signal charge accumulation and charge-voltage conversion is formed so as to surround the pixel 21. An element isolation electrode 27 for element isolation, that is, an element isolation gate electrode 26 for element isolation is formed on the i-type semiconductor well area 24 with a gate insulating film 25 interposed therebetween. Become.

In the pixel 21, a linear gate electrode 30 is formed on a p-type semiconductor region 28 formed in an i-type semiconductor well region 24 with a gate insulating film 29 interposed therebetween. An n-type source region 31 and a drain region 32 are formed on both sides, respectively, to constitute an n-channel MOS transistor.

The element isolation gate electrode 26 is formed of a first-layer electrode (for example, a first-layer polycrystalline silicon).
The gate electrode 30 is formed of a second layer electrode (for example, second layer polycrystalline silicon).

The gate electrode 30 is formed thin so as to transmit incident light. Then, light is transmitted through the gate electrode 3.
By being incident on the p-type semiconductor region 28 below 0, signal charges (holes in this example) due to photoelectric conversion are generated and accumulated in the p-type semiconductor region 28. The source region 31 is connected to a vertical signal line 33 made of a metal wiring (for example, Al), and the drain region 32 is connected to a power supply line 34 made of a similar metal wiring (for example, Al).
36 indicates a drain contact portion, and 37 indicates a source contact portion.

A plurality of such pixels 21 are arranged one-dimensionally or two-dimensionally on a common substrate comprising a p-type semiconductor substrate 22, an n-type semiconductor well region 23 serving as an overflow barrier region, and an i-type semiconductor well region 24. For example, an amplification type solid-state imaging device is configured by being arranged in a matrix. The gate electrode 30 of each pixel 21 is commonly formed for each row, a common vertical signal line 33 is connected to the source region 31 of each pixel 21 via a source contact portion 37 for each column, and the drain region 32 is also drained. A common power supply line 34 is connected to each column via a contact portion 36.

Next, the pixel operation of the amplification type solid-state imaging device will be described. Here, regarding the principle of element isolation and the effect of suppressing the non-uniformity of the characteristics particularly when the signal charge is small, the schematic plan view in FIG. 4, the one-dimensional potential diagram in the vertical direction in FIGS. A description will be given using the horizontal surface channel potential φ _CH and the sensor potential φ _SN of B.

FIG. 4 is the same as FIG. 1 described in the description of the pixel structure of the present embodiment, and an amplification type pixel 21 formed by a MOS transistor is surrounded by element isolation gate electrodes 26 formed in a grid pattern. FIG. 4 is a diagram showing a planar structure that has been drawn. Each point PQ, P ₁ , P ₂ , Q ₁ , Q in FIG.
5A and 5B show vertical one-dimensional potentials of the sensor potential φ _SN and the surface channel potential φ along the dashed-dotted line PP ′ for Q ₂ and Q ₃ , respectively.
_CH and the surface potential φ _CH along QQ 'are shown in FIG.
A and B show. V _g indicates a voltage applied to the gate electrode 30 of the pixel 21, V _i indicates a voltage applied to the element isolation gate electrode 26, and V _sub indicates a substrate voltage applied to the substrate 22.

The reason why the element isolation region 27 having the element isolation gate electrode 26 as shown in FIG. 4 properly functions as the element isolation of the pixel 21 is as follows. That is, as is apparent from the one-dimensional potential at each point in FIG. 5, the potential distribution near the surface (from the surface to the overflow barrier) of the element isolation gates P ₂ and Q ₂ is, for example, a point PQ in a portion shallower than the overflow barrier. Channel potential φ _CH and point Q
_1, Q ₃ does not leak channel current to less than the potential in the vicinity of the surface.

The potential distribution near the surface of the element isolation gates P ₂ and Q ₂ (overflow barrier from the surface) is higher than the sensor potential φ _{SN where} the signal charges at the points PQ and P ₁ are accumulated, and furthermore, in all cases the signal charge 8 is accumulated, the potential of the point P ₂ is in the vicinity depth signal charges are accumulated, higher than the potential of the overflow barrier phi _oF, signal charges 8
Does not leak to adjacent pixels.

In other words, since the potentials at points P ₂ and Q ₂ increase linearly from the potential φ _{OF of the} overflow barrier toward the surface, excessive signal charges 8 are necessarily generated on the substrate. It flows deeper (overflows to the so-called substrate 22 side) and does not leak to adjacent pixels.

Under the element isolation gate electrode 26 of this embodiment, the potential distribution in the substrate depth direction is higher than the overflow barrier potential φ _OF, lower than the surface channel potential φ _CH , and the overflow barrier φ _OF
It is set so as to increase linearly toward the surface. Such a potential distribution can be achieved by forming the semiconductor region 24 below the isolation gate electrode 30 with an i-type semiconductor region or a semiconductor region close thereto.

Next, the effect of suppressing the non-uniformity of the characteristic when the signal charge 8 is small will be described. Comparing the points PQ and P _1, as apparent from the potential distribution shown in FIG. 5A, 2 for potential points P ₁ of the potential of the isolation gate (point P ₂₎
Dimensional effect, by namely proximity effect (narrow channel effect), the surface channel potential phi _CH point P ₁ is lower than that of the point PQ, sensor potential phi _SN point P ₁ is higher than that of point PQ.
Therefore, the channel current 11 easily flows toward the point PQ, and the signal charge 8 easily accumulates. Therefore, when the amount of the signal charge is small, the signal charge is collected at the point PQ, and the channel current also easily flows at the point PQ. Therefore, even when the potential changes due to the influence of the interface state and the fixed charge of the gate insulating film and the like, the phenomenon that is easily generated in the conventional ring-shaped gate electrode, that is, where the signal charge is accumulated and the channel It is difficult to cause a phenomenon in which a part where current flows is separated.

That is, due to non-uniformities such as interface states, fixed charges in the gate insulating film, and impurity concentrations in the semiconductor,
Surface channel potential φ _CH and sensor potential φ
Even if there is non-uniformity in _SN, the narrow channel effect of the element isolation gate has the effect of always bringing the position of the channel current and signal charge storage section to the center of the gate electrode of the pixel. Variations in output characteristics can be suppressed.

The potential of point PQ is point P
_The distribution under the condition that the channel current flows more easily than ₁ and that the signal charges easily accumulate is due to the effect of the potential distribution almost constant in the depth direction of the point P ₂ (that is, below the element isolation gate electrode 30) (narrow channel effect). ), The surface potential φ _CH of the potential P ₁ is low, and the sensor potential φ _SN is high.

As described above, in the basic pixel structure of this embodiment, the pixel 21 having the functions of photoelectric conversion, signal charge accumulation and charge-voltage conversion is surrounded by the element isolation gate electrode 26 around the pixel 21. The potential under the element isolation gate electrode 26 is gradually lowered from the surface to the depth of the overflow barrier so that the signal charges 8 do not leak to the adjacent pixels, and the surface potential is made smaller than the channel potential in the pixel operation. To prevent the channel current 11 from flowing to an adjacent pixel, and to have a structure in which signal charges are easily accumulated in the gate central portion of the pixel 21 and a channel current easily flows by the narrow channel effect of the potential of the element isolation gate portion. By adopting, a slight undulation in the potential distribution in the pixel due to the influence of the interface state etc. Even if the undulation varies in each pixel, when the signal charge is small (at a very low illuminance), the linearity of the sensitivity does not deteriorate, and at the same time, the fixed pattern noise due to the variation between the pixels does not occur. Can be suppressed.

By the way, as a result of further study on the above-mentioned new pixel structure, the following points became clear.

In the case of the pixel 21 described above, the narrow channel effect of the element isolation gate electrode 26 on the sensor potential φ _SN is sufficiently large, but the narrow channel effect of the element isolation gate electrode 26 on the surface channel potential φ _CH is small and not sufficient. . The reason is that the surface channel potential φ _CH is a constant value of the pixel gate electrode 3
0 and a thin gate insulating film (eg, an oxide film) 29 therebetween, the surface channel potential φ _CH is almost one-dimensionally determined by the gate electrode 30 of the pixel. This is because the effect is not so effective.

Further, with respect to the impurity concentration of the p-type semiconductor region 28 for storing signal charges under the gate electrode 30, at the end near the element isolation gate electrode 26 with respect to the center of the gate electrode 30, The impurity concentration of the p-type semiconductor region 28 decreases due to thermal diffusion in the process step, and the channel current tends to gather at the end of the gate electrode 30, which is opposite to the narrow channel effect by the element isolation gate electrode 26. In some cases, it was effective.

FIG. 6A is a sectional view taken along the line PP 'in FIG.
The sensor potential φ _SN and the surface channel potential φ _CH are shown along the line. FIG. 6B shows Q-
The surface channel potential φ _CH is shown along a line parallel to the Q ′ line and passing through the points PQ and P ₁ . As shown in FIG. 6A, but sensor potential phi _SN is part sufficiently receive signal charges 8 accumulates narrow channel effect is strongly formed on the gate center of the pixel 21, the respect surface channel potential phi _CH The effect is thin, and the channel current 11 is not strongly concentrated at the center of the gate of the pixel 21.

As described above, in the pixel 21 having the basic structure proposed in FIGS. 1 to 3, the signal charge storage portion and the surface channel portion are devised so as to gather at the center of the gate by the narrow channel effect of the element isolation gate electrode 26. In the signal charge accumulating portion, the narrow channel effect is large and signal charges are easily collected at the center of the gate. However, in the surface channel portion, impurities on the gate surface are diffused into the device isolation gate portion and the portion near the device isolation gate portion is diffused. A channel current hardly collects at the center of the surface channel portion due to a decrease in impurity concentration, and the effect of concentrating the channel current on the center of the gate due to the narrow channel effect is not high regardless of the signal charge. In other words, the effect of suppressing the unevenness in sensitivity to small signal charges (fixed pattern noise) due to the narrow channel effect of the element isolation gate portion was small.

Next, an embodiment of the present invention in which this point is improved will be described. 7 to 9 show one example. In this example, as the pixel structure, the surface current also increases the channel current of the pixel to the same extent as the sensor potential φ _SN is distributed such that the signal charges are strongly concentrated at the center of the gate of the pixel due to the narrow channel effect of the element isolation gate. The structure is devised so that it gathers strongly at the center of the gate. Pixel 2 having the above basic structure
In FIG. 1, the pixel gate, that is, the channel length under the gate electrode 30 was constant in all portions, whereas in the pixel 41 in the example of FIG. Section shorter than the section. For example, the width of the gate electrode 30 is formed so as to gradually increase from the center to the end, and the gate length gradually increases from the center of the pixel gate toward the end near the element isolation gate electrode 26. Configure.

7 to 9, parts corresponding to those in FIGS. 1 to 3 are denoted by the same reference numerals, and redundant description is omitted. In this embodiment, too, overflow occurs on the p-type silicon semiconductor substrate 22. An n-type semiconductor well region 23 serving as a barrier region is formed, and i-type semiconductor well region 23 is formed on n-type semiconductor well region 23.
A semiconductor well region (e.g., p ^- region) of the type or close to it,
In this example, an i-type semiconductor (intrinsic semiconductor) well region 24 is formed.
A MOS transistor as a pixel (light receiving element) 41 having both functions of signal charge accumulation and charge-voltage conversion is formed, and an element is formed on the i-type semiconductor well region 24 via the gate insulating film 25 so as to surround the pixel 41. An element isolation region 27 having a MOS structure in which an element isolation gate electrode 26 for isolation is formed is formed around the circumference.

In the pixel 41, a linear gate electrode 30 is formed on a p-type semiconductor region 28 formed in an i-type semiconductor well region 24 via a gate insulating film 29, and the gate electrode 30 is sandwiched therebetween, for example, in a vertical direction. An n-type source region 31 and a drain region 32 are respectively formed on both sides of the transistor to form an n-channel MOS transistor.

The element isolation gate electrode 26 is formed of a first layer electrode (for example, first layer polycrystalline silicon), and
The gate electrode 30 is formed of a second layer electrode (for example, second layer polycrystalline silicon).

The gate electrode 30 is formed to be thin so that incident light can be transmitted. When the light is transmitted and enters the p-type semiconductor region 28 below the gate electrode 30, signal charges (holes in this example) by photoelectric conversion are generated. ) Occurs and is accumulated in the p-type semiconductor region 28.

The source region 31 is connected to a vertical signal line 33 made of metal wiring, and the drain region 32 is connected to a power supply line 34 made of similar metal wiring.

Thus, in this example, as shown in FIG. 7, in particular, the gate electrode 30 has a width from the center of the gate electrode (ie, point PQ) toward the element isolation gate electrode 26 (ie, point P ₂ ). Are formed so that the channel length gradually increases from the center toward the element isolation gate electrode 26.

A plurality of such pixels 41 are arranged one-dimensionally or two-dimensionally on a common substrate comprising a p-type semiconductor substrate 22, an n-type semiconductor well region 23 serving as an overflow barrier region, and an i-type semiconductor well region 24. In this example, as shown in FIG. 10, the amplification type solid-state imaging device 38 is formed by being arranged in a matrix.

The gate electrode 30 of each pixel 21 is formed commonly for each row, a common vertical signal line 33 is connected to the source region 31 of each pixel 21 via a source contact portion 37 for each column, and the drain region A common power supply line 34 is connected to the column 32 via a drain contact portion 36 for each column.

Next, the operation of the pixel 41 of the amplification type solid-state imaging device 38 will be described.

FIG. 10A shows the sensor potential φ _SN and the surface channel potential φ along the line PP ′ in FIG.
_CH and FIG. 10B shows the surface channel potential φ _CH along the line QQ ′ in FIG.

In the pixel 41 of this example shown in FIG. 7, the short channel effect is stronger at the center of the gate electrode 30 than at the portion near the element isolation gate electrode 26 due to the shape of the gate electrode 30, and the surface potential φ _CH rises. As a result, as shown by the distribution of the surface channel potential φ _CH and the sensor potential φ _SN in the potential diagram of FIG. 10, in addition to the narrow channel effect due to the element isolation gate electrode 26, the short channel effect occurs at the gate central portion of the pixel 41. Because of the strong operation, a distribution of the surface channel potential φ _CH is obtained such that the channel current 11 is more strongly concentrated near the center of the gate of the pixel 41. Q- of FIG. 7 shown in FIG.
The surface potential φ _{CH in the} channel direction parallel to Q ′ is
For the case of two, which passes through the point PQ and the point P _1, the short channel effect per difference larger as compared with the example of FIG. 1, has a distribution of current easily flows in the gate center portion (point PQ) of the pixel .

According to the pixel 41 of this example shown in FIGS. 7 to 9, non-uniformities such as the interface state between the gate insulating film and the semiconductor, the fixed charge in the gate insulating film and the impurity concentration in the semiconductor are reduced. cause to, even non-uniformity in the pixel gate surface channel potential phi _CH or sensor potential phi _SN is somewhat occurred, the surface channel potential as the channel current 11 is concentrated in the vicinity of the gate center of the pixel 41 phi
The distribution of _CH does not significantly collapse, and the distribution of the sensor potential φ _SN in which signal charges concentrate and accumulate near the center of the gate of the pixel is the same as in FIG. 6A and does not significantly collapse. Therefore, there is almost no variation in the reduction in sensitivity that occurs when the signal charge is small due to the shift of the storage position of the signal charge from the channel current, and the fixed pattern noise at low illuminance is suppressed.

As described above, according to the present invention, a ring-shaped gate is formed by forming an element isolation region of a MOS structure surrounding a pixel having both functions of photoelectric conversion, signal charge accumulation and charge-voltage conversion. Fixed pattern noise due to variation in sensitivity in each pixel when the amount of small signal charge is easy to occur in an amplification type solid-state imaging device using pixels that have electrodes and also have functions of photoelectric conversion, signal charge accumulation and charge-voltage conversion Can be suppressed.

Further, by employing a configuration in which the channel length is changed from the central portion of the gate of the pixel to the gate end portion, the channel current and the signal charge are reduced by the narrow channel effect of the element isolation region having the MOS structure. In particular, the effect of concentrating on the channel current can be enhanced with respect to the channel current flowing on the surface, and fixed pattern noise caused by sensitivity variations in each pixel when the amount of signal charge is small can be suppressed.

In the above example, a case has been described in which a pixel based on an n-channel MOS transistor is formed using a p-type semiconductor substrate. However, a pixel in which p-type and n-type are inverted, that is, a p-type channel type is used. The present invention can also be applied to a pixel based on a MOS transistor, and in this case, the same effect can be obtained.

[0063]

According to the present invention, for a pixel having the functions of photoelectric conversion, signal charge accumulation, and charge-voltage conversion, a slight swell occurs in the potential distribution in the pixel due to the influence of interface states and the like. Even if the undulation varies in each pixel, degradation of sensitivity linearity that tends to occur when the accumulated signal charge is small (low illuminance, small signal) and fixation due to linearity variation in each pixel Generation of pattern noise can be suppressed.

By having an element isolation electrode for electrically isolating adjacent pixels, that is, light receiving elements, signal charges are generated at the same position in plan view due to a narrow channel effect caused by a potential under the element isolation electrode. Can easily be accumulated and the surface channel current can easily flow, and a potential distribution can be provided. Even with a small signal charge, the place where the signal charge is stored and the place where the channel current flows are not separated in a plane, The above effects can be obtained.

In addition, since the central portion of the pixel gate is configured to have a shorter channel length than the other portion, for example, the channel length is gradually increased from the center of the channel toward the end, the channel current is particularly reduced at the central portion of the gate. Thus, the fixed pattern noise due to the sensitivity variation in each pixel at the time of the small signal charge amount can be suppressed.

[Brief description of the drawings]

FIG. 1 is a plan view showing the basic pixel structure of a solid-state imaging device according to the present invention.

FIG. 2 is a cross-sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken on line BB of FIG. 1;

FIG. 4 is a plan view of a pixel used for describing the operation of the present invention.

FIG. 5A is a one-dimensional potential distribution diagram on the line PP ′ of FIG. 4; B is a one-dimensional potential distribution diagram on the line QQ 'in FIG.

6 is a potential distribution diagram on the line PP ′ in FIG. 4; FIG. B is a potential distribution diagram on the line QQ 'in FIG.

FIG. 7 is a plan view showing another embodiment of the image structure of the solid-state imaging device according to the present invention.

FIG. 8 is a sectional view taken along line QQ ′ of FIG. 7;

FIG. 9 is a cross-sectional view taken along the line PP ′ of FIG. 7;

FIG. 10 is a potential distribution diagram on line PP ′ of FIG. 7;

FIG. 11 is a configuration diagram of a conventional amplification type pixel.

FIG. 12A is an explanatory diagram in the case where the potential under the gate of a conventional pixel is uniform. B is an explanatory diagram in the case where the potential under the gate of a conventional pixel is non-uniform.

FIG. 13 is a one-dimensional potential diagram of point A and point B in FIG. 12B.

FIG. 14 is a signal charge-signal output characteristic diagram at points A and B in FIG. 12B.

[Explanation of symbols]

21, 41 pixels (MOS transistor), 22 p
Type silicon semiconductor substrate, 23 overflow barrier region, 24 i-type semiconductor well region, 26 device isolation gate electrode, 27 device isolation region, 28 p-type semiconductor region,
Reference Signs List 30 gate electrode, 31 source region, 32 drain region, 38 amplification type solid-state imaging device

Claims (2)

[Claims] A light receiving element having a function of performing photoelectric conversion by incident light, accumulating signal charges obtained by the photoelectric conversion, and outputting a signal voltage in accordance with the amount of the accumulated signal charges, is provided on the same substrate. A solid-state imaging device having a plurality of arrayed elements thereon, comprising: an element separation electrode for electrically separating adjacent light receiving elements; and a channel length at a central portion of a pixel gate for controlling an operation of the light receiving elements. Is shorter than other parts. 2. The solid-state imaging device according to claim 1, wherein a channel length of the pixel gate gradually increases from a center of the channel toward an end.