JPH10145458A - Loop-back device for t1 network for packet communication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a loop-back signal between a control station and a base station by deforming a reference clock to be used for synchronizing packet communication at the prescribed position of frame for prescribed clock time, and transmitting transmission data while inserting loop-back data to them during the time of deformed reference clock. SOLUTION: A clock generating part 10 generates a system clock for generating and extracting the loop-back data synchronously with the deformed clock position inserted at the prescribed position of reference clock, and a loop-back data inserting part 20 inserts the loop-back data into the transmission data synchronously with the system clock. Then, a framer and interface part 30 receives the input of transmission data including the loop-back data, transmits the to a T1 network and receives data transmitted from a station on the opposite side, and a loop-back data extracting part 40 extracts the loop-back data from the received data outputted by the framer and interface part 30 synchronously with the system clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a packet communication T1.
The present invention relates to a network and, more particularly, to a loopback device of a packet communication T1 network capable of transmitting and receiving a loopback signal between a control station and a base station in a packet communication network using the T1 standard.

[0002]

2. Description of the Related Art In general, in a communication system, information is transmitted between two points that are far apart from each other. Therefore, a loopback procedure is required as a test between devices. The loopback procedure is a test method in which a signal is sent from a starting point to a destination, and then turned back and received at the starting point along the same path to check the signal. FIG. 7 is a conceptual diagram illustrating a general loopback procedure. Generally, a base station or a control station includes a line interface unit LIU, and receives transmission data from a partner station to its own station (control station or base station) through a network edge. As described above, the loopback function is a function of transmitting data for loopback among data received from the partner station to the partner station again. With such a loopback function, a repeater or other equipment at a remote location can be tested at the central exchange, thereby reducing system maintenance costs.

In a mobile communication system, a control station (BS)
C: Base Station Controller) and base station (BTS: Ba)
Communication with the se Tranceiver Station is not a channel service but a packet switching service (P
The packet data communication is performed by a T1 or E1 trunk.

[0004] An E1 trunk is an NFA (Non Frame).
Loopback using National bits of Alignment)
(Loop Back) is possible, but T1 trunk is frame, multi-frame specification (ITU-TG703,7)
04, ANSI T1.102, 107, 403), loopback is not possible because there are no National bits. The T1 trunk does not have a loopback signal and therefore cannot test the network remotely. Therefore, there is a disadvantage that network maintenance is difficult and network maintenance costs are high.

In order to overcome the problems caused by the absence of a loopback signal, US Pat.
No. 656 discloses a remote (r) testing repeater.
emote) A loopback device is disclosed. The apparatus includes means for sensing at least one internal channel code sequence responsive to an inchannel signal and indicating an address, and means for transmitting a loopback signal to a repeater in response to the sensing means. It is composed of

[0006]

However, this prior art device relates to a device which performs a loopback function between repeaters installed on a T1 telephone line, and comprises a base station and a control station of a packet communication system. It does not perform a loopback function between. Therefore, a base station and a control station that use packet data using the T1 standard as transmission / reception data require a new device having a loopback function in order to reduce network maintenance costs.

An object of the present invention is to solve the problems of the prior art, and an object of the present invention is to provide a packet communication system for generating a loopback signal between a control station and a base station in packet communication using a T1 network. An object of the present invention is to provide a loopback device for a communication T1 network. It is another object of the present invention to provide a loopback device of a T1 network for packet communication which can test a network between a control station and a base station in packet communication using the T1 network. Another object of the present invention is to provide a loopback device for a packet communication T1 network which is excellent in network maintenance and reduces maintenance costs by testing a network between a control station and a base station by loopback. To provide.

[0008]

To achieve the above object, a loopback apparatus according to the present invention receives a frame division clock and a reference clock and inserts a modified clock at a predetermined position of the reference clock. A clock generation unit that generates a main clock and generates a system clock for generating and extracting loopback data in synchronization with the modified clock position, and a system that generates loopback data and is generated by the clock generation unit A loopback data insertion unit that inserts loopback data into the first transmission data in synchronization with a clock; and a second unit that includes loopback data output from the loopback data insertion unit.
And the interface unit for transmitting data transmitted from the other station to the T1 network and receiving data transmitted from the other station from the T1 network, and output from the framer and the interface unit in synchronization with the system clock generated by the clock generation unit. A loopback data extraction unit for extracting loopback data from reception data received from the T1 network, outputting the first transmission data to the loopback data insertion unit, and outputting the loopback data extracted by the loopback data extraction unit. A processor for inputting and outputting network test data used for loopback.

Therefore, the reference clock used for synchronizing the packet communication is deformed at a predetermined position of one frame for a predetermined clock time so that packet data cannot be transmitted or received. A loopback function can be obtained by inserting the back data into the transmission data and transmitting the data.

[0010]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. First, the configuration and operational effects of the loopback device in the T1 network for packet communication according to the present invention are shown in detail in FIGS.

FIG. 1 is a block diagram showing the configuration of a loopback device of a T1 network for packet communication according to the present invention.

In the configuration shown in FIG.
Receives a frame division clock (generally 8 KHz) and a reference clock (2.048 or 1.544 MHz) input from inside or outside of a control station or a base station. Then, the clock generator 10 generates a main clock MCLK by inserting the modified clock at a predetermined position of the reference clock, and generates a system clock SCLK for generating and extracting loopback data by synchronizing with the position of the modified clock. I do. Here, the reference clock is 2.048 MHz or 1.544 MHz, and one of the two reference clocks can be selected and used according to the speed of the applied device.

The loopback data insertion section 20 comprises a loopback data generation section 21 and an adder 22. The loopback data generator 21 generates loopback data Rdata. Then, the adder 22 outputs the generated loopback data Rdata to the clock generator 10.
In synchronization with the system clock SCLK generated in
Is added to the transmission data TXD.

The framer and interface unit 30
The second transmission data DST ₁ including the loop-back data output from the loop back data inserting unit 20 transmits to the T1 network. In addition, the other station (opposite station)
From the T1 network.

The loop back data extracting unit 40 extracts a loop back data from the received data DST _O output from the framer and interface unit 30 in synchronism with the system clock SCLK generated by the clock generator 10.

The processor 50 controls these units.
That is, the processor 50 outputs the transmission data TXD to the loopback data insertion unit 20 and outputs the main clock M
When the modified clock exists at a predetermined position of CLK, the transmission data TXD is not output, the loopback data extracted from the loopback data extraction unit 40 is input, and output as output data for testing the network.

FIG. 2 shows a frame format of a T1 trunk for packet communication applied to the present invention. In general,
One frame of the trunk used for the T1 scheme is 19
It consists of 3 bits (when the reference clock is 1.544 MHz), of which the S bit indicating the start of the frame is located at the start of the frame. The remaining bits excluding the S bit are 24 channels (the reference crack is 1.5
44 MHz), and data is allocated here. The present invention uses one of these 24 channels.
One channel is selected, and a predetermined number of bits (for example, 2 bits) are selected from the 8-bit data of the selected channel and assigned to loopback data.

When the reference clock is 2.048 MHz, one frame of the trunk used in the T1 system has 256 bits, and the S bit indicating the start of the frame is located at the start of the frame. The remaining bits excluding the S bit are divided into 32 channels, to which data is assigned. Similarly, one channel is selected from the 32 channels, and a predetermined number of bits (for example, 2 bits) are selected from the 8-bit data of the selected channel and assigned to the loopback data.

Here, the reference clock of 2.048 / 1.544 MHz is modified so that data is not transmitted / received at a specific bit of a specific channel to which loopback data is allocated. That is, the “high (High)” state or the “low (Low)” state is maintained at a specific bit of a specific channel to which loopback data is allocated. The “main clock MCLK” is generated using the modified reference clock.

FIG. 3 is a block diagram showing an embodiment of the clock generator according to the present invention. The clock generation unit 10
A counting unit 31 that counts a reference clock in synchronization with an 8 kHz frame clock; a decoder unit 32 that decodes output data of the counting unit 31 and outputs a decoding signal with a predetermined reference clock; An OR gate 33 that performs an OR logic operation on the decoded signal and the reference clock to output the main clock MCLK, and an AND logic operation on the decoding signal output from the decoder unit 32 and the reference clock to generate the system clock SCLK And an AND gate 34 for outputting.

The number of bits of loopback data is suitably 2 bits. If it is larger than 2 bits, the transmission speed is reduced, and if smaller than 2 bits, it is difficult to distinguish from other data. The operation of the clock generation unit 10 configured as described above will be described using a case where the loopback data is 2 bits as an example.

For example, when transmitting loopback data by the 8th and 7th bits of the first channel,
As shown in FIG. 6, after the frame clock (see FIG. 6A) is generated, when the counting unit 31 counts the first and second of the reference clock (see FIG. 6C), the decoder unit 32 The output of the counting section 31 is decoded to output a "1" signal. “1” output from the decoder unit 32 and the reference clock are ORed by the OR gate 33 and output as the main clock MCLK (FIG. 6).
(E)). The decoder unit 32 is designed in advance so as to decode and output a “1” signal when the counting unit 31 counts the first and second reference clocks. Therefore, the position of the desired reference clock (for example, 2
(First and second reference clocks of the second channel CH2)
, The decoder unit 32 can be designed to output the decoding signal “1”.

Also, "1" output from the decoder section 32 and the reference clock are ANDed by the AND gate 34 and output as the system clock SCLK (see FIG. 6 (G)). The decoder section 32 is a counting section 31
Is designed in advance to decode and output a "1" signal when counting the first and second reference clocks, and to force "0" during the remaining time. The AND gate 34 generates two clocks such as the reference clock only during the generation of the reference clock. System clock SCLK generated from the AND gate 34 is input to the loop back data inserting unit 20 and the loop back data extracting unit 40 is used when it is or extracted when the loop updater respectively are inserted from the received data DST ₀ .

The thus generated main clock MC
LK is input to the processor 50. The processor 50 outputs the transmission data TXD to the loopback data insertion unit 20 according to the main clock MCLK. In addition, since the rising edge and the falling edge do not exist in the modified clock existing at the predetermined position of the main clock MCLK, the processor 50 cannot output the transmission data TXD. Here, the clock generation unit described above is one embodiment, and various modifications are possible depending on the purpose of application.

FIG. 4 is a block diagram showing an embodiment of the loopback data generator. The loopback data generation unit 21 (see FIG. 1) has two D flip-flops 4
1, 42. 1D flip-flop 41
And the second D flip-flop 42 outputs the first data D ₀ applied to each D input terminal D by a write command (WR) input from the processor 50.
And the second data D ₁ are output to the adder 22. Here, the loop-back data generation unit 21 is configured by two D flip-flops for generating 2-bit loop-back data. However, when the loop back data generation unit 21 has three bits, three D flip-flops may be used. Various modifications are possible depending on the purpose.

The adder 22 is a loopback data generator 2
2-bit loopback data RDA output from 1
TA is the transmission data TX output from the processor 50.
Insert into D. The processor 50 has a main clock MC
Since the transmission data TXD is output to the loopback data insertion unit 20 according to the LK, while the modified clock is present at a predetermined position of the main clock MCLK, the transmission data TXD
Cannot be output. Therefore, the adder 22 outputs the transmission data TX
While D is not output, loopback data RDATA is inserted. At this time, the adder 22 outputs the system clock SC
The loopback data RDATA is inserted into the transmission data TXD in synchronization with LK. As described above, the transmission data DST1 including the loopback data is transmitted to the T1 network through the framer and the interface unit 30.

FIG. 5 is a block diagram showing one embodiment of the loopback data extraction unit.

In the loopback data extraction unit 40, a serial / parallel shift register is constituted by four D flip-flops 51, 52, 53 and 54. The first D flip-flop 51 receives the serial data from the framer and interface unit 30, receives the system clock SCLK at the clock input terminal, and generates the system clock SCLK as shown in FIG. In the embodiment, after the frame clock is generated, the loop-back data is output to the output terminal Q in synchronization with the first and second reference clocks). The first loopback data is
The signal is output from the output terminal Q of the first D flip-flop 51 and applied to the input terminals D of the second D flip-flop 52 and the third D flip-flop 53 in synchronization with the system clock SCLK. Next, the second loopback data with the system clock SCLK is the system clock SCL.
In synchronization with K, the signal is output from the output terminal Q of the first D flip-flop 51 and applied to the input terminal D of the third D flip-flop 53. Also, the second D flop flop 52
Is output from the output terminal Q of the second D flip-flop 52 and is applied to the input terminal D of the fourth D flip-flop 54 in synchronization with the system clock SCLK. .

The first data and the second data are 3D
After being applied to the input terminals D of the flip-flop 53 and the fourth D flip-flop 54, the processor 50 applies a “read command RD” to the clock terminals of the third D flip-flop 53 and the fourth D flip-flop 54 and The loopback data and the second loopback data are transferred to the third D flip-flop 53 and the fourth D flip-flop 5
4 from the output terminal Q. Thus, the output first and second loopback data are input to the processor 50 to notify a loopback request from the partner station.

[0030]

As described in detail above, according to the present invention, in a packet communication network using the T1 standard, a loopback signal can be transmitted and received between a control station and a base station, thereby enabling remote control. You can test the other station on the ground. As a result, maintenance of the network can be easily performed, and costs for maintenance and repair of the network can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a loopback device of a T1 network for packet communication according to the present invention.

FIG. 2 is a frame format diagram of a T1 trunk for packet communication applied to the present invention.

FIG. 3 is a block diagram showing an embodiment of a clock generation unit according to the present invention.

FIG. 4 is a block diagram showing an embodiment of a loopback data generation unit.

FIG. 5 is a block diagram showing an embodiment of a roof pack data extraction unit.

FIG. 6 is a timing chart for explaining the operation of the loopback device of the packet communication T1 network according to the present invention.

FIG. 7 is a conceptual diagram of a loopback illustrating a general loopback.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Clock generation part 20 Loopback data insertion part 30 Framer and interface part 40 Loopback data extraction part 50 Processor

Claims (14)

[Claims] In a loopback device of a packet communication T1 network, a main clock is generated by receiving a frame division clock and a reference clock and inserting a modified clock at a predetermined position of the reference clock. A clock generation unit for generating a system clock for generating and extracting loopback data in synchronization with a position; and generating the loopback data, and synchronizing the loop with the system clock generated by the clock generation unit. A loopback data insertion unit for inserting the back data into the first transmission data; and a second transmission data including the loopback data output from the loopback data insertion unit, transmitted to the T1 network, and transmitted from the partner station. And framer receiving data from the T1 network A loopback data extraction unit for extracting loopback data from reception data received from the T1 network output from the framer and the interface unit in synchronization with a system clock generated by the clock generation unit; A processor that outputs the first transmission data to the loopback data insertion unit, and that inputs the loopback data extracted by the loopback data extraction unit and outputs network test data used for loopback. T for packet communication characterized by the following:
Loopback device for loopback of one network. 2. The main clock is modified at a predetermined position in a frame such that the reference clock maintains a “High” or “Low” state for one or more clock times. Wherein the system clock is generated such that a predetermined number of pulses are generated while the main clock holds a “High” or “Low” state. Item 2. A loopback device for a packet communication T1 network according to item 1. 3. A clock generating unit, comprising: a counting unit that counts a reference clock in synchronization with a frame clock; a decoder unit that decodes output data of the counting unit and outputs a decoding signal at a predetermined reference clock. An OR gate for performing a logical operation of a decoding signal output from the decoder unit and the reference clock to generate a main clock, and performing an AND logical operation of the decoding signal output from the decoder unit and the reference clock 2. The loopback device for a packet communication T1 network according to claim 1, further comprising: an AND gate that generates a system clock by using the AND gate. 4. The loopback device for a packet communication T1 network according to claim 1, wherein the loopback data insertion unit includes a loopback data generation unit and an adder. 5. The loopback data extraction unit according to claim 1, wherein
2. The device according to claim 1, further comprising a parallel shift register.
The loopback device of the packet communication T1 network described in the above. 6. The loopback device for a packet communication T1 network according to claim 4, wherein the loopback data generation unit has a D flip-flop corresponding to the number of bits of the loopback data. 7. The packet communication T according to claim 4, wherein the adder adds the loopback data to the transmission data in synchronization with the system clock.
Loopback device for one network. 8. A serial / parallel shift register, comprising: a first flip-flop that receives serial data from the framer and an interface unit and generates output data in synchronization with the system clock; A second flip-flop for receiving output data and generating output data synchronized with the system clock; receiving data output from the first flip-flop and outputting output data according to a control signal output from the processor; 6. The semiconductor device according to claim 5, further comprising: a third flip-flop configured to receive the output data from the second flip-flop and outputting the output data according to a control signal output from the processor. Loopback of T1 network for packet communication Location. 9. A loopback device for a packet communication T1 network, wherein a main clock is generated by inserting a modified clock at a predetermined position of a reference clock, and a clock generation for generating a system clock that generates a clock based on the modified clock position. A loopback data insertion unit for generating loopback data and inserting the loopback data into transmission data while the system clock is generated; and receiving the transmission data including the loopback data and receiving the T1 A framer and an interface unit for transmitting data to a network and receiving data from the T1 network; and extracting loopback data from received data output from the framer and the interface in synchronization with the system clock. A processor that controls the units, outputs transmission data to the loopback data insertion unit using the main clock, and receives network loop data extracted from the loopback data extraction unit and outputs network test data. A loopback device for a packet communication T1 network, comprising: 10. The main clock is modified such that the reference clock keeps a “High” or “Low” state at one or more clock times at a predetermined position of a frame. Wherein the system clock is generated such that a predetermined number of pulses are generated while the main clock maintains a "high" or "low" state. Item 10. A loopback device for a packet communication T1 network according to Item 9. 11. A clock generator for converting a reference clock in a T1 network for packet communication, generating a main clock for transmitting / receiving data to / from the T1 network, and generating a system clock for generating and extracting loopback data. A loopback data insertion unit that generates loopback data in synchronization with the system clock, and inserts the generated loopback data into transmission data; and the transmission data output from the loopback data insertion unit. A framer and an interface for transmitting to the T1 network and receiving data from the T1 network; and a loopback for extracting loopback data from the received data output from the framer and the interface in synchronization with the system clock A processor that outputs the transmission data to the loopback data insertion unit according to the main clock, and receives the input of the loopback data extracted from the loopback data extraction unit, and outputs network test data. A loopback device for a packet communication T1 network, comprising: 12. The clock generator, when a frame clock for dividing a frame is generated, sets a reference clock to “high” or “low” at one or more clock times at a predetermined position of the frame. The main clock is generated while maintaining the "high" state, and a predetermined number of reference clock pulses are generated while the main clock maintains the "high (high)" or "low (low)" state. A clock is generated.
2. The loopback device of the packet communication T1 network according to 1. 13. The loopback data insertion unit, which generates a loopback data in synchronization with the system clock, and adds the loopback data to transmission data in synchronization with the system clock. The loopback device of the packet communication T1 network according to claim 11, comprising an adder. 14. The loopback data extraction unit according to claim 1, wherein the loopback data extraction unit extracts the loopback data inserted at a predetermined position of a reception frame output from the framer and the interface in synchronization with the system clock. 12. The loopback device of the packet communication T1 network according to 11.