JPH10149311A - Memory controller - Google Patents

Abstract

(57) [Problem] To prevent a memory access speed from being reduced by avoiding a standby state of memory access even when a memory access request and a refresh request are simultaneously issued to the same memory device. To realize an efficient memory system. SOLUTION: A request queue 103 for sequentially storing memory access requests and judging the request amount.
a, 103b, a refresh timing circuit that counts the refresh timing time and outputs the number of pending refresh operations, and is determined by the request amount and the pending refresh operation number or the respective amount / number. An arbitration circuit 105 for arbitrating the memory access request and the refresh operation based on the memory control priority to be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling a read / write access and a refresh operation of a memory device using a dynamic RAM or the like requiring a refresh operation.

[0002]

2. Description of the Related Art Conventionally, arbitration means arbitrates between a refresh request from a refresh request output means having a counter for counting a refresh timing and a memory access request from an address decoding means, and sends a memory control signal to a memory device. A memory control device for outputting data has been developed. Further, in the above-mentioned technology, a "memory control device" disclosed in Japanese Patent Laid-Open No. 6-290104, for example, as disclosed below, is disclosed as a device for increasing the speed.

That is, in a memory system having a plurality of memory devices to be controlled, an address input from an external bus and a read / write control signal are decoded, and a memory access request signal is generated for each memory device to be controlled. Address decoding means, refresh request means for outputting a refresh request signal at a fixed period for each memory device to be controlled, and arbitration between these memory access request signals and refresh request signals; A memory control device for generating a RAS / CAS signal in response to a request for access to a memory device different from the memory device performing the refresh during the refresh. This is to execute memory access.

[0004]

However, in the conventional memory control device as described above, when a memory access request and a refresh request are simultaneously made to the same memory device to be controlled. Since only one of the requests is executed and the other request is pending, the memory access may be delayed until the refresh operation is completed, and the memory access speed in the memory access at the time of the refresh request is reduced. There was a problem.

The present invention has been made in view of the above, and is intended to avoid a memory access standby state even when a memory access request and a refresh request are simultaneously made to the same memory device. An object of the present invention is to realize an efficient memory system in which a memory access speed does not decrease.

[0006]

In order to achieve the above object, a memory control device according to a first aspect of the present invention is a memory device requiring a refresh operation, wherein the memory device is used for a memory access request. A memory control device for controlling access and refresh operations of the memory device in response to the memory access requests, storing the memory access requests sequentially, and determining a request amount; A refresh operation number outputting means for outputting a number, a memory access request and the refresh based on a memory control priority determined by the request amount and the pending refresh operation number or the respective amount / number. Arbitrator to mediate operations When, those having a.

That is, the urgency of memory control can be determined from the amount of memory access requests stored in the storage means and the number of pending refresh operations, so that the number of pending refresh operations can be reduced. When memory access requests are at least stored in the storage means, a high-speed memory system can be realized by giving priority to memory access.
When there is no memory access request, priority is given to the pending refresh operation, so that an efficient refresh operation can be performed. When the number increases, the refresh operation is preferentially processed, so that a sufficient refresh operation required by the memory device can be guaranteed.

According to a second aspect of the present invention, there is provided a memory control device which uses a memory device requiring a refresh operation.
An information processing apparatus for assigning a plurality of levels of priority to a memory access request, wherein the memory control unit controls access and refresh operations of the memory device in response to the memory access request. Storage means for sequentially storing memory access requests, and determining the request amount;
Refresh operation number output means for counting the time of refresh timing and outputting the number of pending refresh operations, and a memory determined by the request amount and the number of pending refresh operations or the respective amount / number Arbitration means for arbitrating the memory access request and the refresh operation based on the control priority.

That is, even in an information processing apparatus that assigns a plurality of levels of priority to a memory access request, the priority of memory access is taken into account, so that an efficient refresh operation is realized as in the first aspect. I do.

According to a third aspect of the present invention, there is provided the memory control device, further comprising a counting means for measuring a fixed time interval and outputting the counted value, wherein the arbitration means is provided with the request amount and the pending. Arbitration of a memory access request and a refresh operation is executed based on the number of refresh operations and the count value.

That is, by providing a counting means for measuring a fixed time interval, determining the urgency of memory control in consideration of the count value, and arbitrating the memory access request and the refresh operation, the specification of each memory device , The required number of refreshes within a certain time can be guaranteed.

The memory control device according to a fourth aspect of the present invention further comprises a register which is set by an external write signal and outputs a memory access priority signal.
The memory control priority for a refresh operation determined based on the amount of requests stored in the storage unit and the number of pending refresh operations is changed by the memory access priority signal output from the register. Things.

That is, the memory control priority for memory access can be set high by setting the register. Therefore, when continuous memory access is required by the processor and other devices, the memory control priority can be set. , The high-speed memory access becomes possible.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory control device according to the present invention will be described in detail with reference to the accompanying drawings.

(System Configuration) FIG. 1 is a block diagram showing a configuration of a memory system using a memory control device according to an embodiment. In the figure, reference numeral 101 denotes a bus to which a processor or an external interface is connected;
Reference numeral 2 denotes a bus 1-I / F selector for receiving a memory access request via the bus 101, distributing the request to each request of a priority level, and queuing the request in a request queue described later.

Also, 103a and 103b are request queues as storage means, 104 is a refresh circuit as a refresh operation number output means for outputting the number of pending refresh operations as described later, and 105 is memory access and refresh An arbitration circuit as arbitration means for arbitrating operations, 106 is a scheduler, 107 is a memory device, 108 is a reply data creation unit, 109 is a reply queue, and 110 is a bus 1
I / F.

(System Operation) Next, the operation of the memory system configured as described above will be described. The bus 1-I / F selector 102 receives a memory access request from the bus 101, distributes the request to request requests S1a and S1b for each priority level of the request, and queues the requests in request queues 103a and 103b. The arbitration circuit 105 receives the refresh request S2 from the refresh circuit 104 and the request queue 103a, 1
In response to the request requests S1a and S1b from the server 03b, arbitration regarding memory control is executed as follows.

That is, when the memory control priority associated with the refresh request S2 is higher than the memory control priority of the memory access request S3 and the refresh operation is selected as the memory control, the refresh operation is performed on the memory device 107. When the memory access priority associated with the memory access request S3 is higher and the memory access is selected as the memory control, the scheduler 106 controls the two request queues 103a, 1a.
03b, request requests S1a and S1b from
An access request S5 is made to the memory device 107.

The reply data creation unit 108 creates reply data from the data S6 obtained from the memory device 107 and the request information S7, and queues the reply data in the reply queue 109. Bus 1-I / F110
Retrieves reply data from the reply queue 109 and sends a reply to the processor or the like via the bus.

(Configuration of Request Queue) Next, the configuration and operation of the request queues 103a and 103b will be described in detail. FIG. 2 is a block diagram showing the configuration of the request queue in FIG. In the figure, reference numeral 201 denotes an FIF for sequentially storing request requests for each priority.
O and 202 are memory access request units that output a memory control priority S8 and a memory access request S3 to the arbitration circuit 105 based on the request amount from the FIFO 201.

(Operation of Request Queue) In the request queue 103 configured as described above, the FIFO
201 receives a request request S1 from the bus 1-I / F selector 102,
To the memory access request unit 20
For 2, the amount of requests in FIFO 201 is emp
Inform using ty-flag and full-flag.

The memory access request unit 302 is provided with a FIFO
The request amount from the arbitration circuit 105 is converted into the memory control priority shown in Table 1 below, and the memory control priority S8 and the memory access request S3 are output to the arbitration circuit 105. In response to the access response signal S9, the handshake of the memory access request is performed, and the reading of the FIFO 201 is updated to read the next request.

[0023]

[Table 1]

(Configuration of Refresh Circuit) FIG.
3 is a block diagram showing a configuration of a refresh circuit in FIG. In the figure, reference numeral 301 denotes an up counter for measuring the interval time of the refresh operation based on the reference clock signal S15, and 302 denotes the refresh response signal S1
When 1 is not active, the counter counts the number of refreshes that are pending upon receiving a carry from the up counter 301, 303 is an up counter as counting means for counting a fixed time (32 ms), and 304 is described later. The refresh request section outputs a refresh request and a memory control priority according to the operation performed.

(Operation of Refresh Circuit) In the refresh circuit configured as described above, the counter 301
, The interval time of the refresh operation is measured using the reference clock signal S15. Also, the counter 30
2, if the refresh response signal S11 is not active, the carry from the counter 301 is received and the number of pending refreshes is counted. If the refresh response signal S11 is active, the number of pending refreshes is decremented. , The number of pending refreshes S12 is output to the refresh request unit 304. Also, the counter 30
3 outputs the elapsed time S14 obtained as the count value to the refresh request unit 304.

(Configuration of Refresh Request Unit) FIG. 4 is a block diagram showing the internal configuration of the refresh request unit in FIG. In the figure, reference numeral 401 denotes an internal register which is set by an external write signal S13 and outputs a memory access priority signal S16 based on a specific bit value to a priority level table which will be described later. Reference numeral 402 denotes a ROM implemented by a pending refresh number S12 and a counter 303. Elapsed time S14 and internal register 401
403 is a refresh sequencer that outputs the memory control priority S2 in response to the memory access priority signal S16 from the arbitration circuit 105 and outputs a refresh request signal S10 with the memory control priority S2 to the arbitration circuit 105.

(Operation of Refresh Request Unit) In the refresh request unit 304 configured as described above, the priority level table 402 stores the pending refresh number S12 from the counter 302, the elapsed time S14 from the counter 303, and the external write signal. The memory control priority signal S16 based on the specific bit value of the internal register 401 set in S13 is input, and the memory control priority S2 is output as shown in FIG.

The refresh sequencer 403 is
When there is a pending refresh operation, that is, when there is a pending refresh number S12, the memory control priority S2 is given to the arbitration circuit 105 while receiving the refresh response signal S11 from the arbitration circuit 105 and handshaking the refresh request. A refresh request signal S10 is output accordingly.

The memory control priority S2 obtained from the priority level table 402 by inputting the memory access priority signal S16, the number of pending refreshes S12 and the elapsed time S14 is the case where the memory access priority of FIG. 5 is not specified. In the graph (a) and the graph (b) in the case where the memory access priority is designated, the priorities 0, 1, 3, which are obtained from the coordinates composed of the pending refresh number S12 and the elapsed time S14.
5,7.

In the above, when the elapsed time is on the axis S14, that is, the number of pending refreshes S1
When 2 is 0, the priority is set to 0.

[0031]

As described above, according to the memory control device of the present invention, the amount of memory access requests stored in the storage means and the number of pending refresh operations are determined. Since the urgency of memory control can be determined, if the number of pending refresh operations is small and a memory access request is placed in the storage means, high-speed memory access can be achieved by giving priority to memory access. If the system can be realized, and if there is no memory access request, the pending refresh operation is processed with priority, so that an efficient refresh operation can be performed. If the number of refresh operations For processing with priority Mesh operation, it is possible to ensure a sufficient refresh operation memory device requires. Therefore, an efficient memory system that avoids a decrease in memory access speed is realized.

According to the memory control device of the present invention (claim 2), the priority of memory access is also taken into account in an information processing device that assigns a plurality of levels of priority to a memory access request. Therefore, the above claim 1
In the same manner as described above, an efficient refresh operation can be performed, and an efficient memory system that avoids a decrease in memory access speed can be realized.

Further, according to the memory control device of the present invention (claim 3), there is provided a counting means for counting a predetermined time interval, the urgency of the memory control is determined in consideration of the count value, and the memory access is determined. Since the request and the refresh operation are arbitrated, it is possible to guarantee the required number of refreshes within a certain time described as the specification of each memory device.

According to the memory control device of the present invention (claim 4), the memory control priority for memory access can be set high by setting the register. When continuous memory access is required, high-speed memory access is enabled by increasing the memory control priority.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory system using a memory control device according to an embodiment.

FIG. 2 is a block diagram showing an internal configuration of a request queue in FIG.

FIG. 3 is a block diagram showing an internal configuration of a refresh circuit in FIG. 1;

FIG. 4 is a block diagram illustrating an internal configuration of a refresh request unit in FIG. 3;

FIGS. 5A and 5B are graphs showing refresh priorities according to the embodiment, wherein FIG. 5A shows a case where memory access priority is not specified, and FIG. 5B shows a case where memory access priority is specified; .

[Explanation of symbols]

 103a, 103b request queue 104 refresh circuit 105 arbitration circuit 201 FIFO 202 memory access request unit 302 counter 303 up counter 304 refresh request unit 401 internal register

Claims (4)

[Claims] 1. A memory device requiring a refresh operation, wherein the memory device controls the access and the refresh operation of the memory device in response to the memory access request. A storage means for determining the request amount, and a refresh timing time counted,
A refresh operation number output unit for outputting a pending refresh operation number; and a memory control priority determined by the request amount and the pending refresh operation number or the respective amount / number. A memory control device, comprising: arbitration means for arbitrating a memory access request and the refresh operation. 2. An information processing apparatus using a memory device requiring a refresh operation and assigning a plurality of levels of priority to a memory access request, wherein the information processing device accesses the memory device in response to the memory access request. In a memory control device for controlling a refresh operation, a memory access request is sequentially stored for each of the priorities, a storage means for determining the request amount, a refresh timing time is counted, and the number of pending refresh operations is determined. Means for outputting the number of refresh operations to be output, and the memory access request and the refresh operation based on the request amount and the number of pending refresh operations or a memory control priority determined by the respective amount / number. Tones A memory control device comprising arbitration means for stopping. And a counting means for counting a predetermined time interval and outputting the counted value as a count value, wherein the arbitration means calculates the number of requests, the number of pending refresh operations, and the count value. 2. The arbitration of a memory access request and a refresh operation is performed.
Or the memory control device according to 2. 4. A memory device further comprising a register set by an external write signal and outputting a memory access priority signal, wherein the request amount stored in the storage means is determined by the memory access priority signal output from the register. 4. The memory control device according to claim 1, wherein a memory control priority for a refresh operation determined based on the number of pending refresh operations is changed.