JPH10149377A - Logical verification method - Google Patents

Abstract

(57) Abstract: A first object of the present invention is to provide a logic verification method capable of easily confirming the operation of a fault check circuit. A logic compiler adds a same division number to each of logic elements constituting a failure check circuit and develops the same on a memory, so that the failure check circuit can be extracted as a logic block. The logic simulation execution unit 120 suppresses the input of an arbitrary input signal among a plurality of input signals to the logical block specified by the division number, and sets an arbitrary input signal value for the input signal. , Perform logic verification of the logic block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification method used in the logic design of an electronic computer, and more particularly to a logic verification method used in an electronic computer having a failure check circuit for detecting a hardware failure. A logic verification method suitable for

[0002]

2. Description of the Related Art Conventionally, a logic simulation apparatus for a logic verification method used at the time of logic design of an electronic computer is:
The logic circuit to be verified is converted to a Boolean algebra or other format suitable for logic simulation in its original structure, and a specific signal value is externally set to the signal line of the input port on the logic circuit. The logic operation of each logic element of the circuit is performed, and the signal value of the operation result is propagated according to the connection state.

[0003]

However, according to the conventional method, when a failure check circuit for detecting a failure of hardware is provided in a logic circuit of an electronic computer, the failure check circuit is normally used. Since no error occurs in the logical operation, the method of giving a specific signal value from the input port cannot perform the logic verification of the failure check circuit. Therefore, in general, it is necessary to manually set a fault signal value for an arbitrary input signal line of the fault check circuit, and there has been a problem that it takes time to verify the logic.

Further, although the fault check circuit does not generate an error in normal logic operation, when verifying the operation of the logic circuit itself including the fault check circuit, the normal operation of the fault check circuit itself is checked. Since the logic simulation is performed, unnecessary logic simulation is performed, and there is a problem that the logic verification time becomes longer.

[0005] A first object of the present invention is to provide a logic verification system which can easily confirm the operation of a fault check circuit.

A second object of the present invention is to provide a logic verification system capable of shortening the logic verification time.

[0007]

In order to achieve the first object, the present invention relates to a logic verification system in which a logic circuit including a fault check circuit is developed on a memory and its operation is verified. By adding the same division number to each of the logic elements constituting the failure check circuit and expanding the same on the memory, the failure check circuit can be extracted as a logic block, and B) specified by the division number. The logic verification of the logic block is executed by suppressing the input of an arbitrary input signal among a plurality of input signals to the logic block and setting an arbitrary input signal value to the input signal. With this method, the operation of the failure check circuit can be easily confirmed.

In the above logic verification method, preferably,
The addition of the logical number is based on the connection definition signal, which is the output signal of the failure check circuit, and sequentially assigns the logic elements that output the connection definition signal to other logic elements connected to the input signal of the logic element. This is performed by back tracing, extracting a logical block, and adding the same division number to the logical elements constituting the extracted logical block. This method makes it easy to extract the logical block. What can be done.

Further, in order to achieve the second object,
The present invention relates to a logic verification method in which a logic circuit including a fault check circuit is developed on a memory and its operation is verified.
A) By assigning the same division number to each of the logic elements constituting the failure check circuit and developing the same on the memory, the failure check circuit can be extracted as a logic block, and C) specified by the division number. The logic block to be deleted is deleted based on the division number, the remaining logic circuit is expanded in the internal memory, and an output signal unique value corresponding to the output signal value of the logic block to be deleted is expanded. The logic verification block is input as an input signal of the logic block, and the logic verification time can be reduced by such a method.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A logic verification system according to an embodiment of the present invention will be described below with reference to FIGS. First, an overall configuration of a simulation device used for a logic verification method according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a system block diagram of a logic simulation device used for a logic verification method according to an embodiment of the present invention.

The logic simulation apparatus according to the present embodiment includes a logic compiler 110 and a logic simulation execution unit 120. Logical compiler 1
10 is a logic compiling unit 112 and a circuit information dividing unit 1
14. The logic simulation execution unit 120 includes a logic development unit 122 and a logic simulation unit 124.

The logic circuit file 130 stores a plurality of logic circuits to be subjected to logic simulation. A logic circuit is configured by connecting a plurality of logic elements such as a logical sum and a logical product. An example of the stored logic circuit will be described later with reference to FIG. The logic circuit is a VHDL (VHSIC HardwareD)
script (language description). Here, VHSIC is Very Hi
gh Speed IntegratedCircui
It is an abbreviation of t. The logic circuit to be subjected to the logic simulation is specified by using the input parameter card 140 to specify a file parameter, and the logic circuit file 1
From 30, it is taken into the logic compiler 110.

A logic compiling unit 112 in the logic compiler 110 converts a netlist format logic circuit information table from connection circuit information of logic elements constituting a logic circuit to be subjected to logic simulation read from the logic circuit file 130. create. The detailed configuration of the logic circuit information table will be described later with reference to FIG. The created logic circuit information table is output to the simulation master file 134.

The connection definition file 132 stores output signal line names and output signal fixed values of a plurality of logical blocks, respectively. An example of the connection definition file 132 will be described later with reference to FIG. Although the concept of the logic block will be described later with reference to FIG. 2, a set of logic elements that generate an output signal corresponding to the output signal line name is defined as
It is called a logical block. In the present embodiment, for example, a parity generation circuit and a parity check circuit that constitute a failure check circuit correspond to a logical block.

The circuit information division section 114 uses the logic circuit information table created by the logic compilation section 122 to generate a plurality of logic elements for generating output signals of the respective output signal line names stored in the connection definition file 132. Are extracted as logical blocks. When extracting a plurality of logical blocks, an ID number called a division number is added to each. For example, in a large-scale logic circuit, since a plurality of fault check circuits are built in, a division number is added to each of the extracted fault check circuits so that each fault check circuit can be identified. I have.

The circuit information division section 114 additionally outputs information on the division number added to the extracted logical block to the simulation master file 134, and adds the division number to the logical circuit information table. The circuit information dividing unit 114 also adds a division number to the read connection definition file to create connection definition file information,
The data is additionally output to the simulation master file 134. Details of the connection definition file information will be described later with reference to FIG.

The logic developing unit 122 in the logic simulation execution unit 120 converts the logic circuit information table stored in the simulation master file 134 based on the control parameters specified by the control parameter card 142 into the logic simulation execution unit 120. Expand to internal memory.

Here, the control parameters include a processing mode and a signal line name for designating a logical block. Processing mode is "verify", "delete", "unspecified"
There are three types. The “verification execution” is a mode in which the input operation of the input signal to the failure check circuit in the logic circuit is suppressed and an arbitrary input signal is applied to verify and execute the check operation of the failure check circuit.
“Delete” is a mode in which the fault check circuit is deleted from the logic circuits, and the logic operation is verified and executed only for the remaining logic circuits. “Unspecified” is a mode in which the logic operation of the entire logic circuit including the failure check circuit is verified and executed.

Further, a logical block to be verified or deleted can be specified by using a signal line name for specifying a logical block number.

When the “verification execution” processing mode is specified, the logic developing unit 122 reads the logic circuit information table stored in the simulation master file 134 from the logic circuit information table.
The entire logic circuit is expanded in the internal memory. Then, the input signal to the logical block specified by the division number added for each logical block is suppressed, and the input signal can be given by giving an arbitrary input signal.

When the "delete" processing mode is designated,
The logic developing unit 122 extracts the remaining logic circuits from which the fault check circuits have been deleted from the logic circuit information table stored in the simulation master file 134,
Extract to internal memory. Further, the connection definition file information stored in the simulation master file 134 is also read out. The process of deleting the failure check circuit can be performed by designating the division number added for each logical block. At this time, the failure check circuit is not developed. However, the information of the signal line connected to the input terminal of the failure check circuit is deleted, and the terminal of the input signal line of the logic element to which the failure check circuit is connected is connected to the failure check circuit read from the connection definition file information. By setting the output signal eigenvalue of the above, even if the failure check circuit is deleted, other logic circuits can operate normally. The detailed operation will be described later.

When the “unspecified” processing mode is designated, the logic developing unit 122 reads the logic circuit information table stored in the simulation master file 134
The entire logic circuit including the failure check circuit is developed in the internal memory.

Next, the logic simulation unit 124
The logic development unit 122 compares the logic circuit information developed in the internal memory of the logic simulation execution unit 120 with the signal change information of the input signal line of the logic circuit to be subjected to logic verification stored in the signal value data file 136. Read the signal value. Then, the logic simulation unit 124
Operates the target logic circuit by giving the signal value read from the signal value data file 136 to the developed logic circuit information for each simulation time unit,
The signal change status is stored in the simulation result file 13.
8 is output. The simulation result is output to the simulation result list 150.

Next, an example of a logic circuit to be subjected to logic verification in the logic verification method according to one embodiment of the present invention will be described with reference to FIG. FIG. 2 is a circuit diagram of an example of a logic circuit to be subjected to logic verification in the logic verification method according to one embodiment of the present invention.

The logic circuit 200 includes, for example, eight flip-flops (FF) 210-0, 210-1,.
0-7 and eight flip-flops (FF) 220-
, 220-7, a flip-flop (FF) 230, a parity generation circuit 240, and a parity check circuit 250.

An output signal line DATA0, which is a data signal line of the flip-flop (FF) 210-0, is connected to an input terminal of the flip-flop (FF) 220-0. Similarly, a flip-flop (FF) 210-
Output signal line D which is a data signal line of 1,..., 210-7
ATA1,..., DATA7 are connected to input terminals of flip-flops (FF) 220-1,.

Here, eight flip-flops (FF)
210-0, 210-1,..., 210-7 and eight flip-flops (FF) 220-0, 220-1,.
When the distance between the flip-flop (F) and the flip-flop (F) is large, that is, the eight flip-flops (FF) 210 to the flip-flop (F
F) When the signal transmission line reaching 220 is long, a parity generation circuit 240 and a parity check circuit 250 are provided in order to eliminate the effects of hardware failure, noise, and the like.

The parity generation circuit 240 includes flip-flops (FF) 210-0, 210-1,..., 210-7.
, Output signal lines DATA0, DATA2, ..., DATA7
And outputs a 1-bit parity signal to an output signal line PARITY0 based on an 8-bit output signal output from the. The parity check circuit 250 outputs an 8-bit data signal output from the output signal lines DATA0, DATA2,..., DATA7 of the flip-flops (FF) 210-0, 210-1,. A parity check is performed using a 1-bit parity signal output from the signal line PARITY0, and the result is output to an output signal line DATACHK0.

In the parity check, a parity check circuit 250 generates a predicted parity value from a signal value on an 8-bit data line and compares it with a signal value of a transmitted parity signal to generate a 1-bit error on the data line. This is done by checking the situation. As a result, it is possible to perform a check when an improper failure such as data loss occurs on the data transfer line.

In such a parity circuit, the check result of the signal line in the parity check circuit 250 always generates a constant value indicating a normal value unless a failure due to physical disconnection or the like on the hardware occurs. It is configured. Here, for example, the parity check result is
When there is no transmission error or the like, it is “0”, and when a transmission error occurs, it is “1”.

It is assumed that the output signal line PARITY0 of the parity check circuit 250 is connected to a flip-flop (FF) 230.

In the present embodiment, the parity generation circuit 240 and the parity check circuit 250 are failure check circuits. Therefore, the circuit information dividing unit 1 shown in FIG.
14 extracts the parity generation circuit 240 and the parity check circuit 250 as one logical block and adds the same division number. Further, the logic developing unit 1 shown in FIG.
22 is a block diagram of the logic simulation in which, when the processing mode is “execute verification”, the input signal input to the logic block including the parity generation circuit 240 and the parity check circuit 250 is suppressed and an arbitrary input signal is given to provide a logic simulation. The unit 124 performs verification of the check operation of the logical block.

When the processing mode is "delete", the logical block including the parity generation circuit 240 and the parity check circuit 250 is deleted, and the remaining flip-flops (FF) 210-0 and 210-1 are deleted. ,…,
210-7 and flip-flops (FF) 220-0,
., 220-7 and a flip-flop (F
F) Expanding 230, the logical simulation unit 124
Performs verification of the logic operation of this logic circuit. When the processing mode is “unspecified”, the entire logic circuit 200 shown in FIG. 2 is expanded, and the logic simulation unit 124 executes verification of the logic operation of the logic circuit.

Next, referring to FIG. 3, a connection definition file 1 used in the logic verification method according to the embodiment of the present invention will be described.
An example of the definition of 32 will be described. FIG. 3 is an explanatory diagram of a definition example stored in a connection definition file used in the logic verification method according to one embodiment of the present invention.

The connection definition file 132 includes an output signal line name 1322 and an output signal unique value 1324. The output signal line name 1322 is for defining a logic block of the failure check circuit. The output signal line name 1322 designates the output signal line of the circuit on the output side of the entire logic circuit among the logic element circuits constituting the failure check circuit. For example, the logic circuit 2 shown in FIG.
On the other hand, the logical block of the failure check circuit including the parity generation circuit 240 and the parity check circuit 250 is defined by “DATACHK0” which is the name of the output signal line of the parity check circuit 250.

The output signal unique value 1324 defines a unique value of an output signal given to an output signal line of the logical block when the logical block is deleted. For example, assuming that the output signal representing the parity check result of the parity check circuit 250 shown in FIG. 2 is “0” when there is no transmission error or the like, the output signal unique value 1324 is “0”. Is defined.

Circuit information division unit 1 of logic compiler 110
14 is the output signal line name 13 in the connection definition file 132
22 is read, the logic circuits having the read output signal line names are sequentially traced to the input side, and a logic block in a range surrounded by flip-flops or input / output ports is extracted.

That is, in the example of the logic circuit shown in FIG. 2, when tracing to the input side of the parity check circuit 250,
Flip-flops (FF) 210-0, 210-1,
, 210-7 and the parity generation circuit 240 are connected. Further, flip-flops (FF) 210-0, 210-
1, ..., 210-7 are connected. Therefore, the extracted logical blocks are the parity generation circuit 240 and the parity check circuit 250. In order to sequentially trace the logic circuit with the output signal line name to the input side,
The logic circuit information table created by the logic compiling unit 112 is used. This will be described later with reference to FIG.

Next, the configuration of the logic circuit information table stored in the simulation master file 134 will be described with reference to FIG.

FIG. 4 is an explanatory diagram of the configuration of the logic circuit information table stored in the simulation master file used in the logic verification method according to one embodiment of the present invention. An example of specific contents of the logic circuit information table will be described later with reference to FIG.

The logic circuit information table 400 includes a signal name list 410, a logic element table 420, and an output connection destination list 430. The logic element table 420 is created by the number of logic elements constituting the target logic circuit. The output connection destination lists 430 are created by the same number as the number of the logic element tables 420.

The signal name list 410 includes the signal line name 41
1, an output element address 412, and an initial signal value 413. The signal line name 411 is a name added to each signal line connecting each logic element in the target logic circuit. The output element address 412 indicates the head address of the logic element table 420 of the logic element that outputs the signal line having the signal line name described in the signal line name 411. The initial signal value 413 indicates an initial signal value of the signal line.

The logic element table 420 includes an element function 421, an element delay 422, and a division number 423.
, An output signal value 424, an output signal name list address 425, a control flag 426, an output connection destination element list address 427, an input n signal value 428, and an input n connection source element address 429. . here,
The input n signal value 428 and the input n connection source element address 42
9 are created by the number n corresponding to the number n of the input signal lines.

Here, the element function 421 is AND, OR
Represents the logical function of the element. Element delay 4
Reference numeral 22 denotes a delay time unique to the logic element. The division number 423 indicates the number of a logical block composed of a plurality of logical elements that output the signal line names defined in the connection definition file shown in FIG. Using this division number, a logic element included in the same logic block can be specified.

The output signal value 424 indicates the output signal value of the logic element. The output signal value is determined according to the input signal value and the element function of the logic element. The output signal name list address 425 has the address of the signal name on the signal name list 410 having the signal name of the output terminal of this logic element. The control flags 426 are various flags used for simulation execution control, and one of them is an input suppression flag. The input suppression flags are used in the processing mode “delete”, are created in a number corresponding to the number n of input lines, and can individually set each input suppression flag. The function thereof will be described later. I do.

The output connection element list address 427 is
It shows the address of the connection destination on the output connection list 430 that has the connection destination of the output signal line. Output connection list 43
0 will be described later. The input n signal value 428 indicates the signal value of the signal input to the logic element, and is created by the number n corresponding to the number n of the input lines.

The input n connection source element address 429 indicates an address indicating the connection source of the input signal line. Therefore,
For example, assuming that the input 1 signal of the logic element table 420 'is connected to the logic element specified in the logic element table 420, the input 1 connection source element address 429'-1 of the logic element table 420' Table 420
Shows the start address of the.

The output connection list 430 includes a connection element address 431 and a link pointer 432. The connection destination element address 431 indicates the address of the logic element table 420 ′ to which the output signal line of the logic element specified by the logic element table 420 is connected. In addition, in the case where there are a plurality of input terminals of the logic element of the connection destination, the number of the input terminal can be added to the connection element address 431 in addition to the address of the logic element of the connection destination. In some cases, the output line of one logic element is connected to a plurality of logic elements.
The address of the connection destination element after the third is the ring pointer 4
32. In the final ring pointer 432,
In the last record of the connection destination address 431 of the signal line, "
0 "is set to indicate the end of the record.

Next, an example of the specific contents of the logic circuit information table will be described with reference to FIG.

FIG. 5 is an explanatory diagram of an example of specific contents of the logic circuit information table stored in the simulation master file used in the logic verification method according to one embodiment of the present invention.

As shown, the signal name list 410 includes a signal line name 411, an output element address 412,
An initial signal value 413 is created. For example, a signal line whose signal line name 411 is “DATA0” corresponds to a logical element table 4 whose output element address 412 is indicated by “00000”
20 output from the output element of the address 20,
It is listed that the initial signal value 413 is “1”. Therefore, using “00000” described in the output element address, the logical element table 420A is used.
Can be linked to.

As shown in the drawing, the signal name list 410 includes all output signal lines “DATA” of the target logic circuit.
0 "," DATA1 ", ..." DATA0 "," PARI
TY0 "and" DATACHK0 ", and also describes the starting address of the logical element table of the logical element that outputs the signal line having the signal line name and the initial signal value of the signal line.

Here, the head address of the signal name list 410, that is, the address for “DATA0” is “1”.
0000 "and the address for" DATA1 "is" 10001 ".

The logic element table 420 is created by the number of logic elements constituting the target logic circuit. Therefore,
For the logic circuit shown in FIG. 2, as shown, the logic element table 420A stores the flip-flop 210-
0, and its start address is "00".
000. The logical element table 420B corresponds to the flip-flop 210-1, and its start address is set to "00100." It should be noted that the logical element table 420B corresponds to the flip-flops 210-2,. A logic element table is also created, but is not shown here.

The logic element table 420I corresponds to the flip-flop 220-0, and its head address is "03000". Logic element table 42
0J corresponds to the flip-flop 220-1, and its start address is “03100”. Note that a logic element table corresponding to the flip-flops 220-2,..., 220-7 is also created, but is not shown here.

The logical element table 420R corresponds to the parity generation circuit 240, and its leading address is "01000". Logical element table 420S
Corresponds to the parity check circuit 250, and its start address is set to “02000”. Further, the logic element table 420Q stores the flip-flop 2
30 and its start address is "0".
4000 ".

Next, the contents of the logic element table 420A will be described. The logic element table 420A corresponds to the flip-flop 210-0. Therefore,
In the item of the element function 421A, “FF” indicating the logical function of the element is described. The element delay 422A describes that it is 3 ns. Division number 42
No data is described in the item 3A. this is,
Since the flip-flop 210-0 is not the target of the logical block, the flip-flop 210-0 has no division number added thereto.

In the output signal value 424A, "1" is set as the output signal value of the logic element. This means that the signal name 411 of the signal name list 410 is set to “1” which is the initial signal value 413 for “DATA0”.
Note that the value of the output signal value 424A is the input signal value 428A.
Is determined according to the element function 423A of the logic element.

The address “10000” is set in the output signal name list address 425A. This address indicates an address on the signal name list 410 having the signal name “DATA0”.

The control flag 426A includes the control flag “C
FA ”is set. Since the setting of the control flag changes according to the control state, the details will be described later in the description of the operation of deleting the processing mode.

Output connection element list address 427A
Indicates the address “00090” of the connection destination on the output connection destination list 430A. Address "00090"
An output connection destination list 430A is created.

Since the input signal destination of the flip-flop 210-0 is one, one input signal value 428A is created. Here, it is indicated that the signal value of the signal input to the logic element is “0”. The input connection source element address 429A indicates an address “A3” indicating the connection source of the input signal line. The address “A3” is an address of a logic element table of an arbitrary logic element to which the input signal of the flip-flop 210-0 illustrated in FIG. 2 is connected.

Next, the output connection destination list 430A will be described. The head address of the output connection destination list 430A is “00090”. Output connection list 430A
Is the first connection destination element address 431
“03000” which is A is set. This address “03000” indicates the head address of the logic element table 420I of the flip-flop 220-0.
“1” is set in the ring pointer 432A, and indicates the next address “00091”. The address “00091” includes the second connection destination element address 43
“01000” which is 1A is set. This address “01000” indicates the head address of the logical element table 420R of the parity generation circuit 240. “1” is set in the ring pointer 432A, and
The next address “00092” is shown. The address “00092” includes the third connection destination element address 431
“02000” which is A is set. This address “02000” indicates the head address of the logical element table 420S of the parity check circuit 250.
“0” is set in the ring pointer 432A, indicating that it is the last record.

Other logic element tables 420B, 420
The same applies to the configuration of I, 420J. Logic element table 4
20B, 420I, and 420J each have an output connection destination list 430, but are not shown here.

Next, the logic element table 420R will be described. The logic element table 420R corresponds to the parity generation circuit 240. Therefore, element function 4
In the item of 21R, “parity generation” indicating the logical function of the element is described. The element delay 422R has 2
ns. In the item of the division number 423R, the division number “1” is set. A logic block is formed with another logic element having the division number “1”. Incidentally, the division number 423S of the logical element table 420S for the parity check circuit 250 also
The same division number “1” is set.

In the output signal value 424R, "0" is set as the output signal value of the logic element. This is because the signal name 411 of the signal name list 410 is “PARITY
“0” which is the initial signal value 413 for “0” is set. Note that the value of the output signal value 424R is the input signal value 4
28R and the element function 423R of this logic element.

The address "10008" is set in the output signal name list address 425R. This address indicates an address on the signal name list 410 having the signal name “PARITY0”.

The control flag 426R includes the control flag “C
F-R "is set. Since the setting of the control flag changes according to the control state, the details will be described later in the description of the operation of deleting the processing mode.

Output connection element list address 427R
Indicates the address “R1” of the connection destination on the output connection destination list 430R. An output connection destination list (not shown) is created at the address “R1”.

The input signal destination of the parity generation circuit 240 is
Since there are eight, eight input signal values 428R-0,42
, 428R-7 are created. Here, the input signal value 428R-0 input to the logic element is
"1", and the input signal values 428R-1,.
-7 indicates "0". Also, the input connection source element address 429R-0 indicates an address “00000” indicating the connection source of the input 1 signal line. The address “00000” is stored in the flip-flop 2 shown in FIG.
This is the address of the logical element table 420A for 10-0.

Next, the logic element table 420S will be described. The logic element table 420S corresponds to the parity check circuit 250. Therefore, in the item of the element function 421S, “parity check” indicating the logical function of the element is described. The other configuration is the same as that of the logic element table 420R. However, since there are nine input signals, nine input signal values 428S-
, 428S-8.

Next, the connection definition file information stored in the simulation master file 134 will be described with reference to FIG. FIG. 6 is a configuration diagram of the connection definition file information stored in the simulation master file used for the logic verification method according to one embodiment of the present invention.

The connection definition file information 600 includes an output signal line name 601, an output signal unique value 602, a division number 6
03 and a logical element table address 604.

Output signal line name 601 and output signal unique value 6
02 is the connection definition file 13 shown in FIG.
2 corresponds to the output signal line name 1322 specified in step 2 and its output signal unique value 1324.

The division number 603 is stored in the control definition file 132 by the circuit information division unit 114 of the logic compiler.
The logical block having the output signal line name specified in the above is extracted, and when the logical block corresponds to the logical element in the logical block, the same division number is set in each logical element table 420 and the connection definition file information 600. In the illustrated example, “1” is set as the division number. This division number is shown in FIG.
Are equal to the division numbers of the logic element tables 420R and 420S shown in FIG. Logical element table address 60
4 is a logic element table 42 having this output signal line name.
Address 0 is set. In the illustrated example, “DA
"02000" which is the address of the logic element table 420S of the parity check circuit that outputs "TACHK0"
Is set.

Next, the processing of the logic compiler 110 used in the logic verification method according to one embodiment of the present invention will be described with reference to FIG. FIG. 7 is a flowchart showing a processing procedure of a logic compiler used for a logic verification method according to an embodiment of the present invention.

In step 701, the logic compiling unit 112 of the logic compiler 110 reads the target logic circuit specified by the input parameter card 140 from the logic circuit file 130 and converts the connection information of each logic element from the described circuit information. Based on this, the logic circuit information table 400 shown in FIG. 4 is created. For the logic circuit shown in FIG. 2, the logic circuit information table 400 includes a signal name list 410 and a logic element table 42 as shown in FIG.
0A, 420B, ..., 420I, 420J, ... 420
Q, 420R, 420S and output connection destination list 430
A,.

At step 702, the circuit information analysis unit 114 of the logic compiler 110
A signal line name defined in 32 is read, and a logical block number is prepared for each signal line name. The corresponding signal name is extracted from the signal name list 410 of the created logic circuit information table 400, and the logic element table 420 indicated by the output element address 412 of the record is obtained.

For example, “DATACHK0” is read from the connection definition file 132 shown in FIG. 3 and, for example, “1” is prepared as a logical block number. Then, from the signal name list 410 shown in FIG.
ACHK0 ”is extracted, and a logical element table 420S indicated by the address“ 02000 ”is obtained.

In step 703, the circuit information analysis unit 114 determines that the element function 421 of the logic element table 420 registered in all the input connection source element addresses 429 of the extracted logic element table 420 indicates a flip-flop or an input port. Back trace to the logic element, and extract the connected logic element table group. That is,
All addresses of the searched logic element table 420 are stored in the logic compiler 110.

For example, the logic element table 4 shown in FIG.
20S input connection source element address 429S-0,..., 4
Logical element tables 420A, 420 registered in 29S-7
20B,..., 420R element functions 421A, 421B,
.., 421R are traced first. Element function 421
Since A, 421B,... Are flip-flops, these traces end. However, since the element function 421R of the logical element table 420R is a parity check circuit, the element function 421R further includes an input connection source element address 429.
, 429R-7, the element functions 421A, 421 of the logical element tables 420A, 420B,.
Trace B, ... Since these element functions are all flip-flops, the back trace is completed. Then, the searched logical element table 4
20S, 420R all addresses "02000",
“01000” is stored inside the logic compiler 110.

In step 704, the circuit information analysis unit 114 obtains the connection destination element addresses 431 from the logic element tables 420 other than the last stage of the addresses stored in step 703, and obtains all the corresponding connection destination element addresses 431.
Is registered at the address stored in step 703, that is, as the logical element in the target logical block, the logical block number is set in the division number 423 of the logical element table 420 and the division number 603 of the connection definition file information 600. .

For example, the output connection destination list 430 is obtained from the output connection destination element list address 427R of the logical element table 420R other than the last logical element table 420S shown in FIG. 5, and the connection destination element address 431R is obtained. Here, since the address is only “02000”, all the corresponding connection destination element addresses 431 are registered in the addresses stored in step 703. Therefore, the logical block number “1” is set to the division numbers 423R and 423S of the logical element tables 420R and 420S and the division number 603 of the connection definition file information 600.

At step 705, the circuit information analysis unit 114 outputs the created logic circuit information table 400 and the connection definition file information 600 as the simulation master file 134.

Next, the configuration of the processing mode list used in the logic simulation executing section 120 will be described with reference to FIG. FIG. 8 illustrates the configuration of the processing mode list used in the logic simulation execution unit in the logic verification method according to one embodiment of the present invention.

The processing mode list 800 contains the signal line name 8
01, an output signal unique value 802, a division number 803,
Logical element table address 804 and processing mode 805
It is composed of The signal line name 801, output signal unique value 802, division number 803, and logical element table address 804 are respectively the signal line name 60 shown in FIG.
1, an output signal unique value 602, a division number 603, and a logical element table address 604. The processing mode 805 specifies the type of processing of the target logical block, and includes a “verification execution mode” and a “verification execution mode”.
Delete mode (of the logic block of the failure check circuit) ",
And "unspecified mode".

Next, the processing of the logic development section 122 of the simulation execution section 120 will be described with reference to FIG. FIG. 9 is a flowchart illustrating a processing procedure of the logic developing unit of the simulation executing unit used in the logic verification method according to the embodiment of the present invention.

In step 901, the logic developing unit 122 of the simulation executing unit 120 reads the signal line name and the processing mode described in the control parameter card 142 and creates a processing mode list 800. The control parameter card 142 describes a plurality of signal line names and a processing mode for each signal line name. That is, since a plurality of failure check circuits are used in a large-scale logic circuit, they are connected to the control parameter card 14.
2 can be used to specify the processing mode at a time.
In step 901, the signal line name 801 and the processing mode 805 of the processing mode list 800 shown in FIG. 8 are set for each specified signal line name unit. That is, as shown in FIG. 8, for example, "DATAC" is added to the signal line name 801.
HK0 ”, and set the processing mode 805 to“ verification execution mode ”,“ deletion mode ”, or“ non-designated mode ”.

At step 902, the logical developing unit 12
2 reads the signal name list 410 shown in FIG. 4 and the connection definition file information 600 shown in FIG. 6 from the simulation master file 134 and develops them on the internal memory of the logical simulation execution unit 120. When the signal line name 801 existing in the processing mode list 800 matches the output signal line name 601 of the connection definition file information 600, the contents of the connection definition file information 600 are set in the corresponding processing mode list 800. That is, the output signal unique value 602, the division number 603, and the logical element table address 604 of the connection definition file information 600 in FIG. 6 are converted into the output signal unique value 80 in the processing mode list 800 shown in FIG.
2, division number 803, logical element table address 804
Set to.

Next, in step 903, the logic developing unit 122
4 is read from the logic circuit information table 400 shown in FIG.

In step 904, the logical developing unit 12
No. 2 determines whether or not the division number 423 of the logical element table 420 matches the division number 803 of the processing mode list 800, and further determines whether or not the processing mode 805 is “deletion mode”. Logical element table 420
If the division number 423 of the processing mode list 800 matches the division number 803 of the processing mode list 800 and the processing mode 805 is the “deletion mode”, the process proceeds to step 905; otherwise, the process proceeds to step 906. move on.

Step 905 is performed when the division number 423 matches the division number 803 and when the processing mode 805 is the “deletion mode”. In step 905, the logical expansion unit 122 does not expand the logical element table 420 of the logical block having the division number to be deleted in the memory, and stores the logical element table 420 of the previous stage indicated by the input connection source element address 429 of these logical element tables 420. The address of the logical element table 420 to be deleted is deleted from the connection destination element address 431 of the output connection destination element list address 427 of the logical element table 420.

For example, when the logical block having the division number “1” is to be subjected to the “delete mode”, the logical element tables 420 R and 420 S shown in FIG. Does not expand.
.. 429R-7 indicated by the input connection source element addresses 429R-0,... 429R-7 of the logic element table 420R, and the output connection destination list 430 from the output connection destination element list address 427 in the logic element tables 420A, 420B,.
A,... Are traced, and the connection destination device address 431A,
., The address “01000” of the logical element table 420R to be deleted is deleted. Similarly, the input connection source element address 429S of the logic element table 420S
-0,... 429S-7
The output connection destination list 430A,... Is traced from the output connection destination element list address 427 of the output connection destination element list 427A in the logical element table 420S to be deleted from the connection destination element addresses 431A,.
00 ”.

Step 906 is a process performed when the division number 423 does not exist in the processing mode list 800 or when the division number 423 matches the division number 803 and the processing mode 805 is the “verification execution mode”. It is. In step 906, the logical developing unit 122
The contents of the read logic element table 420 are directly expanded on the internal memory.

In step 907, the logical developing unit 12
2 judges whether reading of the logic circuit information table 400 has been completed or not, and if not completed, step 90
3, the operation of reading the logical element table 420 stored in the series of simulation master files 134 is repeated.

Step 908 is a processing mode list 80
0 is the initial setting processing of the logic element registered in the processing mode 805.
When 05 is in the “verification execution mode”, a different process is performed.

When the processing mode 805 is the “delete mode”, in step 908, the logic developing unit 122 sets the output signal value 802 to the output signal value of the logic element table 420 indicated by the logic element table address 804.

For example, as shown in FIG. 8, when the address of the logical element table address 804 is “02000”, the output signal value 4 of the logical element table 420S is
At 24S, “0” which is the output signal unique value 802 is set.

On the other hand, when the processing mode 805 is the “verification execution mode”, in step 908, the logical developing unit 122 reads the logical element table 420 indicated by the logical element table address 804, and The logical element table 420 having the same division number 423 is sequentially back-traced by using the input connection source element address 429, and an arbitrary input signal value 428 of the logical element table 420 which is the first stage of the logical block having the same division number 423 is obtained. A fixed value is set, and an input suppression flag of the target input terminal is set in the control flag 426 of the logical element table.

For example, the logic element table 420S of the address “02000” indicated by the logic element table address 804 shown in FIG. 8 is read, and the input connection source element addresses 429S-0,
, 429-8, the logical element table 420R having the same division number 423, "1", is sequentially backtraced.

Here, arbitrary input signal values 428R-0, 428R-1,..., 428 of the logical element table 420R which is the first stage of the logical block having the same division number 423.
A fixed value is set to R-7, and an input suppression flag of the target input terminal is set to the control flag 426 of the logical element table. That is, for example, the logic element table 420
The input signal value 428R-0 of R is suppressed, and a fixed value is set instead. Control flag CF-R
If the input suppression flag in is set to 8 bits, input 0
The input suppression flag corresponding to the signal value is set to “1”. Then, the input signal values 428R-0, 428R-1,.
When 8R-7 is, for example, “10000000”, the output signal value 424R of the logical element table 420R having the element function as the parity generation circuit is originally “0”. At this time, it is assumed that the input signal value 428R-0 is fixed to “0”. That is, the input signal value 428
R-0,428R-1, ..., 428R-7 are "000
00000 ", and the output signal value 424R becomes" 1 ". The input signal values 428R-1,..., 428R-7 other than the arbitrarily fixed input signal value 428R-0 are used to directly provide the input signal values for performing the logic verification of the entire normal logic circuit. . On the other hand, a logic element table 420S having an element function as a parity check circuit
, 428S-0, 428S-1,..., 428
S-7 is “1000000” because the input is not suppressed.
If "00" remains, the parity signal formed from these input signals will be "0". On the other hand, the input signal value 428S-8 is “1” because it is equal to the output signal value 424R of the logic element table 420R. Since the logic element table 420S having the element function as the parity check circuit does not match, the output signal value 424S does not match “1” as the output signal value 424S.
, It is possible to verify the logical operation of the fault check circuit including the parity generation circuit and the parity check circuit.

The input terminals to be fixed, that is, the input connection source element address 429 and the fixed value are stored in a file or the like as control information, and a different input terminal is selected using the information. Accordingly, it is possible to execute verification of all input terminals of a specific logic block.

Next, referring to FIGS. 10 and 11, the logic simulation section 12 of the simulation execution section 120 will be described.
The process 4 will be described. FIG. 10 is a flowchart showing a processing procedure of the logic simulation unit of the simulation execution unit used in the logic verification method according to the embodiment of the present invention. FIG. FIG. 4 is an explanatory diagram of a simulation table.

In step 1001, the logic simulation section 124 of the logic simulation execution section 120
Sets the simulation time to "0".

In step 1002, the logic simulation section 124 reads the signal value data file 136 at the simulation time “0”, and reads the logic element table 4 having the signal line name specified by the signal value data.
20 and the signal value of the simulation time “0” is set when the input inhibition flag of the control flag 426 of the preceding logical element table 420 indicated by the connection destination logical element address 431 of the logical element table 420 is not set. The connection destination element address 431 is registered as an event 1110 in the event table 1101 shown in FIG. The signal value data at the simulation time “0” is processed.

Next, in step 1003, the logic simulation section 124 reads the registered event 1110 at the simulation time “0”, and from the input signal value 428 of the logic element table 420 indicated by the event 1110 according to the element function 421. The output signal value is calculated, and when the output signal value changes, the output signal value is propagated to the input signal value 428 of the logic element table 420 indicated by the connection destination element address 431, and after the delay time indicated by the element delay 422. The connection destination element address is registered in the event table 1101 indicated by the simulation time.

In step 1004, the logic simulation section 124 performs all event processing at the simulation time “0”.

In step 1005, the logic simulation unit 124 determines that the processing mode 805 registered in the processing mode list 800 is the output signal value of the logic element table 420 indicated by the logic element table address 804 of the “verification execution mode”. When a mismatch occurs with the signal values in the processing mode list 800, the names of the signal lines and output signal lines connected to the input terminals of the corresponding logical block and the signal values are output in a list.

In step 1006, the logic simulation unit 124 sets the next simulation time by adding +1 to the simulation time.

In step 1007, the logic simulation unit 124 sets the control parameter card 1 in advance.
These simulation processes are executed until the simulation end time designated by 42.

In FIG. 11, a time wheel 1100
Is a management table for controlling the processing time of the event with respect to the simulation time. The current simulation time is set to 0 to indicate the relative execution time of the event, and the event 1110 indicated by the link pointer 1102 on the time wheel 1100 is the event to be processed at that time. The event 1110 has a link 1112 which is the address of the event 1110 to be processed at the same time as the address 1111 of the logical element table to be processed.

As described above, according to the present embodiment, the operation of the failure check circuit can be easily confirmed. That is, after expanding the entire logic circuit including the fault check circuit in the internal memory, the fault check circuit is extracted as a logic block using the logic number, and the input of an input signal to the logic element at the preceding stage of the logic block is suppressed. In addition, the operation of the failure check circuit can be confirmed by giving an arbitrary failure signal value. Also, the output signal value at the subsequent stage of the logic block is normally set to an output unique value that does not affect the logic operation, and therefore does not affect other logic circuits. Here, since the signal value for logic verification of the entire logic circuit is given except for an arbitrary signal value given to the failure check circuit, the operation of the failure check circuit can be easily checked.

Further, when executing the logic verification of the entire normal logic circuit, only the input suppression of the input signal is released.
The verification can be easily performed.

Further, according to the present embodiment, the logic verification time can be reduced. In other words, when a normal logic circuit is verified, a hardware failure or the like does not occur. Therefore, the failure check circuit itself is unnecessary. Since the operation verification of the check circuit itself is also performed, extra time is required for the logic verification. However, by using the deletion mode, the logic check of the remaining logic circuits can be performed after the fault check circuit has been deleted from the logic circuit, so that the logic verification time can be reduced. . When the failure check circuit is developed, signal value propagation processing for the failure check circuit itself is required, and the amount of events increases. However, these event amounts can be reduced, and the logic verification time can be shortened.

Further, since the failure check circuit does not need to be developed on the internal memory, the handling scale (memory capacity) at the time of logic verification can be reduced. Since a plurality of failure check circuits are provided on the logic circuit, the effect of reducing the scale of handling increases. In other words, it is possible to expand the scale of a logic circuit that can be developed for an internal memory having the same capacity.

[0116]

According to the present invention, it is possible to easily confirm the operation of the fault check circuit in the logic verification method.

Further, according to the present invention, it is possible to shorten the logic verification time in the logic verification method.

[Brief description of the drawings]

FIG. 1 is a system block diagram of a logic simulation device used for a logic verification method according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a logic circuit to be subjected to logic verification in a logic verification method according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a definition example stored in a connection definition file used in a logic verification method according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a configuration of a logic circuit information table stored in a simulation master file used in a logic verification method according to an embodiment of the present invention.

FIG. 5 is an explanatory diagram of an example of specific contents of a logic circuit information table stored in a simulation master file used in a logic verification method according to an embodiment of the present invention.

FIG. 6 is a configuration diagram of connection definition file information stored in a simulation master file used for a logic verification method according to an embodiment of the present invention.

FIG. 7 is a flowchart showing a processing procedure of a logic compiler 110 used for a logic verification method according to an embodiment of the present invention.

FIG. 8 illustrates a configuration of a processing mode list used in a logic simulation execution unit in a logic verification method according to an embodiment of the present invention.

FIG. 9 is a flowchart showing a processing procedure of a logic development unit of a simulation execution unit used for a logic verification method according to an embodiment of the present invention.

FIG. 10 is a flowchart illustrating a processing procedure of a logic simulation unit of a simulation execution unit used for a logic verification method according to an embodiment of the present invention.

FIG. 11 is an explanatory diagram of a simulation table at the time of executing a simulation in the logic verification method according to an embodiment of the present invention.

[Explanation of symbols]

 110 ... Logic Compiler 112 ... Logic Compile Unit 114 ... Circuit Information Dividing Unit 120 ... Logic Simulation Execution Unit 122 ... Logic Expansion Unit 124 ... Logic Simulation Unit 130 ... Target Logical Circuit File 132 ... Connection Definition File 134 ... Simulation Master File 136 ... Signal Value data file 138 Simulation result file 140 Input parameter card 142 Control parameter card 150 Simulation result list 400 Logic circuit information table 410 Signal name list table 420 Logic element table 430 Output connection destination list table 431 Output Connection destination list 600 Connection definition file information 800 Processing mode list 1100 Time wheel 1101 Event table 1110 Event

Claims (3)

[Claims] 1. A logic verification method in which a logic circuit including a fault check circuit is developed on a memory and its operation is verified. A) The same division number is added to each of the logic elements constituting the fault check circuit. By expanding the fault check circuit as a logic block by expanding the fault check circuit as a logic block, B) suppressing input of an arbitrary input signal among a plurality of input signals to the logic block specified by the division number A logic verification method for performing logic verification of the logic block by setting an arbitrary input signal value for the input signal. 2. The logic verification method according to claim 1, wherein the addition of the logic number is based on a connection definition signal that is an output signal of the failure check circuit, from a logic element that outputs the connection definition signal. This is performed by sequentially back-tracing other logic elements connected to the input signal of the logic element, extracting the logic block, and adding the same division number to the logic elements constituting the extracted logic block. A logic verification method characterized by the following. 3. A logic verification method for developing a logic circuit including a fault check circuit on a memory and verifying its operation, wherein: A) adding the same division number to each of the logic elements constituting the fault check circuit; By expanding the fault check circuit as a logic block by expanding the fault check circuit as a logic block, C) deleting the logic block specified by the partition number based on the partition number and removing the remaining logic circuit A logic verification method which is developed in the internal memory and inputs an output signal unique value corresponding to an output signal value of a logic block to be deleted as an input signal of the developed logic block.