JPH10150182A - Solid-state imaging device and solid-state imaging device application system - Google Patents

Abstract

(57) [Summary] To provide high sensitivity by increasing the photoelectric conversion gain in a unit cell, and to suppress noise jumping from a vertical signal line or the like to realize low noise. Kind Code: A1 A first and a second read transistor gate wirings and a first read transistor drain are formed between first and second diodes in an element region. . The drain 25 is connected to the gate 27 of the amplifying transistor via the jump wiring 26.
Connected to. The gate 27 of the amplification transistor is also connected to the source 31 of the reset transistor formed on the reset transistor element region 30 via the jump wiring 16. On the element region 30 of the reset transistor, a drain 33 is provided on a side opposite to the source 31 with the gate wiring 32 of the reset transistor interposed therebetween.
Are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device with high sensitivity and low noise. The present invention also relates to an application system using the solid-state imaging device with high sensitivity and low noise.

[0002]

2. Description of the Related Art Advances in semiconductor device technology have made video cameras smaller and lighter, more portable and easier to carry.
Widely used. In the case of an electronic device, a battery is used as a power supply in terms of portability, but a video camera has conventionally used a CCD sensor as an image sensor. However, the CCD sensor requires a plurality of voltages to drive the device, and requires a power supply circuit for generating the voltage from the battery voltage. This hinders further miniaturization of the video camera, and also hinders reduction in power consumption.

[0003] In order to make it easier to handle, research on reducing the size and weight of video cameras has been promoted, and a solid-state imaging device having a larger number of pixels has been developed so as to obtain high-quality images. However, in order to reduce the size and weight of the video camera, not only the size of the solid-state imaging device but also the appearance of a solid-state imaging device with low power consumption and low voltage is strongly required.

In order to simply reduce the size of the solid-state imaging device and increase the number of pixels, the pixels may be miniaturized. However, when pixels are miniaturized, there is a problem that the amount of signal charges handled per pixel decreases. As a result, the dynamic range of the solid-state imaging device is reduced, and there arises a problem that a clear high-resolution image cannot be obtained.

In the case of a CCD, since a plurality of types of voltages are used for driving the elements, a simple system cannot be used in terms of the configuration and handling of a camera system. In other words, for application to a portable camera or a camera mounted on a personal computer, it is desired that a solid-state imaging device with a single power supply having a good S / N and a low power consumption and a low voltage are required. However, a CCD cannot be driven by a single power supply and cannot not only reduce power consumption and voltage, but also cannot meet the above demand because the S / N becomes poor when pixels are miniaturized.

[0006] Then, looking for another device that satisfies the above requirements, a MOS sensor using an amplifying transistor has been proposed as a solid-state imaging device which can be driven by a single power supply with low power consumption and low voltage. is there.

This solid-state imaging device amplifies a signal detected by a photodiode in each cell by a transistor, and has a feature of high sensitivity.

[0008] Unlike a CCD sensor using a special manufacturing process, a MOS sensor is produced by a MOS process that is frequently used in semiconductor memories such as DRAMs, processors and the like. Therefore, the MOS sensor has advantages such as being formed on the same semiconductor chip as the semiconductor memory and the processor, and being easy to share a production line with the semiconductor memory and the processor.

However, a conventional MOS sensor (amplification type MOS sensor) using the above-described amplification transistor.
As the user demands higher resolution, that is, higher density and finer pixels, the problem of securing a high photoelectric conversion gain emerges. Further, as will be described later, a problem of luminance unevenness called fixed pattern noise remains. Therefore, how to improve them is a major issue.

Further, the dynamic range of the output of this amplification type MOS sensor is only about 60 dB, which is insufficient compared with 90 dB of a silver halide film and 70 dB of a CCD sensor. Therefore, incorporating this amplification type MOS sensor into an image system device such as a video camera has a practically great limitation in terms of image quality.

[0011]

As described above, in recent years, a solid-state imaging device using an amplification type MOS sensor (amplification type MOS solid-state imaging device) has been proposed as one of the solid-state imaging devices. This element has a characteristic that an optical signal detected by the photoelectric conversion storage unit is amplified very close to the photoelectric conversion storage unit.

FIG. 18 is a plan view of a conventional amplification type MOS solid-state imaging device, and FIG. 19 is a circuit diagram of a unit cell of the conventional amplification type solid-state imaging device shown in FIG. Hereinafter, FIG.
The operation of the amplification type solid-state imaging device will be described with reference to FIGS.

The signal charge generated as a result of the photoelectric conversion in the photodiode 1 is read out to the gate of the amplifying transistor 4 by turning the readout line 2 to a high level and turning on the readout transistor 3, thereby changing the gate potential.
The potential of the vertical signal line 5 changes according to the potential of the gate of the amplification transistor 4.

After reading the signal, the gate 7 of the reset transistor 6 is set to a high level to reset the gate potential of the amplification transistor 4 to a desired potential. Further, the address of the unit cell is performed using the address transistor 8 connected in series to the drain side of the amplification transistor 4.

In general, a photoelectric conversion gain g [V] in a unit cell of an amplification type solid-state imaging device having a readout transistor.
/ Electron] is given by the following equation.

[0016] Here, C _sn is the capacitance of the detection unit, and is the sum of the gate capacitance of the amplification transistor and the substrate capacitance of the drain of the read transistor. In reality, the capacitance of the detection unit is largely occupied by the substrate capacitance of the drain of the read transistor.

As described above, in order to increase the sensitivity of the solid-state imaging device, it is necessary to increase the photoelectric conversion gain of the unit cell. It is necessary to reduce the substrate capacity of the drain.

As shown in FIG. 18, conventionally, there is only one element forming region constituting the drain capacitance, the area is large, and a quite high photoelectric conversion gain cannot be obtained. In particular, in the example shown in FIG. 18, since the reset transistor 6 for resetting the potential of the gate of the amplification transistor 4 is connected to the drain of the read transistor 3, the substrate capacitance of the drain of the read transistor 3 increases. It has the problem of being easy.

Another disadvantage of the above-mentioned conventional example is that the drain of the read transistor 3 is almost completely surrounded by an element isolation region. Since the substrate concentration is generally high under the element isolation region, if the portion where the drain is in contact with the element isolation region is large, the parasitic capacitance at that portion increases, resulting in deterioration of the photoelectric conversion gain and sufficient dynamic range. There is a problem that it cannot be secured.

FIG. 20 is a plan view of a unit cell showing another example of the conventional amplification type solid-state imaging device. FIG. 21 is a sectional view taken along line AA 'of the solid-state imaging device shown in FIG. It is sectional drawing along.

This solid-state imaging device has a photodiode 1
Reference numeral 0 denotes a base of an NPN bipolar transistor, an N-type substrate 11 includes a collector, and a vertical signal line 12. The signal charge generated as a result of the photoelectric conversion in the photodiode 11 is read out to the vertical signal line 12 by setting the control gate 13 to a high level to make a forward bias between the base and the emitter. After the signal is read, a sufficiently negative voltage is applied to control gate 13 to reset the base potential to a desired potential.

Incidentally, in order to reduce the noise of the solid-state imaging device, it is necessary to suppress noise contamination before input to the amplifying transistor constituted by the NPN transistor. However, the control gate 13 for addressing a certain line covers only a part of the base region. For this reason, noise jumps into the base region from the vertical signal line 12 or the like made of Al. For this reason, this is a major obstacle to reducing the noise of the solid-state imaging device.

As described above, conventionally, the electrode on the control electrode side of the amplifying transistor forming the capacitor for selecting the unit cell is not completely covered with the vertical selection line.
There has been a problem that noise from a vertical signal line or the like via a parasitic capacitance is apt to jump in and S / N is poor.

Therefore, according to the present invention, it is possible to increase the photoelectric conversion gain in the unit cell to increase the sensitivity, and to suppress noise from entering the gate of the amplification transistor from the vertical signal line or the like via the parasitic capacitance. It is an object of the present invention to provide a solid-state imaging device capable of achieving low noise.

Further, the present invention relates to such an amplification type MO.
To provide an application system using the solid-state image sensor of the S sensor, and to improve the gain problem and the noise problem of the solid-state image sensor of the amplifying MOS sensor to be incorporated in image system equipment such as video cameras. It is to provide an application system that can be put to practical use.

[0026]

In order to achieve the above object, the present invention is configured as follows.

(1) That is, the present invention firstly provides an amplifying transistor for outputting a signal based on the potential of a control electrode, a photodiode provided adjacent to the amplifying transistor, and a control electrode of the amplifying transistor. In a solid-state imaging device provided with a plurality of photoelectric conversion cells having a drain and a MOS-type read transistor formed using the photodiode as a source, the drain of the read transistor has a plurality of element formation regions. It is characterized by comprising.

(2) Secondly, the present invention provides a photoelectric conversion / accumulation unit, an amplifying transistor for inputting an output of the photoelectric conversion / accumulation unit to a control electrode, and a vertical selection capacitor capacitively coupled to the control electrode of the amplifying transistor. An imaging region in which unit cells each having a line and a reset transistor for resetting the potential of the photoelectric conversion storage unit are arranged in a two-dimensional matrix on a semiconductor substrate; a power supply line for the amplification transistor and the reset transistor; A plurality of vertical signal lines arranged in a first direction for reading the current of the amplification transistor; a plurality of horizontal selection transistors provided at one end of the vertical signal line; and a selection pulse signal sequentially applied to the gate of the horizontal selection transistor And a horizontal signal line for reading a signal current from the vertical signal line via the horizontal selection transistor. The body imaging apparatus is characterized in that it comprises a capacitance means having a lower electrode formed by the gate of the amplification transistor and an upper electrode formed by the vertical selection line and covering the lower electrode.

(3) Thirdly, the present invention provides a photodiode, a transfer transistor for transferring a signal of the photodiode, a detection unit for detecting a signal transferred by the transfer transistor, and a detection unit A unit cell comprising an amplifying transistor having a gate connected to a gate, addressing means for activating the amplifying transistor, and resetting means for discharging the signal of the photodiode, arranged in a matrix two-dimensionally on a semiconductor substrate In the imaging device, a potential barrier is formed between the detection unit and the drain of the amplification transistor, and the potential of the detection unit is changed to discharge electrons across the potential barrier to the drain to perform reset. It is characterized by the following.

(4) Fourthly, the present invention relates to a photodiode, an amplifying transistor for inputting a signal of the photodiode to a gate, address means for activating the amplifying transistor, and a signal for the photodiode. A unit cell having a reset transistor to be discharged,
In a solid-state imaging device arranged in a matrix two-dimensionally on a semiconductor substrate, the drain of the photodiode and the amplification transistor constitute the source and the drain of the reset transistor.

(5) Fifthly, the present invention provides an image pickup area formed by arranging unit cells having a photoelectric conversion unit and an amplification transistor on a semiconductor substrate in a two-dimensional matrix, and a readout row of the image pickup area. In a solid-state imaging device including a vertical selection unit for selecting and a signal line for reading out a signal of a signal of a row selected by the vertical selection unit, cells in odd-numbered rows and cells in even-numbered rows are different from each other. The conversion efficiency is set.

According to the present invention, the element forming region forming the drain of the read transistor is divided into a plurality of regions, and the area of the element forming region is small, so that the substrate capacity of the drain of the read transistor can be reduced. Therefore, the photoelectric conversion gain increases.

Further, according to the present invention, since the upper electrode on the control electrode side of the amplification transistor forming the capacitance for selecting the unit cell is completely covered with the vertical selection line, the vertical signal through the parasitic capacitance is provided. It is possible to suppress noise from entering from a line or the like. Therefore, a low-noise solid-state imaging device can be provided.

(6) Further, sixth, the present invention provides an optical system which receives an optical image from a subject and guides the optical image to a predetermined position, and converts the optical image guided to the predetermined position into pixel units. An image processing unit having a sensor for photoelectrically converting the optical image into an electric signal corresponding to the light amount of the optical image, and a signal processing unit for processing an output of the image processing unit into a predetermined form and outputting the processed signal; A photoelectric conversion element disposed at a position, and an output circuit including an amplification MOS transistor connected to the photoelectric conversion element and amplifying and outputting the output of the photoelectric conversion element, wherein the sensor comprises (1) (5) A solid-state imaging device application system using the solid-state imaging device according to any one of (1) to (5).

Further, the sensor further includes a photoelectric conversion element disposed at the predetermined position and an amplification MOS transistor connected to the photoelectric conversion element, and amplifies the output of the photoelectric conversion element at a first timing. An output circuit for outputting a noise irrelevant to the output of the photoelectric conversion element at a second timing, and connected to an output of the output circuit;
A noise removing circuit for obtaining a difference between outputs of the output circuit at the first and second timings.

According to the present invention, the photoelectric conversion gain in the unit cell can be increased to increase the sensitivity, and
A low-noise, high-quality, high-dynamic-range solid-state imaging device application system capable of suppressing noise from a vertical signal line or the like into the gate of the amplification transistor via a parasitic capacitance and achieving low noise can be obtained. Furthermore, even when the fixed pattern noise of the amplification type MOS sensor becomes a problem, it can be removed to provide a solid-state imaging device application system with high dynamic range and high image quality.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a plan view of a unit cell of a solid-state imaging device according to a first embodiment of the solid-state imaging device of the present invention. In the embodiments described below, the same portions are denoted by the same reference numerals and description thereof will be omitted.

In FIG. 1, an element region 20 is provided in a unit cell.
First and second diodes 21 vertically adjacent to each other
And 22 are provided. First photodiode 2
1, a gate wiring 2 of the first read transistor
3 is provided with a gate wiring 24 of the second read transistor above the second photodiode 22.
The first line between the gate lines 23 and 24 is
Of the read transistor is formed.

The drain 25 is electrically connected to a gate 27 of the amplification transistor via a jump wiring 26. The drain 28 of the amplification transistor is connected to a power supply line (not shown) via a contact, and the source 29 of the amplification transistor is connected to a vertical signal line (not shown) via a contact. Further, the gate 27 of the amplification transistor is also electrically connected to the source 31 of the reset transistor formed on the element region 30 of the reset transistor via the jump wiring 16. On the element region 30 of the reset transistor, a drain 33 is formed on a side opposite to the source 31 with the gate wiring 32 of the reset transistor interposed therebetween.

Reference numerals 31 'and 32' denote the source and gate wirings of the reset transistors of the adjacent cells, respectively.

Next, the operation of the cell thus constructed will be described.

The signal charge generated by photoelectric conversion in the first photodiode 21 formed in the element region 20 is:
By applying a pulse for turning on the read transistor to the gate wiring 23, the read is performed to the drain 25 of the first read transistor. Since the drain 25 is electrically connected to the gate 27 of the amplification transistor, the potential of the gate 27 of the amplification transistor changes as the signal charges are read. Further, the potential of the vertical signal line is changed by the change in the potential of the gate 27 of the amplification transistor. This change in the potential of the vertical signal line becomes the output of the photodiode 21.

After reading out the signal charges, the potential of the gate 27 of the amplification transistor is reset to a desired potential. Similarly, the signal charge generated by the photoelectric conversion in the second photodiode 22 is read out to the drain 25, and then the potential of the vertical line is changed by using an amplification transistor, and is taken out.

In the first embodiment, the substrate capacitance of the drain of the read transistor is substantially the sum of the gate capacitance of the gate of the amplification transistor and the substrate capacitance of the source of the reset transistor. However, the element isolation region 20 that forms the drain of the read transistor and the element formation region 30 that forms the source of the reset transistor
Are not directly connected and are separated by the LOCOS area,
It is electrically connected via the jump wiring 16 to prevent the substrate capacity from becoming unnecessarily large.

Further, in this embodiment, the drain of the read transistor is surrounded by two types of gate wirings of the read transistor, and has a short peripheral length in contact with the element isolation region and a small parasitic capacitance. Have.

As described above, according to the first embodiment,
The element formation region of the drain of the read transistor is LOC
Since the OS region is divided into a plurality of regions, the area of the element formation region is reduced, and the substrate capacitance of the gate of the amplification transistor is reduced. Therefore, a unit cell having a high gain of the amplification transistor can be obtained.

The drain of the read transistor is
The periphery is surrounded by the gate wirings of two types of read transistors, and a unit cell having a short peripheral length in contact with the element isolation region, a small parasitic capacitance, and a high gain of the amplification transistor can be obtained.

Next, a second embodiment of the present invention will be described.

(Second Embodiment) FIG. 2 is a plan view of a unit cell of a solid-state imaging device according to a second embodiment of the present invention.

In FIG. 2, a unit cell includes an element region 3
5 and a first and second diode 3 vertically adjacent to each other.
6 and 37 are provided. Below the first photodiode 36, a gate wiring 38 of the first read transistor is provided, and above the second photodiode 37, a gate wiring 39 of the second read transistor is provided. And, between these gate wirings 38 and 39,
A drain 40 of the first read transistor is formed.

The drain 40 is electrically connected to the gate 42 of the amplification transistor via the jump wiring 41. The drain 43 of the amplifier transistor is connected to a power supply line (not shown) via a contact, and the source 44 of the amplifier transistor is connected to a vertical signal line (not shown) via a contact. Further, the gate 42 of the amplification transistor is also electrically connected to the source 46 of the reset transistor formed on the element region 45 of the reset transistor via the jump wiring 41. On the element region 45 of the reset transistor, a drain 48 is formed on the opposite side of the source 46 with respect to the gate wiring 47 of the reset transistor.

Reference numeral 49 denotes a gate wiring of the address transistor.

Next, the operation of the solid-state imaging device will be described with reference to the circuit diagram of FIG.

The signal charge generated by the photoelectric conversion in the photodiode 50 is read out to the gate 42 of the amplification transistor 53 by turning the readout line 51 high and the readout transistor 52 being turned on, and the potential of the gate is reduced. Change. The potential of the vertical signal line 54 changes according to the potential of the gate 42 of the amplification transistor 53.

After the signal is read, the gate 47 of the reset transistor 55 is set to the high level, and the gate potential of the amplification transistor 53 is reset to a desired position. Also, the address of the unit cell is the
This is performed using the address gate wiring 49 capacitively coupled to the gate of the third by the capacitor 56.

FIG. 4 is a partial sectional view of a unit cell of the solid-state imaging device shown in FIG.

In FIG. 4, an n-type impurity diffusion layer 59, a LOCOS region 60, a gate oxide film 42,
An interlayer insulating film 61 is formed. The n-type impurity diffusion layer 59 is connected to a jump wiring 41 as a lower electrode formed on the interlayer insulating film 61 via a contact 42a. The jump wiring 41 is entirely covered with the vertical selection capacitor insulating film 62. Further, on the vertical selection capacitor insulating film 62,
An address gate wiring 49 as an upper electrode is formed.

As described above, in this embodiment, the lower electrode 4 electrically connected to the gate 42 of the amplification transistor
1 is completely covered by the vertical selection capacitor insulating film 62, so that noise from a vertical signal line or the like via a parasitic capacitance is less likely to enter. For this reason, it is advantageous for low noise of the solid-state imaging device.

In the second embodiment, a unit cell in which the upper electrode and the lower electrode forming the address capacitance are formed by self-alignment and the edges are aligned is desirable. In this case, variation in capacitance can be reduced. When the variation in capacitance is small, a solid-state imaging device with less sensitivity unevenness can be configured.

By the way, the cell pattern of a basic amplification type solid-state imaging device (Ando, Kawashima, Tanaka et al.
Vol.49, No.2, pp.188-195 (1995))
It is configured as shown in FIG. FIG.
FIG. 2B is a circuit diagram of one cell corresponding to FIG.

In FIGS. 5A and 5B, a photodiode and a source / drain of a transistor are formed in an active region 65. Element isolation regions 66 are formed in portions other than the active regions 65. The photodiode 67 is electrically connected to the gate of the amplification transistor 68, and the current of the amplification transistor 68 is modulated by the potential of the photodiode 67. Thereby, the signal of the photodiode 67 is read out.

Since a large number of these cells are arranged two-dimensionally, an address transistor 69 for selecting a row is provided. Since the current flows through the amplification transistor only in the row where the address transistor 69 is turned on,
Thereby, a desired row can be selected.

The reset transistor 70 is provided to reset the signal of the photodiode 67. The optical signal passes through the reset transistor 70 and is discarded to the drain 68D of the amplification transistor. In this example, the gate of the reset transistor 70 is shared with the address gate of the pixel on one row. Further, the drain 68D is shared with the drain of the amplification transistor in this example.

Although the drain wiring is not shown here for the sake of simplicity, it is made of a first layer of aluminum (1A1) in the horizontal direction in the figure. Also,
The signal line Sig is provided in the vertical direction in the second layer of aluminum (2Al), as shown by the line in the drawing.

Here, it is assumed that the detection unit 71 is a part electrically connected to the gate of the amplification transistor 68. That is, the detection unit 71 is a part that directly determines a signal read out of the cell. For example, in FIG. 5A, the active region is on the left side of the reset transistor 70.
In (b), the thick line part is the detection unit 71.

FIG. 5C shows another example of the cell circuit.

Here, the electrons of the photodiode 67 are transferred to the detector 73 through the transfer transistor 72. The reason for this is not described in detail, but is to remove kTC noise or to perform a synchronous operation. Addressing is performed by an address capacitor 74 instead of a transistor. That is, the potential of the node of the address capacitor 74 on the side opposite to the detection unit 72 is increased or decreased, and the detection unit potential, that is, the amplification gate potential is increased or decreased by capacitive coupling to select a row.

The drain of the amplification transistor 68 and the drain of the reset transistor 70 may be different.

As described above, the conventional basic amplification type solid-state imaging device has a problem that it is difficult to miniaturize the device because the number of transistors per cell is large. For example, in a CCD which is a general solid-state imaging device at present, a cell having a side of about 7 μm is practically used with a design rule of about 0.8 μm. On the other hand, in the case of the example shown in FIG.
13.5 μm in height and 17.0 μm in width with m design rules
It has become.

As described above, it has been extremely difficult to realize a fine cell such as a CCD with the basic configuration of the amplification type solid-state imaging device. Further, if a transfer gate is added, it becomes more difficult to miniaturize.

Further, the basic amplifying solid-state imaging device has a high height from the silicon substrate. Since the drain wiring and the signal line are wirings through which a current flows, both require a metal wiring having a low resistance, particularly the A1 wiring in the current technology. In the example shown in FIG. 5A, 1AI is used for a drain wiring and 2A1 is used for a signal line. Further, for practical use, a light-shielding film for blocking incident light other than the photodiode is required, and it is necessary to form this with a third-layer metal (for example, 3Al). This further increases the height of the device from the silicon substrate.

As the height increases, it becomes difficult to form color filters and microlenses provided on the device. In addition, if the light-shielding film is located at a high position, the accuracy of light-shielding naturally deteriorates. Furthermore, the more wiring layers, the longer the manufacturing process. For CCD, aluminum wiring is 1
The amplification type solid-state imaging device is disadvantageous in comparison with this because the number of layers is sufficient.

Further, in the amplification type solid-state imaging device, when a large amount of light is incident on a certain photodiode, the photoelectrically converted electrons overflow from the photodiode and are absorbed by the photodiodes of the surrounding cells, thereby causing blooming.
When this blooming occurs, there is a problem because even if there is no light in the surrounding cells, the state becomes the same as that in which light has entered. In the case of the amplification type solid-state imaging device having the above-described basic configuration, blooming is likely to occur because the photoelectrons of the photodiode cannot be reset during a period when the signal potential must be held in the amplification gate.

Hereinafter, an example of an amplification type solid-state imaging device in which blooming is prevented while miniaturization of the cell is performed and the height of the device from the silicon substrate is not increased.

First, an embedded transistor is used as reset means in order to create a finer cell in which a transfer gate is introduced. The operation principle of the embedded transistor is described with reference to FIGS.

FIG. 6A is a plan view of an embedded transistor. Detector 77 and drain 78 on active region 76
In between, an ion implantation region 79 exists. This portion is a portion where a wiring serving as a gate is present when resetting is performed by a MOS transistor as in the related art. This is advantageous for miniaturization because only the setting of the channel potential of the ion-implanted region 79 is performed by ion-implantation without forming a wiring in the ion-implanted region 79.

FIGS. 6 (b) to 6 (d) are potential diagrams of the above-mentioned parts during the signal holding period, the reset period, and after the reset, respectively, and are shown with the positive direction facing downward.

As shown in FIG. 6B, signal electrons are present in the detection section 77 during the signal holding period. And FIG.
As shown in (c), the reset of the signal is performed by the detection unit 7.
By operating the potential on the negative side to the negative side, electrons having energy equal to or higher than the channel potential of the ion implantation region 79 are discharged to the drain. Detection unit 77
Can be performed by swinging the voltage of the wiring having the capacitive coupling with the detection unit 77 in the negative direction. After reset,
As shown in (d), the reset is completed by returning the potential of the detection unit 77 to the original state.

As described above, the use of a buried transistor is advantageous for miniaturization. After adopting this embedded transistor, the most efficient planar cell pattern is that the direction of the current when the optical signal is transferred from the photodiode to the detector and the direction of the current in the amplifying transistor are parallel and opposite. The reset is performed by connecting the detection unit and the drain of the amplification transistor in a direction perpendicular to the reset direction.

That is, the active regions are preferably arranged as shown in FIG.

In FIG. 7, the gate of the transfer transistor 72 is provided as shown by a horizontal solid line in the figure. Further, the gate wiring from the detection unit 77 to the amplification transistor 68 is connected to either the left or right amplification transistor 68 as indicated by the arrow in the drawing. If, for example, an address wiring having capacitive coupling is passed over the gate, a row can be selected by raising or lowering the potential of the amplification gate by this wiring, and a new effect can be obtained. , The potential of the embedded reset transistor 70 can be operated.

As described above, the gate wiring is provided above and below the reset transistor 70, and the reset transistor 70
Is a buried transistor which does not require a gate wiring, so that a most efficient planar cell pattern can be formed.

Next, consider sharing the light-shielding film with the drain wiring. As a method of lowering the height from the silicon substrate, a light-shielding film and a wiring can be shared. Especially,
It is preferable to use the drain wiring as a light shielding film. The reason is,
The wiring of the gate of the transistor is required to be given an electric potential independently for each row, and the signal line is required to be independent for each column, while the drain has the same electric potential in all pixels. Is allowed.

By covering a portion other than above the photodiode in the pixel portion with the metal wiring of the drain, the height of the device can be reduced, the number of manufacturing steps can be reduced, and light can be reliably shielded. it can.

Another method for lowering the height from the silicon substrate is
One method is to form the drain wiring and the signal line in the same wiring layer. Since the drain wiring is not necessarily independent in each row, if the drain wiring extends in the same direction as the signal line, the signal line and the drain wiring can be formed of the same metal wiring layer. Also in this case, since only two metal wiring layers are required together with the light-shielding film, the height of the depice can be reduced and the number of manufacturing steps can be reduced, so that light-shielding can be reliably performed.

Also, without using an embedded transistor,
In order to realize a reset transistor and an amplifying transistor using only ordinary MOS transistors, resetting is performed directly from a photodiode, and this drain is made to coincide with the drain of the amplifying transistor, whereby miniaturization is facilitated.

For example, the address by the capacitor 74,
When a transfer transistor is provided, the cell circuit is configured as shown in FIG. In particular, when the transfer transistor 72 is provided, it is preferable that the direction of the reset transistor 70 be orthogonal to both the transfer transistor 72 and the amplification transistor 68. This is purely due to pattern placement issues.By connecting the transistor directly to something you want to make big, such as a photodiode,
This is because the arrangement in a small area becomes easy.

In the structure of the cell having the transfer transistor 72 as shown in FIG. 8, in order to reset the signal charge transferred to the detection unit 77 through the transfer gate, both the transfer gate and the reset gate are turned on. Detection unit 77
Through the photodiode 67 to the drain. When the transfer gate is turned off and the reset gate is turned on, the photodiode 67 can be reset without affecting the signal of the detection unit 77.

Using this, the photodiode 67
Of the photodiode 67 is transferred to the detection unit 77, and then the photodiode 67 is reset. This prevents blooming in which electrons leak from the photodiode 67 when strong light enters during this period.

Next, a third embodiment of the present invention will be described.

(Third Embodiment) FIG. 9 shows a third embodiment of the present invention and is a cell pattern diagram of an amplification type solid-state imaging device.

In FIG. 9, the gate of the transfer transistor 72 is formed below the photodiode 67 in the horizontal direction. The signal charges are transferred from the photodiode 67 to the detection unit 77 through the transfer transistor 72. The gate of the amplification transistor 68 is connected to the detection unit 77.

On the right side of the detecting section 77, there is a region of an embedded reset transistor 70 for resetting. In this region, ion implantation for controlling the channel potential is performed. At the time of reset, the signal electrons are discarded from the detection unit 77 to the drain D through the embedded transistor 70. The drain is an amplifying transistor 68
Shared with the drain. The source side Sig of the amplification transistor 68 is connected to a signal line formed in the vertical direction.

In the above components, the direction of the current when the optical signal is transferred from the photodiode 67 to the detection unit 77 and the direction of the current in the amplification transistor 68 are parallel and opposite. And the reset transistor and 7
0 is performed by connecting the detection unit 77 and the drain of the amplification transistor 68 in a direction perpendicular to these directions.

Addressing is performed using an address capacitor 74. The address capacitor 74 is formed as a capacitance between the gate of the amplifying transistor 68 and an address gate line linearly and horizontally passed thereover.
Here, the address gate wiring is omitted because the figure becomes complicated.

The address capacitor 74 is also used for resetting by the embedded reset transistor 70 by raising and lowering the potential of the detection unit 77.
The signal line is made of a first-layer metal wiring, but the drain wiring is shared with the light-shielding film 80 by covering a portion other than above the photodiode 67 with the second-layer metal wiring.

With this configuration, a cell having a side of 5.5 μm and corresponding to イ ン チ inch 330,000 pixels using a 0.7 μm design rule can be formed with a 16% aperture ratio of the photodiode 67 secured. Pixel miniaturization comparable to CCDs is achieved.

Next, a fourth embodiment of the present invention will be described.

FIG. 10 shows a fourth embodiment of the present invention and is a cell pattern diagram of an amplification type solid-state imaging device.

In FIG. 10, the signal charge of the photodiode 81 is sent to the detection unit 83 through the transfer transistor 82 on the right side in the figure. The gate of the amplification transistor 84 is connected to the detection unit 83.

The reset transistor 85 is arranged above the photodiode 81. The direction of the reset transistor 85 is perpendicular to both the transfer transistor 82 and the amplification transistor 84. In this example, the gates of the reset transistor 70 and the transfer transistor 82 are shared by the upper and lower pixels in the figure.

The reset of the photodiode 81 is performed by transferring the electric charge from the photodiode 81 to the drain D through the reset transistor 85.
The reset of the detection unit 83 is performed by discharging the electrons to the drain through the photodiode 81 by simultaneously turning on the gate of the transfer transistor 82.

The drain D is connected to the reset transistor 85
The drain is also used as a drain of the amplification gate, and is connected to a drain wiring formed in the illustrated direction. The source Sig of the amplification transistor 84 is connected to a signal line formed in the vertical direction.

The drain wiring and the signal line are arranged in parallel, and both are formed by the first-layer Al wiring. Although not shown in FIG. 10, a light shielding film made of a second layer of Al is formed on a portion other than the position of the photodiode 81. Further, the address is the same as that of the third embodiment, and the address gate wiring is not shown in FIG.

In this configuration, as in the third embodiment, a cell of 5.5 μm on a side corresponding to 万 inch and 330,000 pixels using a 0.7 μm design rule is used for the aperture ratio of the photodiode. % Can be created. Therefore, pixel miniaturization is achieved, which is as common as that of CCD.

The operation of the fourth embodiment will be described with reference to the timing chart of FIG.

In the timing chart of FIG.
The pulse of the gate of the transfer transistor 82 and the pulse of the gate of the reset transistor 85 in the case of the row arrangement are shown. Other pulses are omitted here because they are not essential and depend on circuits outside the cell section.

First, the transfer transistor 82 and the reset transistor 85 in all rows are applied to the period from time t _{1 to} t _2.
Is turned on, and the detection units 83 and the photodiodes 81 of all the pixels are reset. Then, at time t ₂ the transfer transistor 82 and reset transistor 85 in all the rows photoelectrons are turned off accumulation is started in the photodiode 81.

At time t ₃ , transfer transistors 8 in all rows
2 is turned on, and the electrons accumulated in the photodiode 81 until then are transferred to the detection unit 83. That is, t
Period of ₂ ~t ₃ is a light-receiving period.

At time t ₄ , the reset transistors 85 in all the rows are turned on, so that the photoelectrons flowing into the photodiodes 81 are discharged to the drains D. As a result, blooming does not occur even when strong light enters.

In the basic cell circuit as shown in FIGS. 5B and 5C, when the reset transistor is turned on, the signal electrons of the detecting section are reset. It cannot work.

At time t ₅ , the potential of the detection unit 83 in row 1 is read by the circuit outside the cell unit. Then, at time t _6, when the transfer transistor 82 of the row 1 is turned on detector 83 of row 1 is reset. Thereafter, at time t ₇ , the detection unit 8 in row 1 is operated by the circuit outside the cell unit.
The reset potential of 3 is read, and the difference from the above value is output as a true signal amount.

Next, at time t ₈ , the potential of detector 83 in row 2 is read by a circuit outside the cell section. Then, at time t _9, the transfer transistors 82 of the row 2 Once turned on, the detection section 83 of the line 2 is reset.

[0115] Further, at time t _10, the read potential which is reset detection unit 83 of the line 2 by the outer circuit of the cell unit, the difference between the value described above can be outputted as a true signal amount.

In this manner, signals of the entire screen are read.

Here, the case where the number of rows is 2 has been described as an example, but the present invention is not limited to the collector, and the same applies even when the number of rows is 3 or more.

Meanwhile, in making the cells finer, it is considered that signal lines and the like of adjacent cells are made common. However, as described above, when cells are arranged adjacent to each other and the openings on each cell are formed to have the same size, there is a portion that is partially blocked by a light-shielding film or an electrode. It is actually difficult to make all the sensitivities to light the same.

In order to improve this, the photoelectric conversion efficiency may be set to be different between adjacent rows or columns, for example, cells of odd-numbered rows and cells of even-numbered rows. Specifically, (1) the optical aperture ratio defined by the light-shielding film and other electrodes is provided so as to be different between the odd-numbered rows and the even-numbered rows.

(2) The collection efficiency of the photo-generated carriers in the photoelectric conversion unit in the semiconductor substrate is set to be different between odd rows and even rows.

FIG. 12 is a layout diagram of a light shielding film opening showing an example for improving the photoelectric conversion efficiency of such a cell. In the figure, for example, a light-shielding film opening 90 arranged in an odd-numbered row has a larger opening than an adjacent row, that is, a light-shielding film opening 91 arranged in an even-numbered row.

As described above, by previously forming the optical aperture ratios in adjacent rows to be different from each other, it is possible to equalize the sensitivity of the adjacent cells to the incident light.

FIGS. 13 (a), 13 (b) and 14 are layout diagrams showing an example in which the light-shielding film openings are made equal.

FIG. 13 shows an example in which the electrodes 92 other than the light-shielding films for the cells in the odd-numbered rows and the electrodes 93 other than the light-shielding films for the cells in the even-numbered rows are arranged in different areas.
Then, in FIG. 13A, each of the electrodes 92 and 93
Are formed so as to partially protrude from the corners of the light-shielding film opening 90. On the other hand, in FIG. 13B, the image electrodes 92 and 93 are arranged between adjacent cells in each row.

FIG. 14 shows an example in which an electrode 94 other than the light-shielding film shared by the cells of the odd-numbered rows and the even-numbered rows is arranged between the cells.

FIG. 15 shows a first example formed by changing the collection efficiency of the photo-generated carriers in the photoelectric conversion section in the semiconductor substrate. That is, the areas of the photodiodes 95a in the odd rows and the photodiodes 95b in the even rows are set to be different.

FIG. 16 shows a second example formed by changing the collection efficiency of the photo-generated carriers in the photoelectric conversion section in the semiconductor substrate. For example, in the odd-row photodiodes 95, another diffusion layer 96 is formed between them,
The diffusion layer 96 is provided between the photodiodes 95 in even rows.
Is not formed.

FIG. 17 shows a third example formed by changing the collection efficiency of the photo-generated carriers in the photoelectric conversion unit in the semiconductor substrate. That is, the diffusion layer 97 shared by the photodiodes 95 in the odd and even rows is formed between the photodiodes 95.

In the setting of the light-shielding film openings or the photodiodes shown in FIGS. 12 to 17, the odd-numbered rows and the even-numbered rows may be reversed.

As a result, the amplification type MOS solid-state imaging device can be miniaturized. In addition, the height of the solid-state imaging device is reduced, so that a color filter or a microlens can be easily attached, and light can be reliably shielded.

Next, an application example of the above-mentioned amplification type MOS solid-state imaging device will be described.

(Fourth Embodiment) An embodiment of an application device using the above-described high photoelectric conversion gain and low noise MOS solid-state imaging device (CMOS sensor) will be described.

As a solid-state image sensor, a CCD sensor is generally used. As shown in FIG. 22, the basic configuration of the solid-state imaging device includes an input unit I, a processing unit II, and an output unit III. The input unit I is a light receiving unit. The light receiving unit I has a configuration in which photodiodes constituting pixels are arranged for a plurality of pixels, and an electric signal is output from each pixel in accordance with the amount of received light. The processing unit II is a unit that reads out the signal of each pixel in order and cancels the noise.
III is a circuit for outputting a signal read from each pixel. In the case of a CCD sensor, a plurality of types of drive power sources are required, and it is difficult to save energy. In addition, when a battery is driven by a battery, a large-scale power supply circuit is required to generate a plurality of types of voltages.

In the present invention, a MOS sensor that can be driven by a single power supply is used in place of the CCD sensor, and the above-described MOS sensor of the present invention is used to achieve low noise and high image quality. An application system.

Although not a subject of the present invention, it is necessary to take measures against fixed pattern noise. In this case, an example in which a noise canceller circuit is provided in the processing unit in addition to the readout control circuit. Show. Thus, further energy saving, miniaturization, and high image quality can be achieved.

The MOS sensor used in the present invention is m ×
m in which n photodiodes are arranged in a matrix
A photo sensor (input unit) which is a MOS sensor having a configuration of × n pixels and in which m × n photodiodes are arranged in a matrix.
And a processing unit including a reading unit for sequentially reading signals from each photodiode constituting the light receiving unit, a noise canceller circuit unit, and an output unit for outputting the signal read by the processing unit.

The processing section is provided with a reading section and a noise canceller circuit according to the present invention. The MOS sensor used in the present invention separates a signal into a timing for extracting only a noise component and a timing for extracting a signal component on which a noise component is superimposed, and cancels the noise component. This is to obtain a signal component that does not exist. The noise canceller circuit can match the impedance when outputting only the noise component and when outputting the noise component and the signal component so that the noise can be canceled accurately. With the provision of such a noise canceller circuit, the MOS sensor used in the present invention is a high-performance MOS sensor capable of performing high-speed noise cancellation with low noise that has sufficiently reached a practical level.

When the MOS sensor used in the present invention is used as the solid-state imaging device, a sensor unit for performing photoelectric conversion in the MOS sensor and other circuits (I
V conversion circuit, AGC circuit, CLP circuit, ADC circuit)
Can be manufactured using a normal MOS process. Therefore, it becomes easy to form these circuits on the same semiconductor chip. In addition, power consumption can be reduced, and a video camera or the like can be driven by a single voltage, so that a power supply circuit is simplified and a battery can be easily driven.

(Fifth Embodiment) An application example of a system will be described. Various systems to which a MOS type solid-state imaging device which achieves low power consumption and low voltage and has a good S / N ratio and a single power supply will be described.

FIG. 23 shows a general configuration of an apparatus using a MOS sensor as an image detecting section. As shown in the figure, the optical system includes an optical system A1, a MOS sensor A2, and a signal application unit A3. The optical system A1 is a device for guiding an optical image to the MOS sensor A2, and specifically includes a lens, a prism, a pinhole, a dichroic mirror, a condensing optical fiber, a concave mirror, a convex mirror, a color filter, a shutter mechanism, a diaphragm mechanism, and the like. Are appropriately combined according to the use of the system.

The MOS sensor A2 converts the optical image guided by the optical system A1 into an image signal corresponding to the light amount,
This is an apparatus that outputs only signal components without noise by performing noise cancellation processing. The element of the noise canceling process of the MOS sensor A2 is a noise canceller circuit which is one of important elements which will be described in detail later.

The signal application section A3 is an apparatus for processing the output of the MOS sensor A2 subjected to the noise cancellation processing according to the form of the system. For example, when a video camera is assumed as a system, the signal application unit A3 is an application function unit that converts an image signal output from the MOS sensor A2 into a composite video signal of the PAL system or the NTSC system.

The MOS sensor A2 can be driven by a single power supply, and uses a photodiode as a light receiving unit for converting light into an electric signal. The photodiode is equivalent to a pixel, and a plurality of photodiodes are arranged in a matrix as in the related art. In order to miniaturize the pixel, the area of the photodiode is reduced, but the output is reduced. An amplifier (transistor) is provided corresponding to the pixel in order to amplify the small output. Noise generated by passing through the amplifier (transistor) (a noise component that cannot be avoided due to the characteristics of the amplification transistor) is used to reset the output of the photodiode of the MOS sensor A2, Holding the output signal (noise component) and using the held output signal (noise component) and the output signal (“signal component + noise component”) of the amplifier (transistor) before or after the reset operation By performing a processing operation such as a cancellation process for both, noise is canceled and only signal components are extracted.

The MOS sensor A2 has a configuration described later, so that an output signal having a voltage amplitude of about 10 mV or less and an output current of about 1 μA and having no 1 / f noise can be obtained. Furthermore, the dynamic range of the output of the MOS sensor A2 is improved to 70 dB or more, which is almost the same as that of the CCD sensor, and by performing appropriate signal processing, the dynamic range of 90 dB is almost the same as that of a silver halide film.
B can be further improved.

As a result, a single power supply and high sensitivity amplification type M
Various systems using an OS sensor as an imaging device can be realized, low power consumption and low voltage can be achieved, and an amplification type MOS solid-state imaging device (amplification type MO) having a good S / N ratio.
S sensor) can be provided.

(Sixth Embodiment) <Application of Amplified MOS Sensor to Video Camera> FIG.
FIG. 1 shows an embodiment of a video camera using a MOS sensor according to the present invention. As shown in FIG. 25, a video camera 100 according to the present invention includes a lens 101 which is an optical system for capturing a subject image, a focus adjustment mechanism 102 for adjusting the focus of the optical system, and a diaphragm mechanism for adjusting the amount of incident light of the optical system. A diaphragm adjustment / focus adjustment circuit 103 for controlling the focus adjustment mechanism 102 and an MOS sensor 10 which is an image sensor that converts an optical image formed by the lens 101 into an electric signal corresponding to the light amount of the optical image in pixel units.
5. A color filter array 104 provided on the imaging surface side of the MOS sensor 105 and having one of RGB color filter units for each pixel, and a current-to-voltage conversion for converting an electric signal obtained by the MOS sensor 105 into a voltage signal. Circuit 1
06, AGC circuit 107 for adjusting the level of the voltage signal obtained through current / voltage conversion circuit 106, AGC circuit 10
7, a clamp circuit (CLP) 108 for clamping a voltage signal whose level has been adjusted, an analog-to-digital converter (ADC) 109 for converting an output from the CLP 108 to a digital signal corresponding to a level, and timing as a basic operation of the system. A timing control circuit 110 for generating a timing pulse (clock signal), and a TG / SG circuit 1 for controlling the driving of the MOS sensor 105 in synchronization with the clock signal output from the timing control circuit 110
11, a process control circuit 112 for processing a digital signal output from the ADC 109, an encoder circuit 113 for encoding a signal processed by the process control circuit 112, an output circuit 114 for outputting the encoded signal, and an output circuit A digital-to-analog conversion circuit 115 converts a signal output via 114 into an analog signal.

In the video camera 100 having such a configuration, light from the subject passes through the lens 101 to the MOS camera.
The light incident on the sensor 105 is converted into an electric signal by photoelectric conversion and output as a current value. A color filter array 104 in which red, blue, and green color filters are regularly arranged on the MOS sensor 105 corresponding to each pixel.
Is formed, whereby one MOS sensor 1 is formed.
From 05, color image signals corresponding to the three primary colors are output as electric signals.

The electric signal output from the MOS sensor 105 is supplied to a current-voltage conversion circuit 106, an AGC circuit 107,
The signal is supplied to the ADC circuit 109 via the LP circuit 108.

The ADC circuit 109 converts, for example, digital data having one sample value of 8 bits based on the image signal from the CLP circuit 108, and supplies this data to the process control circuit 112.

The process control circuit 112 includes, for example, a color separation circuit, a clamp circuit, a gamma correction circuit, a white clip circuit, a black clip circuit, a knee circuit, and the like.
Process processing is performed on the supplied video signal as necessary. If necessary, processing such as color balance is performed.
The signal processed by the process control circuit 112 is sent to the encoder circuit 113.

The encoder circuit 113 calculates the transmitted signal and converts it into a luminance signal and a color difference signal. Also,
When the video camera output is communicated via a network or the like, the encoder circuit 113 uses PAL or NTS.
A process of converting the composite video signal into the C format or the like is performed.

The MOS sensor 105 and the current / voltage conversion circuit 106 are provided with a TG / SG (timing generator /
The timing is controlled by a timing signal and a synchronization signal sent from a signal generator (CIR) circuit 111. The operating power supply and output voltage of the TG / SG circuit 111 are as follows:
This is the same as the power supply level supplied to the MOS sensor 105.

Thereafter, the video signal is applied to a D / A conversion circuit 115 via an output circuit 114, and the D / A conversion circuit 115 converts the input signal into an analog video signal and outputs it as a camera signal. . Further, the video signal can be directly output as a digital signal via the output circuit 114. These camera signals are supplied to a recording device such as a video tape recorder or a monitor device.

In this embodiment, in a video camera which requires low power consumption and low voltage and needs to process an image of 30 frames per second, a fixed pattern noise component is canceled within a horizontal blanking period. S /
A video camera capable of obtaining a high-quality image signal with good N can be provided.

In this embodiment, the color filter array 104 and the MOS sensor 10 as an image pickup device are used.
5 used a separate structure, but recently, C
Taking a CD device as an example, there are many devices in which an imaging device and a color filter are integrated. Therefore, a color filter array 104 and a MOS sensor 105 may be used in an integrated configuration. The imaging device in which the color filter array 104 and the MOS sensor 105 are integrated may be configured as shown in FIG.

That is, a light-shielding mask having an opening in the region of each photodiode light receiving surface is provided on each photodiode light receiving surface side of a semiconductor substrate Sub in which a large number of fine photodiodes PD are arranged in a matrix. A light-shielding film Mst is formed of, for example, aluminum, a transparent smooth film Mft is formed thereon, and a cyan filter FCy, a magenta filter FMg, and a yellow filter FYe are further formed thereon.

The photodiode PD has a M for magenta image.
g, G for green image, Ye for yellow image, C for cyan image
The cyan filter FCy is on the light receiving surface of the photodiode for the green image and the cyan image, the magenta filter FMg is on the light receiving surface of the photodiode for the magenta image, and the yellow filter FYe is the yellow image. And formed on the light receiving surface of the photodiode for use. Then, a transparent overcoat layer O is formed on the upper surface.
c, and a microlens array Lmc is formed thereon. The micro lens array Lmc is formed by arranging a large number of minute lenses, and each minute lens portion is designed to be on the light receiving surface of the photodiode PD. The microlens array Lmc secures the amount of light incident on the photodiode PD and increases the detection sensitivity of the photodiode PD.

If such a color filter / integrally formed image pickup device is used as an image pickup element (MOS sensor 105) of a single-plate image pickup system, it is not necessary to separately provide a color filter, and the light reception of the MOS sensor 105 is eliminated. The alignment of the color filter with respect to each pixel on the surface can be omitted, and the space of the optical system can be saved.

(Seventh Embodiment) <Application of Amplified MOS Sensor to Video Camera> FIG.
FIG. 14 shows another embodiment of a video camera using a MOS sensor according to the present invention. In the example shown in FIG. 26, while FIG. 25 is a single-chip imaging system, the imaging system is configured by RGB (red, green,
This is an example of a three-panel video camera divided into three systems (blue). As shown in FIG. 26, the video camera 100 of the present invention
-2 is a lens 10 which is an optical system for capturing a subject image
1. A focus adjustment mechanism 102 for adjusting the focus of the optical system, an aperture mechanism 116 for adjusting the incident light amount of the optical system, an aperture adjustment / focus adjustment circuit 103 for controlling the focus adjustment mechanism 102, and the optics captured by the lens 101. Color separation prisms 201R, 201G, and 201B for separating an image into three primary color components of RGB. Images separated into three primary color components of RGB are formed by these color separation prisms 201R, 201G, and 201B, and the light amount of the optical image in pixel units. R which is an image sensor for converting to a corresponding electric signal
MOS sensors 105R for the component, the G component, and the B component,
105G, 105B, these MOS sensors 105R, 1
The current-voltage conversion circuits 106R, 106G, 106B and the current-voltage conversion circuits 106R, 106G, 106B for the R component system, the G component system, and the B component system for converting the electric signals obtained by the 05G and 105B into voltage signals. AGC circuits 107R and 107G for the R component system, the G component system, and the B component system for adjusting the level of the voltage signal obtained by
A clamp circuit (CLP) 108R, 108G, 108B, CLP 1 for an R component system, a G component system, and a B component system for clamping voltage signals whose levels have been aligned via 107B and AGC circuits 107R, 107G, 107B.
08R, 108G, 108B for the R component system for converting the output from the digital signal corresponding to the level, for the G component system,
Analog-to-digital converter (ADC) 1 for B component system
09R, 109G, 109B, a timing control circuit 110 for generating a timing pulse for taking a basic timing of the operation of the system, and the timing control circuit 110
MOS sensor 1 in synchronization with the timing pulse output from
05 for R component system, G component system, B
TG / SG circuit 111 for component system, ADC 109
A process control circuit 112 for processing digital signals output from the R, 109G, and 109B, an encoder circuit 113 for encoding a signal processed by the process control circuit 112, and an output circuit for input / output control of the encoded signal. 114, output circuit 114
And a digital-to-analog conversion circuit 115 for converting a signal output through the digital-to-analog converter into an analog signal.

The video camera 100-2 having such a configuration is described.
, The light from the subject passes through the lens 101, passes through the color separation prisms 201R, 201G, 201B, and
An image is formed on the OS sensors 105R, 105G, and 105B.

These color separation prisms 201R, 201R
G and 201B decompose the optical image into three primary color components of RGB, and separate the color separation prisms 201R and 201B.
G and 201B decompose the image into three primary color components of RGB.
The image is formed on 05G and 105B.

MOS sensors 105R, 105G, 105
The R component, G component, and B component optical images formed on B are photoelectrically converted into current signals, and are output as current values corresponding to brightness.

MOS sensors 105R, 105G, 105
The electric signals for each component output from B are converted into current-voltage conversion circuits 106R, 106G, 106B for each component, AGC circuits 107R, 107G, 107B, and a CLP circuit 108.
R, 108G, 108B, ADC circuit 109R,
109G and 109B.

ADC circuit 109R, 109 for each component
G and 109B convert, based on the image signal from the CLP circuit 108, digital data in which, for example, one sample value is composed of 8 bits, and convert this data to the process control circuit 112.
Supply to

The process control circuit 112 includes, for example, a gamma correction circuit, a white clip circuit, a black clip circuit, a knee circuit and the like, and performs a process process on the supplied video signal as necessary. If necessary, processing such as color balance is performed. The signal processed by the process control circuit 112 is sent to the encoder circuit 113. The encoder circuit 113 calculates the transmitted signal and performs processing such as color balance. When the video camera output is communicated via a network or the like, the encoder circuit 113 performs a process of converting the output into a composite video signal according to a standard color television broadcasting system such as the PAL system or the NTSC system.

The MOS sensors 105R, 105G,
105B, current-voltage conversion circuits 106R, 106G, 10
The timing of 6B is controlled by a timing signal and a synchronization signal sent from the TG / SG circuit 111 corresponding to the own system. The operation power supply and output voltage of the TG / SG circuit 111 are the same as the power supply level supplied to the MOS sensor 105.

Thereafter, the video signal is applied to a D / A conversion circuit 115 via an output circuit 114, and the D / A conversion circuit 115 converts the input signal into an analog video signal and outputs it as a camera signal. . Further, the video signal can be directly output as a digital signal via the output circuit 114. These camera signals are supplied to a recording device such as a video tape recorder or a monitor device.

In the present embodiment, a fixed pattern noise component is canceled within a horizontal retrace period in a video camera which requires low power consumption and low voltage and needs to process an image of 30 frames per second. S /
A video camera capable of obtaining a high quality image signal while securing N can be provided.

In the above example, the optical image is separated into the three primary color components of RGB using the color separation prism.
This can be configured to perform color separation by a dichroic mirror. For example, red, green and blue dichroic mirrors separate and distribute the incident light,
Each optical image is decomposed into RGB components. The optical image is taken by a MOS sensor for R image, G image, and B image,
Image signals of an image, a G image, and a B image are obtained. This way,
The optical image can be obtained for each of the three primary colors without using a prism.

(Eighth Embodiment) <Application of Amplified MOS Sensor to Network System> FIG. 27 shows a system configuration in which the signals of video cameras 100 and 100-2 described above are sent to a monitor device or the like via a network. Here is an example. In the figure, reference numeral 300 denotes a network, which may be a LAN (local area network), a public line (telephone line), a dedicated line, the Internet, an intranet, or the like. The video cameras 100 and 100-2 are connected to the network 300 via an interface 301.

Reference numeral 310 denotes an intelligent terminal, which corresponds to a personal computer or a workstation. The intelligent terminal 310 includes a computer main body 311 including a processor, a main memory, a clock generator, and the like, an interface 312 for network connection, and a video RA as a memory for image display.
M313, printer interface 314, SCSI
(Small Computer System Interface), and standard bus interfaces 315 and 317, an interface 316 for video camera connection, and the like, which are connected by an internal bus. The video RAM 313 has C
Monitor device 318 such as an RT monitor or a liquid crystal display
Is connected, and the printer interface 3
14 is connected to a printer. An optical disk device, a hard disk device, or a large-capacity external storage device 320 such as a DVD (Digital Video Disc) is connected to the standard bus interface 317. The standard bus interface 317 further includes, for example, an image scanner 321 that captures an image from a hard copy. Is connected. Also, an interface 31 for connecting a video camera is provided.
For example, the video camera 100 having the configuration described in the above embodiment is connected to 6.

In such a configuration, the video camera 1
As described above, the image of the subject obtained by being picked up at 00 or 100-2 is converted into a digital signal that has been subjected to image compression processing by the MPEG method for communication of the video camera output by the encoder circuit 113 over a network or the like. Is performed. The composite video signal is converted into digital data by the interface 30.
1 to the network 300 in a network transmission format. An intelligent terminal 310 is connected to the network 300 via an interface 312, and the video camera 100 or 1
If the transmission data from 00-2 is addressed to the intelligent terminal 310, the computer main body 311 of the intelligent terminal 310 fetches the transmission data from the network 300 via the interface 312. Then, the computer main body 311 extracts an image information portion from the transmission data. Video camera 10
At 0 or 100-2, the image is compressed, so
The computer main body 311 expands the image and restores the original image. Then, the restored image data is sequentially written to the video RAM 313. Since the image is a moving image, the image data in the video RAM 313 is updated one after another.
As a result, the moving image sent from the video camera 100 or 100-2 is displayed on the monitor device 318 that displays the image data of the video RAM 313 as an image.

As described above, the image of the subject obtained by the imaging by the video camera 100 is subjected to image compression processing by the MPEG system by the encoder circuit 113 in order to communicate the video camera output through a network or the like. After being converted into digital data, it is output to the computer main body 311 via the interface 316, and the computer main body 311 performs a decompression process on the data to restore the original image. Then, the restored image data is sequentially written to the video RAM 313. Since the image is a moving image, the image data in the video RAM 313 is updated one after another. In this manner, the moving image sent from the video camera 100 is displayed on the monitor device 318 that displays the image data of the video RAM 313 as an image.

When the image of the video camera 100 connected to the intelligent terminal 310 is to be transmitted to the network 300, the computer main body 311 edits the image into a transmission format of the network, and transmits the image to the network 30 via the interface 312.
Output to 0.

(Ninth Embodiment) <Application of Amplified MOS Sensor to Still Camera> FIG.
FIG. 1 shows an embodiment of a still camera using a MOS sensor according to the present invention. As shown in FIG. 28, a still camera 400 according to the present invention includes an optical system 411 including a lens system and an aperture for capturing a subject image, a MOS sensor 415 for forming an image captured by the optical system 411, and the MOS sensor 415. 41
5 is positioned between the image forming plane 5 and the optical system 411 and is removably disposed on an optical path therebetween, and when inserted on the optical path, a subject image captured by the optical system 411 is removed. When the image is distributed to the finder 414 and escapes from the optical path, the object image captured by the optical system 411 is read by the MOS sensor 41.
A mirror 412 having a function as a shutter for forming an image on the image forming surface of the finder 5
4, an imaging circuit 416 that reads an image signal from the MOS sensor 415 for each color component, an A / D converter 417 that converts the read output to a digital signal, and conversion by the A / D converter 417. A frame memory 418 for holding the obtained digital signals on a screen basis,
A compression circuit 419 for compressing the digital signal held in the frame memory 418 on a screen-by-screen basis, a memory card 421 for storing image data, and control for writing image data obtained by compression processing by the compression circuit 419 to the memory card 421. And a card control circuit 420.

In such a configuration, by operating a shutter button (not shown), the subject image captured by the optical system 411 is formed on the MOS sensor 415. MO
The S sensor 415 is a solid-state imaging device including a noise canceller circuit used in the present invention. When an optical image captured by the optical system 411 is formed, the S sensor 415 converts the optical image into an electric signal corresponding to the light amount of each pixel. I do. In order to be able to capture a color image, the MOS sensor 415 is provided with a color filter array having one of RGB color filter units for each pixel on the image forming surface side thereof.
6 converts the electric signal obtained by the MOS sensor 415 into RG
B components are separated and output. Then, the current-voltage conversion circuit 106 converts the electric signal for each color component output from the imaging circuit 416 into a digital signal, and the converted digital signal is temporarily stored in the frame memory 418 on a screen basis.

[0177] The digital signal held in the frame memory 418 is subjected to compression processing for each image by the compression circuit 419 and output to the card control circuit 420. Then, the card control circuit 420 controls the storage of the compressed image data in the memory card 421 as a data storage medium.

[0178] In this manner, a still image photographed each time the shutter button is operated is compressed and stored in the memory card 421 on a screen-by-screen basis. The memory card 421 is detachable from the camera, and the image stored in the memory card 421 is attached to a reading / reproducing device (not shown) to decompress and restore the image data and display the image data on a monitor device, a video printer, or the like. Output to a hard copy device for viewing.

In this embodiment, low power consumption and low voltage can be achieved, and high-speed continuous shooting for continuously shooting a plurality of frames per second can be realized with high S / N. , A high-performance still camera can be obtained. That is, it is possible to provide a still camera capable of canceling a fixed pattern noise component, which has been a problem in the MOS sensor, in a short period of time and obtaining a high-quality photograph with a good S / N.

(Tenth Embodiment) <Application of Amplified MOS Sensor to Facsimile> FIG. 29
FIG. 1 shows an embodiment of a facsimile apparatus using a MOS sensor according to the present invention. The figure shows a basic configuration, in which a document 501 hand-written or printed on paper or a sheet-like document 501 such as a photograph is conveyed in a main scanning direction (arrow B direction) by a main conveyance mechanism (not shown). Then, the image information of the document is read by the MOS sensor 502 fixed at a fixed position and arranged in the transverse direction of the document. Reference numeral 503 denotes a light source, and reference numeral 504 denotes a lens for forming a document image on the light receiving surface of the MOS sensor 502.

The MOS sensor 502 is a linear sensor in which light receiving portions (photodiodes) are arranged one-dimensionally in pixel units, and is a monochrome solid-state imaging device having a noise canceller circuit used in the present invention.

A sheet-like original 50 is attached to the facsimile machine.
1 is set, the main transport mechanism (not shown)
01 in the main scanning direction (direction of arrow B). And
On the light receiving surface of the MOS sensor 502 fixed at a fixed position,
An image of the original is formed through a lens 504 by an amount corresponding to one line. The MOS sensor 502 reads the image information of the formed document.

That is, the MOS sensor 502
, A signal corresponding to the amount of received light is read out and output as an image signal in pixel units in the order of pixel arrangement.
Then, the amplified image signal is converted into a digital signal by an A / D converter 506 and then modulated for a telephone line by a modem 507 and output to a telephone line.

On the receiving side, the received signal is demodulated, and pixels are printed in the transverse direction of the recording paper conveyed in the main scanning direction with the density corresponding to the signal value in the receiving order, so that the image is reproduced as a hard copy. Is done.

In the present embodiment, it is possible to reduce the power consumption and voltage and to realize high-speed reading with a high S / N, and obtain a compact, high-performance, high-performance facsimile apparatus. Can be. That is, it is possible to provide a facsimile apparatus which can cancel a fixed pattern noise component which has been a problem in a MOS sensor in a short time and which can transmit a high-quality image with good S / N at a high speed.

In the case of a recent linear sensor,
Adhesive type devices that read an image in close contact with the document surface have appeared. Therefore, in order to form a close contact type, a lens that guides the original image, an image guided by this lens is formed and converted into an electric signal corresponding to the amount of light, and a light receiving unit in pixel units, and illumination light is applied to the original surface. It can be realized as a configuration in which a light emitting element to be applied is integrated, and such a light emitting element may be used.

(Eleventh Embodiment) <Application of Amplification Type MOS Sensor to Copying Machine> FIG. 30 shows an embodiment of an electronic copying machine using a MOS sensor according to the present invention. The figure shows a basic configuration, and a box-shaped housing 60 is shown.
A document table 60 made of transparent glass or the like
2 is provided, and the original is hand-printed or printed on paper, or a sheet-like original 603 such as a photograph is placed on the upper surface of the original placing table 602, and the original is pressed by the holding lid 604.

In the housing 601, near the position directly below the document table 602, there is provided an optical system capable of repeatedly moving at a constant speed from one end to the other end of the document table 602. Here, this repetitive movement direction is referred to as a main scanning direction. The optical system is a rod-like light source 605, a mirror 60
6, a lens 607, and the light source 605 is arranged in a direction orthogonal to the main scanning direction (this direction is referred to as a sub-scanning direction).

A MOS sensor 608 is provided at the image forming position of the lens 607. The MOS sensor 608 is a linear sensor in which light receiving units (photodiodes) are arranged one-dimensionally in pixel units, and is a monochrome solid-state imaging device provided with a noise canceller circuit used in the present invention.

The MOS sensor 608 forms an image of one line in the sub-scanning direction and converts the image into a signal corresponding to the amount of received light. The scanner controller 609 is a MOS sensor 6
08 so that a signal corresponding to the amount of received light is read and output as an image signal in pixel units in the order of pixel arrangement.
In addition to controlling the sensor 608, the driving control of the optical system in the main scanning direction is controlled so that the optical system sequentially moves in the main scanning direction. A system controller 610 controls the entire system.
The output of the laser light source 611 is controlled based on the signal corresponding to the amount of received light output from. The laser light source 611 generates a spot-shaped laser beam. The laser beam generated from the laser light source 611 is reflected by a polygon mirror 612 which is a scanning mirror for scanning the laser beam, and is formed into a cylindrical photosensitive member. An image is formed on the drum 613. This imaging position is the drawing position. The photoconductor drum 613 is configured to be driven to rotate in one direction at a predetermined speed, and the photoconductor drum 613 is charged by a charging device (not shown) at an upstream position of the laser beam irradiation position (upstream position of the drawing position).

The polygon mirror 612 is controlled by the system controller 610 to apply a spot-shaped laser beam to the surface of the cylindrical photosensitive drum 613.
When scanning is performed in accordance with the output speed of the signal from the S sensor 608, and the drum rotation direction of the photosensitive drum 613 is the main scanning direction, the laser beam is scanned in a direction orthogonal to the rotation direction, so that the laser beam is applied to the drum surface. The charge is lost corresponding to the light amount of the beam, and a latent image equivalent to the image of the document is formed. The photoconductor drum 613 develops the latent image at the position where the developing unit 614 that makes the latent image visible at the downstream position of the drawing position is developed by the toner provided by the developing unit 614 and passes through the visible image. Be transformed into Then, the toner images are taken out one by one from the copy paper storage tray 615 and transferred to the copy paper conveyed to the conveyance path 616 on the lower surface side of the photosensitive drum 613.

Copy Paper Conveyance Speed and Photosensitive Drum 61
The rotation speed of the document 3 is synchronized, and the toner image of the same image as that of the original is copied by transferring the latent image toner image formed on the surface of the photosensitive drum 613 by sequentially drawing one line at a time. Will remain on the paper. The transport path 616 is a path for sending the copy sheet on which the toner image has been transferred to the discharge port side, and the copy sheet is sent to the discharge port side by a transport mechanism provided on the transport path 616. The fixing unit 617 is a device for fixing toner provided in front of the discharge port. When the copy sheet onto which the toner image has been transferred passes through the fixing unit 617, the toner is fixed on the copy sheet and discharged to the discharge port. It is a mechanism that is performed.

In such a configuration, at the time of copying, a sheet-shaped document 603 is placed on the upper surface of the document table 602, and the document is pressed by the holding cover 604. Document table 6
In the vicinity of the position immediately below the document holder 02, an optical system that can repeatedly move in the main scanning direction at a constant speed between one end and the other end of the document table 602 is provided. A light source 605, a mirror 606,
The lens 607 is configured to move repeatedly in the main scanning direction.

When the main scanning direction is regarded as the vertical direction, the horizontal direction of the document table 602 is defined as the width direction. in this case,
A light source 605 constituting the optical system illuminates a range corresponding to the width of the document table 602, and a mirror 606 constituting the optical system.
The lens 607 forms an image of the illuminated area on the light receiving surface of the MOS sensor 608. The MOS sensor 608 is a linear sensor in which light receiving units (photodiodes) are arranged one-dimensionally in pixel units, and is a monochrome solid-state imaging device provided with a noise canceller circuit used in the present invention.

Therefore, the MOS sensor 608 has a width of 1 in the width direction.
An image corresponding to a line (that is, one line in the sub-scanning direction) is formed and converted into a signal corresponding to the amount of received light. The scanner controller 609 controls the MOS sensor 608 so that a signal corresponding to the amount of received light is read out and output as an image signal in pixel units in the pixel arrangement order, and the optical system is sequentially arranged in the main scanning direction. The movement of the optical system in the main scanning direction is controlled so as to move. Therefore, a signal corresponding to the amount of received light can be obtained from the image image of the document 603 on the document table 602 in the main scanning direction and in the order of pixels in the sub-scanning direction one line unit.

This signal is given to the system controller 610, and the system controller 610 controls the output of the laser light source 611 according to this signal. Therefore, the laser light source 611 oscillates light output from the MOS sensor 608 and having an intensity corresponding to the amount of received light.

On the other hand, the system controller 610 drives and controls the polygon mirror 612 to swing in synchronization with the read speed of the MOS sensor 608.
In addition, an optical image corresponding to one line of the image (that is, one line in the sub-scanning direction) is drawn on the photosensitive drum 613 by the polygon mirror 612.

The photosensitive drum 613 is driven to rotate in a fixed direction at a peripheral speed corresponding to the main scanning speed. The peripheral surface of the photosensitive drum 613 has a polygon mirror 612.
At the stage where the laser beam reaches the drawing position of the laser beam, the charging means has already charged the surface. Then, by being irradiated with the laser beam, the photosensitive drum 613 in the irradiated portion loses the charge by the amount of the irradiated light. Therefore, the image of the document remains as a latent image on the photosensitive drum 613 in a region downstream of the drawing scan position of the laser beam by the polygon mirror 612 in the rotation direction.

At the stage where the latent image passes through the position of the developing unit 614, the latent image is developed by the toner provided by the developing unit 614 to become a visible image. Then, the toner images are taken out one by one from the copy paper storage tray 615 and transferred to the copy paper conveyed to the conveyance path 616 on the lower surface side of the photosensitive drum 613. The conveyance speed of the copy paper and the rotation speed of the photosensitive drum 613 are synchronized, and 1
By transferring the toner image of the latent image formed on the surface of the photosensitive drum 613 by sequentially drawing the image on a line-by-line basis, a toner image of the same image as the document remains on the copy sheet. The copy sheet onto which the toner image has been transferred is sent to the discharge port side through the transfer path 616 by the transfer mechanism, and passes through the fixing unit 617 provided in front of the discharge port.
The fixing unit 617 fixes the toner on the copy sheet and discharges it.

In the present embodiment, low power consumption and low voltage can be achieved, and high-speed reading can be realized with high S / N. Thus, a compact, high-performance, high-performance electronic copying machine can be obtained. Will be able to do it. In other words, MO
Provided is an electronic copying machine capable of canceling a fixed pattern noise component which has been a problem in an S sensor in a short time, reading a high-quality image with good S / N, and copying at high speed. it can.

Although the copying machine described above has a configuration in which the original is fixed in position and the optical system is moved in the main scanning direction, the optical system is fixed in position and the original is conveyed in the main scanning direction. It can also be realized as a device having a configuration configured to do so. Although the above-described copying machine has been described by taking a monochrome device as an example, three primary color filters are provided in the optical system, color separation is performed, a latent image is formed for each color, and the latent image for each color is converted to the latent image. By developing with a toner of a corresponding color, a copying machine capable of obtaining a color copy can be realized.

(Twelfth Embodiment) <Application of Amplified MOS Sensor to Scanner> FIG. 31 shows an embodiment of a handy image scanner using a MOS sensor according to the present invention. Image scanner 7 of the present invention
As shown in FIG. 00, an LED array 702 as a light source, a mirror 703, and a roller 704 are mounted in a housing 701, as shown in FIG. The LED array 702 is a housing 70
1, which extends almost all over the width, and illuminates the lower outside of the housing 701. The mirror 703 is arranged near the position where the LED array 702 is arranged, and
The image image of the document illuminated by 2 is taken into the inside of the housing 701 through the slit 701a provided in the lower part of the housing 701.

The hand-held image scanner shown in FIG.
The housing 701 is placed on a document, and is moved and scanned by hand as it slides on the document. At that time, a roller 704 is provided to synchronize the detection of the line position and the reading in order to take in the image of the document from the slit 701a in units of one line. The roller 704 exposes a part of the peripheral surface from the lower part of the housing 701 in order to be able to rotate by the friction with the original in contact with the original. This exposure position is the slit 701
a.

An encoder 705 for detecting the direction and amount of rotation of the roller 704 in synchronization with the rotation of the roller 704 is provided inside the housing 701.
An S sensor 706 and a lens 707 for forming a document image guided by the mirror 703 on the light receiving surface of the MOS sensor 706 are provided.

The MOS sensor 706 is a linear sensor in which light receiving portions (photodiodes) are arranged one-dimensionally in pixel units, and is a monochrome solid-state imaging device having a noise canceller circuit used in the present invention. In recent years, linear sensors are often of the close contact type that read an image in close contact with a document surface. Therefore, in order to form a close contact type, a lens that guides the original image, an image guided by this lens is formed and converted into an electric signal corresponding to the amount of light, and a light receiving unit in pixel units, and illumination light is applied to the original surface. It can be realized as a configuration in which a light emitting element to be applied is integrated.

Here, in order to show the principle, a configuration as shown in FIG. 31 is shown.

A signal read from the MOS sensor 706 is associated with a position by the output of the encoder 705 and used for read timing control.

In such a configuration, the sheet-shaped document is placed on a flat place, the handy scanner is placed thereon, and the document is moved on the document in a direction in which the roller 704 can rotate. This moving direction is the main scanning direction. At this time, the LED array 702 illuminates the original surface and the slit 7
The image of the original enters mirror 703 via 01a.
Then, the light is reflected by the mirror 703 and is imaged on the MOS sensor 706 by the lens 707.

The MOS sensor 706 is a line image sensor, and the image of the original is placed on the light receiving surface of the fixed MOS sensor 706 by a lens corresponding to one line.
And read image information of the imaged document.

As described above, in the hand-held image scanner of this embodiment, the housing 701 is placed on the document, and the hand-held image scanner is moved and scanned by hand while sliding on the document. At this time, a roller 704 is provided to synchronize the detection of the line position and the reading in order to take in the image of the document from the slit 701a in units of one line. As a result, the encoder 705 outputs a detection signal corresponding to the rotation direction and the rotation amount of the roller 704 from the encoder 705. Then, based on the detection signal from the encoder 705, the MOS sensor 706 is controlled by control means (not shown).
Is controlled and output so that the output signal of the original coincides with one line unit of the document.

In the present embodiment, low power consumption and low voltage can be achieved, and high-speed reading can be realized with high S / N. Thus, a compact, high-performance, high-performance image scanner can be obtained. be able to. In other words, MO
It is possible to provide an image scanner device capable of canceling a fixed pattern noise component, which has been a problem in the S sensor, in a short period of time and capable of transmitting a high-quality image with high S / N at a high speed.

In this example, a hand-held type image scanner is shown. However, the present invention can also be applied to a desktop type image scanner in which an original is placed on an original placing table and an optical system is driven by main scanning. Further, it can be realized as an apparatus having a configuration in which the optical system is fixed in position and the original is conveyed in the main scanning direction. Although the above image scanner has been described by taking a monochrome device as an example, the optical system is provided with three primary color filters to perform color separation,
By obtaining an image signal for each color, an image scanner capable of obtaining a color image signal can be realized. Further, the optical system is formed using a concave mirror, and an image is guided to the MOS sensor by the concave mirror, or an image is guided to the MOS sensor by an optical fiber formed by bundling optical fibers. Is possible.

(Thirteenth Embodiment) <Desktop type color image scanner>
Embodiment 1 shows a configuration of an optical system used in a desktop type color image scanner. In a desktop color image scanner, the optical system is fixed at a fixed position, and scans a document in the main scanning direction. In this case, as shown in FIG. 32, color filters of three primary colors are provided in the optical system, color separation is performed, and an image signal is obtained for each color. In FIG. 32, a MOS sensor S for obtaining an image signal is a line sensor, and pixels are arranged linearly for one line. A color filter F is arranged on the light receiving surface side of the MOS sensor S. The color filter F has R (red), G (green), and B, each having a width and a length corresponding to one line.
In this configuration, the optical filter units for each color component of (blue) are arranged in parallel. The light receiving surface side of the MOS sensor S is configured to form an optical image of the document DP via the lens L and the color filter F. The document DP is illuminated by the light source LP.

The color filter F is composed of R (red), G
(Green) and B (blue) optical filters for each color component
The driving and scanning mechanism DR is supported so as to be able to move and scan so as to move on the light receiving surface of the S sensor S. When receiving a red image, the optical filter for the R color component is used. When receiving a green image, the optical filter for the G color component is used. When receiving a blue image, the color of B is used. The driving movement is controlled while synchronizing with the image acquisition timing so that the component optical filter section is positioned on the light receiving surface of the MOS sensor S.

Thus, the MOS sensor S outputs R
An image signal of an optical image for each color component of (red), G (green), and B (blue) can be obtained.

(Fourteenth Embodiment) <Application of Amplified MOS Sensor to Film Scanner> The amplified MOS sensor of the present invention can be used in a personal computer, an image display device, or the like, for example, for one frame of 35 mm long film. The present invention can also be applied to a film scanner device that reads one frame and obtains an image signal.

FIG. 33 shows an example of the configuration. As shown in the drawing, a contact type line sensor S using an amplification type MOS sensor, an S developed silver halide long film FM disposed on the light receiving surface side of the line sensor S, and the silver halide long film FM Light source L illuminating on the light receiving surface position of
P, a pair of transport rollers C transporting the silver halide long film F in one direction at a constant speed.

According to such a configuration, the silver halide long film FM is sandwiched between the transport rollers C, and the transport rollers C are driven to rotate at a constant speed. Thus, the silver salt long film FM is transported in one direction at a constant speed. Therefore, the image of the silver halide long film FM is read out and controlled by the contact type line sensor S in synchronization with the film transport speed, and a signal corresponding to the amount of received light is obtained. This signal has been subjected to noise cancellation, and a film image containing only image components can be converted into an electric signal for each line and output.

(Fifteenth Embodiment) <Application to Autofocus Mechanism> FIG. 34 shows an embodiment of a single-lens reflex camera with an autofocus mechanism using a MOS sensor according to the present invention. In the figure, a single-lens reflex camera 800 of the present invention includes a lens 801 having a focal position adjusting mechanism, a film 803 on which an optical image captured by the lens 801 is formed and exposed, and a lens 801 on a finder 802a of the camera 800. The lens 801 is composed of a prism 802 b for guiding a captured optical image, the autofocus sensor module 804 of the present invention, and a half mirror.
And a flip-up finder mirror 805 which is completely deviated from the optical path by operating a shutter. The finder mirror 805 is attached to the back of the finder mirror 805 and is mounted on the optical path of the lens 801. When the mirror 805 is located, a sub-mirror 806 for forming a transmission optical image of the finder mirror 805 on the autofocus sensor module 803 is provided.

Auto focus sensor module 804
Is an M with a noise canceller circuit used in the present invention.
An OS sensor is used, and as shown in FIG.
A separator lens 804b is fixedly provided on the front surface of the light receiving surface of the sensor 804a. MOS sensor 804
A having a two-dimensional array of light receiving surfaces is used as a. The separator lens 804b is, as shown in FIG.
The configuration is such that a pair of convex lenses are arranged side by side, and the optical image distributed by the sub-mirror 806 is formed on another area of the light receiving surface of the MOS sensor 804a by the separator lens 804b. With the configuration in which the optical image is guided to the light receiving surface of the MOS sensor 804a by the separator lens 804b having a configuration in which a pair of convex lenses are arranged side by side, images are formed on different regions on the light receiving surface, A pair of images will be obtained.

The camera having such a configuration is provided with a lens 801.
The object image captured by the finder mirror 805 is distributed by the finder mirror 805 to the prism 802 b and the sub mirror 806. The subject image distributed to the finder mirror 805 is formed on the finder 802a through the prism 802b, so that the subject image captured by the camera 800 can be observed.

On the other hand, the subject image distributed to the sub mirror 806 is guided to the auto focus sensor module 804. The auto focus sensor module 804 is M
An OS sensor 804a is provided, and a separator lens 8 is provided in front of the light receiving surface of the MOS sensor 804a.
04b is arranged. Then, the separator lens 804b forms an image on the light receiving surface of the MOS sensor 804a in different areas. Since the MOS sensor 804a generates an electric signal corresponding to the light amount of the optical image formed on the photodiode corresponding to each pixel forming the light receiving surface, the electric signal is sequentially read.

Auto focus sensor module 804
, The MOS is formed by the separator lens 804b.
The light receiving surface of the sensor 804a is effectively divided into two image forming regions, and the subject images formed in the two image forming regions are in focus (in a focused state). ), The output of the MOS sensor 804a is centered on the reference pixel positions P0 and P0 'of each divided image forming area, as indicated by 806A in FIG.
In this state, the same image appears.

In the case of the front pin (in a state where the focus position is shifted from the film surface to the front position), the reference numeral 806 in FIG.
As shown in B, the output of the MOS sensor 804a is such that the same image appears at a position closer to the inside than the reference pixel positions P0 and P0 'of each divided image forming area.

In the case of a rear focus (in a state where the focus position is shifted to a position behind the film surface), 8 in FIG.
As in the case of 06C, the output of the MOS sensor 804a is the reference pixel position P0, P0 'of each divided image forming area.
At the positions further away from each other, the same image appears.

Accordingly, from the output of the MOS sensor 804a, the output of the MOS sensor 804a is changed to a state where the same image appears around the reference pixel positions P0 and P0 'of each of the divided image forming areas. A control amount necessary to adjust the focus of the lens 801 in a certain direction is obtained, and the focal position adjusting mechanism is controlled by the control amount. Accordingly, the focus is adjusted so that the lens 801 is in focus with respect to the film surface.

When the shutter is operated, the finder mirror 805 jumps up and out of the optical path, so that the subject image captured by the lens 801 is formed on the film surface, and the film is exposed and the focused subject image is captured. You.

The camera provided with the auto-focus mechanism of the present invention can realize the focus state detection with low power consumption and low voltage, and can realize high-speed reading with high S / N, and provide a fast shutter. Even when shooting at high speed or in high-speed continuous shooting, the focus state can be sufficiently followed to detect the focus state, and the focus can be controlled immediately to shoot a clear image. In other words, MO
The fixed pattern noise component, which has been a problem in the S sensor, can be canceled in a short time, and a high-quality image can be read at high speed because of good S / N, and the focus state can be detected at high speed. The alignment can be controlled, and a clear image can be taken.

Although the single-lens reflex camera has been described as an example, the autofocus mechanism can be applied to a lens shutter camera, binoculars, an optical microscope, and the like.

Next, a low-noise MOS sensor used in each system described above, that is, a MOS sensor capable of effectively removing fixed pattern noise and obtaining a large output dynamic range of, for example, 70 dB or more,
A specific example of a noise canceller circuit and a unit cell used in the MOS sensor will be described with reference to the drawings.

A solid-state imaging device using an amplifying MOS sensor uses a photodiode as a light receiving section, and a signal detected by the photodiode is amplified by a transistor for each cell, and has a feature of high sensitivity.

In general, in an amplification type MOS solid-state imaging device, an output signal of a photodiode which is a light receiving section corresponding to a pixel in each unit cell is amplified and taken out through an amplification transistor provided in the unit cell. Therefore, at the time of this amplification, a portion corresponding to the variation in the characteristics of the amplification transistor is superimposed on the signal. therefore,
Even if the potential of each photodiode in each unit cell is the same, the amplification transistors in the unit cell to which the photodiode belongs are different from each other, and the characteristics of each amplification transistor are slightly different. The signals are not the same. Therefore, when an image captured by the amplification type MOS solid-state imaging device is reproduced, noise corresponding to variation in the characteristics of the amplification transistor in each unit cell is generated.

As described above, in the amplification type MOS solid-state imaging device, the characteristics are slightly different in the amplification transistor in each unit cell, and are unique to each unit cell.
Noise that is fixedly distributed in the reproduced image, that is, two-dimensional noise, cannot be avoided. This noise is called fixed pattern noise in the sense that it is fixed in place on a screen which is a two-dimensional space.

The noise canceller circuit used in the present invention, which will be described in detail below, is provided to remove the fixed pattern noise.

Next, a specific example of a noise canceller circuit used in a solid-state imaging device using an amplification type MOS sensor for amplifying signal charges in a cell will be described.

(Sixteenth Embodiment) FIG. 36 relates to a MOS solid-state imaging device according to a sixteenth embodiment used in the present invention, and in particular, shows a configuration example of a MOS solid-state imaging device having a noise canceller circuit. Is shown. Unit cell P4-
ij are arranged vertically and horizontally in a two-dimensional matrix. Although only 2 × 2 is shown in the figure, there are actually several thousands × thousands. i is a variable in the horizontal (row) direction, and j is a variable in the vertical (column) direction. Each unit cell P4-ij
Has already been described with reference to FIG. 3, FIG. 5B, FIG. 5C or FIG. 36, those having the same names as those described in FIG. 3, FIG. 5 (b), FIG. 5 (c) or FIG. 8 shall be the same.

The application fields of the solid-state imaging device used in the present invention include a video camera, an electronic still camera, a digital camera, a facsimile, a copier, a scanner and the like.

The vertical address lines 906-1, 906-2, which are wired in the horizontal direction from the vertical address circuit 905.
... are connected to the unit cells of each row and determine horizontal lines from which signals are read. That is, the vertical address line 906-
Reference numerals 1,906-2,... Denote signal lines for deciding whether to activate the amplifying transistors in the unit cells of each row.

Similarly, reset lines 907-1 and 907-
Are connected to the unit cells in each column, and drive the gates of the reset transistors in the unit cells.

The unit cells in each column are connected to vertical signal lines 908-1, 908-2,... Arranged in the column direction, and output detection signals (pixel signals) of the unit cells through these signal lines. These vertical signal lines 908-1, 908-2,
Are connected to one end of the load transistors 909-1, 909-
2, ... are provided. Load transistor 909-
The gates and drains of 1, 909-2,... Are commonly connected to a drain voltage terminal 920.

The other ends of the vertical signal lines 908-1, 908-2,...
... connected to the gate. MOS transistor 926
The sources of 1,926-2,...
8-1, 928-2,...
Transistors 926-1, 926-2, ..., 928-
, Operate as a source follower circuit. The gates of the MOS transistors 928-1, 928-2,... Are connected to a common gate terminal 936.

MOS transistors 926-1, 926-
2,... And MOS transistors 928-1, 928-2,
Are connected to the sample-and-hold transistor 930−
1, 930-2,...
932-2,... Clamp capacity 93
The sample-and-hold capacitors 934-1, 934-2,... And the clamp transistors 940-1, 940-2,.
The other ends of the sample hold capacitors 934-1, 934-2,... Are grounded. Clamp capacity 932-1, 932
The other ends of −2,... Are horizontal selection transistors 912-1, 9
12-2, a signal output terminal (horizontal signal line) 915
Is also connected.

The vertical address circuit 905 is a circuit for shifting a plurality of signals, here two signals, collectively.
This is realized by one of the circuits shown in FIGS. In the example of FIG. 37, the output of the address circuit 944 that sequentially shifts and outputs the input signal 946 from a large number of output terminals is combined with the two input signals 950 by the multiplexer 948.
In the example of FIG. 38, the output of the decoder 952 for decoding the encode input 954 is
It is combined with the input signal 958. In the example of FIG. 39, the outputs of the two address circuits 960a and 960b are bundled to form a control signal line for each row.

Each unit cell P4-1-i shown in FIG.
(I = 1, 2, 3,...) Correspond to, for example, FIGS.
(B), FIG. 5 (c) or FIG.

In general, in an amplification type MOS solid-state imaging device, since the variation in the characteristics of the amplification transistor affects the signal, even if the output of the photodiode is the same, the output signal from the cell will not be the same, and When the reproduced image is reproduced, a fixed pattern noise, which is a two-dimensional noise corresponding to a variation in characteristics of the amplification transistor, is generated. That is, in the amplification type MOS solid-state imaging device, even if uniform light is applied to the entire light receiving surface, the level of the image signal obtained from each pixel in the matrix arrangement does not become uniform in each pixel. An image signal having uneven brightness is obtained. The image having uneven brightness is noise in which noise is distributed two-dimensionally, that is, noise distributed in a plane called a screen, and is called fixed pattern noise in the sense that it is fixed in place.

For this reason, in this embodiment, as shown in FIG. 36, the horizontal selection transistor 91 corresponds to the unit cell.
Before step 2, a noise removing circuit (noise canceller circuit) provided with a circuit for suppressing the fixed pattern noise is used.

FIG. 41 is a circuit diagram showing a conventional solid-state imaging device using an amplification type MOS sensor. The unit cells P0-ij corresponding to the pixels are vertically and horizontally arranged in a two-dimensional matrix. Although only 2 × 2 is shown in the figure, the array is actually several thousands × thousands. i is horizontal (ro
The variable in the w) direction, j is the variable in the vertical (column) direction. Each unit cell P0-ij includes a photodiode 1-
ij, amplifying transistor 2-ij, vertical select transistor 3-ij, reset transistor 4-i
-J. Further, there are a vertical address circuit 205 and a horizontal address circuit 213 for sequentially selecting the unit cells P0-1-1,... P0-ij,. The vertical address circuit 205 has n
× m unit cells P0-1 in a two-dimensional matrix array
There are a number of pairs of address output terminals and reset signal terminals corresponding to n which is the number of horizontal arrangements (the number of arrangements in the horizontal (row) direction) of -1,... P0-ij,.
3 is an address corresponding to m, which is the number of vertical cells (the number of cells arranged in the vertical direction (column direction)) of unit cells P0-1-1,..., P0-ij,. There is an output terminal. Note that m, n, i, and j are arbitrary integers.

Then, one by one along the unit cells P0-1-1, P0-1-2,... P0-2-j,... Arranged in the horizontal (row) direction from the vertical address circuit 205.
), The vertical address lines 6-1, 6-2,...
Are connected to the corresponding one of the n address output terminals of the vertical address circuit 205, respectively.

The unit cells P arranged in the horizontal (row) direction
0-1-1, P0-1-2,..., P0-2-j,.
Are arranged in this order in the direction, and these reset signal lines 7-1, 7-2,... Are respectively provided among n reset signal terminals of the vertical address circuit 205. Connected to the corresponding one.

The unit cells P0-1-
, P0-1-2,..., P0-2-j,..., The vertical signal lines 8-1, 8-2,. Each of the vertical signal lines 8-1, 8-2,... Is connected to a corresponding one of m address output terminals of the horizontal address circuit 213.

The vertical address lines 6-1, 6-2,... Arranged in the horizontal direction from the vertical address circuit 205 are connected to the gates of the vertical selection transistors 3-1-1,. The horizontal line from which is read is determined. Similarly, the reset lines 7-1, 7-2,... Wired in the horizontal direction from the vertical address circuit 205 correspond to the reset transistors 4-1-1,.
Connected to the gate.

Photodiode 1-i for detecting incident light
-J forms a light receiving portion for detecting incident light, generates signal charges corresponding to the amount of received light, and forms one pixel with one photodiode. The amplifying transistor 2-ij amplifies the signal charge generated by the photodiode 1-ij and outputs it as a detection signal. The cathode of the photodiode 1-ij is connected to its own gate. Thus, the signal charge of the photodiode 1-ij is amplified, and an amplified output corresponding to the signal charge is generated on the drain side as a detection signal.

The vertical selection transistor 3-ij has its own source-drain connected between the DC system power supply and the drain side of the amplification transistor 2-ij, and its own gate side has a vertical address. It is connected to the vertical address line 6-j of the circuit 205.

The reset transistor 4-ij has its own source-drain connected between the DC system power supply and the cathode of the photodiode 1-ij, and operates in response to the signal of the photodiode 1-ij. Reset the charge.

That is, specifically, the source side of the vertical selection transistor 3-ij and the reset transistor 4-i-
The source side of j is commonly connected to a drain voltage terminal of a DC system power supply so that a drain voltage is supplied.

As described above, the vertical address circuit 205
Vertical address lines 6-1,
6-2,... Are the vertical selection transistors 3 of the unit cells in each row.
.. Are connected to the gates and determine horizontal lines from which signals are read. Similarly, the vertical address circuit 205
Reset lines 7-1 and 7-
Are reset transistors 4-1-1 in each row.
Connected to the gate.

Therefore, in the reading of the pixels of the n × m configuration (array configuration of n rows and m columns), the vertical address circuit 205 is used to activate the horizontal lines (row direction lines) having n lines in the reading scanning order. Sequentially activate the vertical address lines 6-1, 6-2,.
It is configured to operate to output a signal to an output terminal so as to reset the signal charge of the pixel.

The above is the description of the image detecting section. In addition to the image detecting section, there is an output section for reading out the image detected by the image detecting section. The output part is load transistors 9-1 and 9-
2,..., The signal transfer transistors 10-1, 10-2,
.., Storage capacitors 11-1, 11-2,..., And horizontal (row) selection transistors 12-1, 12-2,.

That is, the source sides of the amplification transistors 2-1-1, 1-2-2,... Of the unit cells in each column are among the vertical signal lines 8-1, 8-2,. , Are respectively connected to the corresponding columns. Also,
One load transistor 9-1, 9-2,... Is provided for each unit cell in each column, and one end of the vertical signal lines 8-1, 8-2,. -1, 9-2,..., And the source-drain side of the load transistor to a DC system power supply.

The other ends of the vertical signal lines 8-1, 8-2,... Are connected to the signal transfer transistor 1 for taking in signals for one row.
Storage capacitors 11-1, 11-2 for storing one row of signals via one of 0-1, 10-2,.
,... Selected by the horizontal address pulse supplied from the horizontal address circuit 213, and the horizontal (row) selection transistors 12-1, 12-2,. It is connected to a signal output terminal (horizontal signal line) 215 via the terminal.

That is, the other ends of the vertical signal lines 8-1, 8-2,... Are connected to the signal transfer transistors 10-1, 10-2,.
Are connected to one end of a corresponding one of the storage capacitors 11-1, 11-2,... Via the source-drain of the corresponding one of the transistors.
Horizontal (row) selection transistors 12-1, 12-2,...
Are connected to a signal output terminal (horizontal signal line) 215 via a source-drain of a corresponding one of the transistors. The other ends of the storage capacitors 11-1, 11-2,... Are grounded, and the signal transfer transistors 10-1, 10-2,.
Are connected to the common gate 214. By applying a signal transfer pulse to the common gate 214 at a timing at which a signal is to be transferred, the signal transfer transistors 10-1, 10-2,...
., 8-2,...
-1, 11-2,... And stored.

The horizontal address circuit 213 is for sequentially selecting a pixel position to be read out per horizontal line, and is used for reading out pixels of an n × m configuration (n rows and m columns). The horizontal address pulse is generated so as to activate the horizontal (row) selection transistors 12-1, 12-2,... At the pixel positions corresponding to the respective scanning positions according to the line scanning speed.

Therefore, in the reading of the pixels of the n × m configuration (the configuration of the n rows and the m columns), it is possible to control the scanning such that the signal of the pixels in the line is read while the line position is sequentially changed.

Referring to the timing chart of FIG.
The operation of this conventional MOS-type solid-state imaging device will be described. The vertical address line 6-
When an address pulse for setting the vertical address line 6-i to the high level is applied to i, only the selection transistors 3-i-1, 3-i-2,... of this row are turned on, and the amplification transistor 2 of this row is turned on. , And load transistors 9-1, 9-2,... Constitute a source follower circuit.

As a result, the amplification transistor 2-i-
Are applied to the vertical signal lines 8-1, 8-2,..., That is, voltages substantially equal to the voltages of the photodiodes 1-i-1, 1-i-2,. appear.

At this time, the signal transfer transistor 10-
When a signal transfer pulse is applied to the common gate 214 of 1, 10-2,..., The amplified signal storage capacitors 11-1, 11-2,.
.. Store the amplified signal charge represented by the product of the voltage appearing on the vertical signal lines 8-1, 8-2,.

The amplified signal storage capacitors 11-1, 11-2,...
After the signal charge is stored in the vertical address circuit 5, the vertical address circuit 5 applies a reset pulse to the reset line 7-i. This reset pulse causes the reset transistor 4
Are turned on, and the signal charges stored in the photodiodes 1-i-1, 1-i-2,... Are reset by the reset transistors 4-i-1, 4-i-. It is discharged through 2,. Thereby, the photodiode 1-i
-1, 1-i-2,... Have been reset.

Next, the horizontal address pulse is supplied from the horizontal address circuit 213 to the horizontal selection transistors 12-1 and 12-1.
−2,... Then, the horizontal selection transistors 12-1, 12-2,... Are turned on while the horizontal address pulse is being applied. The signal charges stored in the amplified signal storage capacitors 11-1, 11-2,...
-2,... Through a storage signal output terminal (horizontal signal line) 215
Output from Thus, an image signal for one row is obtained as an output signal.

By continuing this operation sequentially to the next row (horizontal line) and the next row, all the signals of the photodiodes arranged two-dimensionally can be read.

As described above, by performing read control while sequentially changing the line position, image signals for one screen can be sequentially taken out, and a moving image can be obtained by repeating this operation continuously. .

The unit cell P0-ij of the conventional MOS-type solid-state imaging device described above includes an amplifying transistor 2-ij, which amplifies a charge signal from the photodiode 1-ij,
A total of three transistors are used: a vertical selection transistor 3-ij for selecting a line from which a signal is read, and a reset transistor 4-ij for charging / discharging the gate of the amplification transistor.

However, since the MOS solid-state imaging device amplifies and outputs the charge signal using the amplification transistor 2-ij, the problem of noise due to the amplification transistor 2-ij follows. That is, the amplification transistor 2-
ij is provided for each unit cell which is a pixel, and the amplification transistor generates an output even when the photodiode is not receiving light. This is due to the unavoidable variations such as dark current and thermal noise due to the characteristics of the amplification transistor. Since each pixel cell in the matrix arrangement is unique and unique, uniform light is received on the light receiving surface. Even if the image is applied to the entire surface, the level of the obtained image signal is not uniform for each pixel and becomes an image signal having uneven brightness. The image having uneven brightness is noise in which noise is distributed two-dimensionally, that is, noise distributed in a plane called a screen, and is called fixed pattern noise in the sense that it is fixed in place. The problem of this noise is significant, and becomes more prominent as the pixels are miniaturized. Therefore, improvements and countermeasures are required for imaging.

To remove this fixed pattern noise,
In the sixteenth embodiment, a noise elimination circuit (noise canceller circuit) in which a circuit for suppressing this fixed pattern noise is provided in front of the horizontal selection transistor 12 corresponding to the unit cell (FIG. 36).

In FIG. 36, as an example of the noise elimination circuit, there is shown a correlated double sampling type in which a difference between a signal and noise is obtained in a voltage domain. Without limitation, various noise removing circuits can be used.

Referring to the timing chart of FIG.
The operation of the MOS solid-state imaging device with the noise canceller circuit having the configuration shown in FIG. 36 will be described. The common drain terminal 920 of the load transistor 909 and the common gate terminal 93 of the transistor 928 of the impedance conversion circuit
6. Common source terminal 93 of clamp transistor 940
8 is a DC drive and is omitted from the timing chart.

When a high-level address pulse is applied to the vertical address line 906-1,
Unit cells P4-1-1, P4- connected to 6-1
The vertical selection transistors 965 of 1-2,... Turn on, and the amplification transistor 964 and the load transistor 909 are turned on.
-1, 909-2,... Constitute a source follower circuit.

Sample hold transistor 930-
, The common gate 937 of the sample hold transistors 930-1, 930
Turn on -2, .... Thereafter, the clamp transistor 9
, The common gate 942 of the clamp transistors 940-1, 940-2,.
Turn on 2, ...

Next, the clamp transistors 940-1,
The common gate 942 of 940-2,... Is set to the low level, and the clamp transistors 940-1, 940-2,. Therefore, the vertical signal lines 908-1, 908-
The signal plus noise components appearing at 2,... Are accumulated in the clamp capacitors 932-1, 932-2,.

After the vertical address pulse is returned to the low level, a high-level reset pulse is applied to the reset line 907-1, and the unit cell P4-1-1 connected to the reset line 7-1 is applied. , P4-1-2,... Are turned on, and the output circuit 9 is turned on.
The charge at the input terminal 68 is reset.

When a high-level address pulse is again applied to the vertical address line 906-1, the unit cell P4-1-1, connected to the vertical address line 906-1,
The vertical selection transistor 965 of P4-1-2,... Is turned on, and the amplification transistor 964 and the load transistor 9 are turned on.
The source follower circuit is constituted by 09-1, 909-2,..., And only noise components whose signal components have been reset appear on the vertical signal lines 908-1, 908-2,.

As described above, the clamp capacitance 932-
Since the signal plus noise component is accumulated in 1,932-2,..., The clamp nodes 941-1, 941-2,.
.. Show only the voltage change of the vertical signal lines 908-1, 908-2,..., That is, only the signal voltage without the fixed pattern noise obtained by subtracting the noise component from the signal component plus the noise component.

Then, the sample hold transistor 9
The common gate 937 of the sample hold transistors 930-1, 930-2,.
930-2, ... are turned off. Therefore, noise-free voltages appearing at the clamp nodes 941-1, 941-2,...
Is accumulated in

Thereafter, the horizontal selection transistor 912-
, 921-2,... Are sequentially applied to sample-hold capacitors 934-1, 933-1.
The signal of the photodiode 962 without noise stored in 4-2,... Is read from the output terminal (horizontal signal line) 915.

Hereinafter, similarly, the vertical address line 906-
By repeating the above operation for 2,906-3,..., Signals of all cells arranged two-dimensionally can be extracted.

Here, the relationship between the timing and the timing shown in FIG. 40 will be described. The required order is as follows. Vertical address pulse rise, sample hold pulse rise, clamp pulse rise → reset pulse rise → reset pulse fall → sample hold pulse fall → vertical address pulse fall Note that vertical address pulse rise, sample The relationship between the rise of the hold pulse and the rise of the clamp pulse is arbitrary, but is preferably in the order described above.

As described above, according to the operation shown in FIG. 40, a voltage difference between the presence of a signal (plus noise) and the absence of a signal due to resetting of the gate of the amplification transistor appears at clamp node 941. , Unit cell P4-1-i
The fixed pattern noise caused by the variation in the characteristics of the amplifying transistors at (i = 1, 2, 3, 4 to) is compensated. That is, a circuit including the clamp transistor 930, the clamp capacitor 931, the sample hold transistor 940, and the sample hold capacitor 934 functions as a noise canceller.

Note that the noise canceller of this embodiment is an impedance conversion circuit 92 comprising a source follower circuit.
6, 928 to the vertical signal line 908. That is, the vertical signal line is connected to the gate of the transistor 926. Since this gate capacitance is very small, the amplification transistor of the cell is connected to the vertical signal line 908-1,
Since only 908-2,... Are charged, the time constant of CR is short, and a steady state is established immediately. Therefore, the reset pulse application timing can be advanced, and the noise cancel operation can be performed in a short time. In the case of a television signal, the noise cancellation operation needs to be performed within the horizontal blanking period, and it is a great advantage that noise can be accurately canceled in a short time. Furthermore, since the impedance of the noise canceller viewed from the unit cell is the same between the time of signal plus noise output and the time of noise output included in the noise canceling operation, noise can be accurately canceled.

That is, when the "noise component" is output and when the "signal component + noise component" is output, the impedance of the noise canceller circuit viewed from the unit cell is substantially the same. Therefore, the noise component becomes almost the same at both outputs, and if the difference between them is taken, the noise output can be accurately removed and only the signal component can be extracted. Therefore, noise can be accurately canceled. Further, when the noise canceller circuit is viewed from the unit cell, only the gate capacitance can be seen in terms of impedance, and since the capacitance is very small, noise can be surely canceled in a short time.

Next, the element structure of the noise canceller circuit of this embodiment will be described.

As can be seen from the circuit configuration of FIG. 36, since the clamp capacitor 932 and the sample hold capacitor 934 are directly connected and close to each other, they can be stacked and formed on the same surface, and the noise canceller circuit portion Can be reduced in size.

More specifically, as shown in FIG. 43, a sample hold capacitor 34 is formed by forming a first electrode 876 on a silicon substrate 872 with a first insulating film 874 interposed therebetween. The clamp capacitor 832 is formed by forming the second electrode 880 over the one electrode 876 with the second insulating film 878 interposed therebetween.

As is clear from this figure, the first electrode 876 serves as a common electrode, and the clamp capacitor 832 and the sample hold capacitor 834 are formed in a stacked manner. The same capacitance value can be obtained.

In this embodiment, the unit cell P4-1-
1, P4-1-2,... And peripheral circuits such as the vertical address circuit 905 and the horizontal address circuit 913 are formed on a semiconductor substrate having ap ⁺ -type impurity layer formed on a p ^-- type substrate.

FIG. 44A and FIG. 44B are cross-sectional views of such a semiconductor substrate.

As shown in FIG. 44A, the p ⁻ type substrate 8
Cell elements such as a photodiode 883 are formed on a semiconductor substrate in which ap ⁺ -type impurity layer 882 is formed on 81.

[0296] By the semiconductor substrate to such a configuration, p ^- / by diffusion potential at the p ⁺ boundary, p ^- the dark current generated in the mold board 81 to prevent a part from flowing to the p ⁺ side Can be.

The result of analyzing the flow of electrons in detail will be briefly described. For electrons generated on the p ⁻ side, the thickness L of the p ⁺ impurity layer 882 is a multiple of the concentration of p ⁺ and p ⁻ , that is, L ·
p ⁺ / p ^- to look.

That is, as shown in FIG. 44B, the distance from the p ^- substrate 881, which is the source of the dark current, to the photodiode 883 appears to be ^{p.sup. +} / P.sup. ^- fold. Some dark currents are generated in the depletion layer near the photodiode 883 in addition to those flowing from the deep part of the substrate. The dark current generated in the depletion layer is almost the same as the dark current flowing from the deep part of the substrate. The thickness of the depletion layer is about 1 μm, and the dark current flowing from the deep part of the substrate also flows from a depth of about 100 μm. This depth is called an electron diffusion distance inside the p-type semiconductor. The reason why the dark current is the same despite the difference in thickness is that the probability of occurrence of dark current per unit volume is higher inside the depletion layer. Here, since the dark current generated in the depletion layer cannot be separated from the signal current in principle, the dark current is reduced by reducing the component flowing from the deep part of the substrate.

Further, since cells are formed on the semiconductor substrate in which the p ⁺ -type impurity layer 72 is formed on the p ^-- type substrate 71, fluctuation of the substrate potential due to generation of dark current can be prevented, and the p-type Since the substrate is thick, the resistance is low, and the noise elimination circuit can be reliably operated as described later.

This is important because, when the element temperature rises, the components from the deep part of the substrate increase more rapidly.
The standard is that the component from the deep part of the substrate is sufficiently smaller than the component generated in the depletion layer. Specifically, the dark current from the deep part of the substrate is about one order of magnitude lower than that from the inside of the depletion layer. I just need. That is, p ⁺ / p ⁻ may be set to 10 and the depth from the substrate may be reduced to about 1/10.

Furthermore, it can be said that there is almost no dark current from the deep part of the substrate in the semiconductor substrate composed of the n-type substrate and the p-type well. It is necessary to set p ⁺ / p ⁻ to 100 and reduce the dark current from the deep part of the substrate to about 1/100.

In a conventional CCD having a proven track record, the impurity concentration of the n-type buried channel is about 10 ¹⁶ cm ⁻³ , and the p-type surrounding the buried channel for stably manufacturing the buried channel diffusion layer. The impurity concentration of the layer (here, the p-type substrate) is about 10 ¹⁶ cm ⁻³ .

[0303] p ⁺ concentration of the layer is p ⁺ / p ^- about 10 ¹⁶ cm ^-3 about the case of the 10, p ⁺ / p ^- If you 100 becomes about 10 ¹⁷ cm ^-3, n-type Of the buried channel is about 10 ¹⁶ cm ^-3 or reversed by one digit.

For this reason, it has not been conceived to use a p ⁺ layer having such an impurity concentration in a CCD which has been conventionally used. Further, when the concentration of the p ⁻ layer is reduced, there is a problem that the sheet resistance of the substrate increases.

However, since there is no buried channel of the CCD in the amplification type MOS imaging device, the value of p ⁺ / p ⁻ can be set to some extent freely without lowering the concentration of the p ⁻ layer.

Therefore, a cell can also be formed by lowering the resistance of the p-type well and improving the structure of the semiconductor substrate composed of the n-type substrate and the p-type well.

FIG. 45 is a sectional view of a unit cell using ap ⁺ well 886 having a low sheet resistance on an n-type substrate 885. FIG. 46 is a sectional view of a unit cell of the CCD.

The n-type substrate 887, p-type well 886, and n-type buried channel 889 of the CCD unit cell have an impurity concentration of about 10 ¹⁴ cm for stable production.
^-3 , about 10 ¹⁶ cm ^-3 , and about 10 ¹⁶ cm ^-3 .

Since the impurity concentration of the n-type photodiode 890 can be set freely to some extent, there is not much restriction on manufacturing. The sheet resistance of the p-type well 886 is about 100 kΩ / □ at the above impurity concentration. As described above, the CCD has very small noise even at such a high value.

On the other hand, when a noise elimination circuit is used in an amplification type MOS imaging device, the sheet resistance of the p-type well is very important. Because p due to the reset pulse
This is because the time during which the potential disturbance of the mold well 886 subsides must be matched to the system to which this apparatus is applied.

In the NTSC system, which is the current television system, the operation of the noise elimination circuit is performed during a horizontal retrace period of about 11 [μs]. During this time, the disturbance of the potential of the p-type well 886 needs to be reduced to about 0.1 [mV].

The very small value of 0.1 [mV] is attributable to the noise voltage output of the CCD of this level. 0.1 in a very short time of 11 [μs].
To settle down to a very small value of 1 [mV],
According to a detailed analysis, the sheet resistance of the p-type well 886 is 1 k
Ω / □ or less. This is a conventional CCD
About 1/100 of the above.

For this purpose, it is necessary to increase the impurity concentration of the p-type well 886 by about 100 times, which is impossible with a CCD as described above for the p-type substrate. Furthermore, in the HDTV system, the horizontal retrace period is 3.7.
7 [μs], and the sheet resistance of the p-type well 886 is 3
It should be less than 00Ω / □.

As another modification, a high concentration p ⁺ -type sandwich layer may be formed on the substrate, and the surface may be a lower concentration p-type layer.

FIG. 47 shows a p ^- type substrate 91 and a p-type layer 893.
FIG. 10 is a diagram showing a configuration of a semiconductor substrate in which ap ⁺ -type sandwich layer 892 is formed between. FIG. 48 shows a p ⁺ -type sandwich layer 8 between an n-type substrate 895 and a p-type layer 897.
It is a figure showing composition of a semiconductor substrate in which 96 was formed.

[0316] Such a p ⁺ -type sandwich layer can be realized by a high-acceleration megavolt ion implanter.

In the p-type layer, in addition to a photodiode 883 and a transistor which are constituent elements of a unit cell,
Peripheral circuits such as a horizontal address circuit and a vertical address circuit are also formed.

FIG. 49 shows a case where a photodiode 883 is surrounded by a high-concentration p-type well 1103 and an n-type substrate 110 is formed.
FIG. 4 is a diagram showing a configuration of a semiconductor substrate configured by forming another portion on the first substrate with another p-type well 1102.

[0319] By employing such a structure, it is possible to prevent dark current from leaking into the photodiode 883. Note that the semiconductor substrate 1101 may be a p ^- type substrate.

Further, the concentration of the p-type well forming a part or all of the horizontal address circuit and the vertical address circuit around the cell is determined by the circuit design, and differs from the optimum value of the cell. It is also conceivable to use a different p-type layer from the p-type well to be formed.

FIG. 50 shows a configuration of a semiconductor substrate in which a p-type well 1106 forming an imaging region is formed on an n-type substrate 1105 and another p-type well 1107 forming a peripheral circuit portion is separately formed. FIG.

With this configuration, a p-type well suitable for each component can be formed. Note that the n-type substrate 1105 may be a p ^- type substrate.

In FIG. 51, ap ⁺ -type sandwich layer 1108 and a low-concentration p-type layer 1109 for forming an imaging region are formed on an n-type substrate 1105, and another p-type well 1107 is formed in a peripheral circuit portion. Things.

With such a configuration, a p-type well suitable for each component can be formed, and leakage of dark current into the photodiode can be prevented. Note that the n-type substrate 1105 may be a p ^- type substrate.

As described above, according to the present embodiment,
Since the output of the unit cell is output via the noise canceller circuit, it is possible to suppress the fixed pattern noise according to the characteristic variation of the amplification transistor of the unit cell. In the noise canceller circuit, the clamp capacitance 9
.., 932-1, 932-2,... (Hereinafter collectively referred to as 932; the same applies to other subscripted members) and the sample-and-hold capacitor 934 are directly connected and close to each other. The capacitor can be formed by stacking them on top of each other, and the capacity can be reduced.

Further, since the output of the unit cell is supplied to the noise canceller via the impedance conversion circuit, the impedance of the noise canceller as viewed from the unit cell is substantially the same between the time of noise output and the time of signal plus noise output. The noise component is almost the same at both outputs, and by taking the difference between them, the noise output can be accurately removed, and only the signal component can be extracted, and the noise can be accurately canceled. When the noise canceller is viewed from the unit cell, only the gate capacitance can be seen in terms of impedance, and since the capacitance is very small, noise can be surely canceled in a short time.

Further, a unit cell is formed by using, as a semiconductor substrate for forming a unit cell, a substrate composed of a p − -type impurity substrate and a p + -type impurity layer formed on the p − -type impurity substrate. Dark current can be reduced,
And since the potential of the substrate surface can be stabilized,
The noise elimination circuit (noise canceller circuit) can be reliably operated.

Note that the above-described noise canceller circuit portion shown in the sixteenth embodiment is an example, and other known circuits can be applied.

As described above, according to the present invention, the photoelectric conversion gain in the unit cell is increased to obtain high sensitivity, and the noise from the vertical signal line or the like to the gate of the amplification transistor via the parasitic capacitance is suppressed. Thus, a solid-state imaging device capable of realizing low noise can be obtained. Further, a high-resolution, high-quality application device using the high-sensitivity, low-noise solid-state imaging device can be obtained.

The present invention is not limited to the above specific examples, but can be implemented with various modifications.

[0331]

As described above, according to the present invention, high sensitivity can be obtained by increasing the photoelectric conversion gain in the unit cell, and
It is possible to provide a solid-state imaging device capable of suppressing noise from entering a gate of an amplification transistor from a vertical signal line or the like via a parasitic capacitance and realizing low noise.

Further, it is possible to provide a high-resolution, high-quality application device using the high-sensitivity, low-noise solid-state imaging device.

[Brief description of the drawings]

FIG. 1 is a plan view of a unit cell of a solid-state imaging device according to a first embodiment of a solid-state imaging device of the present invention.

FIG. 2 is a plan view of a unit cell of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 3 is a circuit configuration diagram for describing an operation of the solid-state imaging device in FIG. 2;

FIG. 4 is a partial sectional view of a unit cell of the solid gift device shown in FIG. 2;

5A is a diagram showing a cell pattern of a basic amplification type solid-state imaging device, FIG. 5B is a circuit diagram of one cell corresponding to FIG. 5A, and FIG. FIG. 3 is a diagram illustrating an example of a circuit.

6A and 6B are diagrams for explaining the operation principle of an embedded transistor, in which FIG. 6A is a plan view of the embedded transistor,
(B)-(d) is a potential diagram of each part during a signal holding period, a reset period, and after a reset, respectively.

FIG. 7 is a diagram showing an example of the arrangement of active regions when a buried transistor is used.

FIG. 8 is a circuit configuration diagram of a cell when an embedded transistor is used.

FIG. 9 shows a third embodiment of the present invention and is a cell pattern diagram of an amplification type solid-state imaging device.

FIG. 10 shows a fourth embodiment of the present invention.
It is a cell pattern diagram of an amplification type solid-state imaging device.

FIG. 11 is a timing chart illustrating the operation of the fourth embodiment.

FIG. 12 is a layout view of a light-shielding film opening showing an example for improving the photoelectric conversion efficiency of a cell.

FIG. 13 is an arrangement diagram showing an example in which the light-shielding film openings are made equal in order to improve the photoelectric conversion efficiency of the cell.

FIG. 14 is a layout diagram showing another example in which the light-shielding film openings are made equal in order to improve the photoelectric conversion efficiency of the cell.

FIG. 15 is a layout diagram of photodiodes showing a first example formed by changing the collection efficiency of photogenerated carriers in a photoelectric conversion unit in a semiconductor substrate.

FIG. 16 is a layout diagram of a photodiode showing a second example formed by changing the collection efficiency of photogenerated carriers in a photoelectric conversion unit in a semiconductor substrate.

FIG. 17 is a layout diagram of a photodiode showing a third example formed by changing the collection efficiency of the photo-generated carriers of the photoelectric conversion unit in the semiconductor substrate.

FIG. 18 is a plan view of a conventional amplification type solid-state imaging device.

19 is a circuit diagram of a unit cell of the conventional amplification type solid-state imaging device shown in FIG.

FIG. 20 is a plan view of a unit cell showing another example of the conventional amplification type solid-state imaging device.

21 is a cross-sectional view of the solid-state imaging device shown in FIG. 20, taken along line AA '.

FIG. 22 is a diagram illustrating a basic configuration of a solid-state imaging device.

FIG. 23 is a diagram illustrating a general configuration of a device using a MOS sensor as an image detection unit.

FIG. 24 is a sectional view showing an example of a MOS imaging device having a configuration in which a color filter array 104 and a MOS sensor 105 are integrated.

FIG. 25 is a view for explaining the fifth embodiment of the present invention, and is a configuration diagram showing an example of a video camera using a MOS sensor according to the present invention.

FIG. 26 is a diagram for explaining the sixth embodiment of the present invention, and is a configuration diagram showing an example of another video camera using a MOS sensor according to the present invention.

FIG. 27 is a diagram for explaining the seventh embodiment of the present invention, and is a diagram for explaining an application example of the amplifying MOS sensor in the present invention in a network system.

FIG. 28 is a diagram for explaining the eighth embodiment of the present invention, and is a diagram for explaining an application example of the amplifying MOS sensor according to the present invention to a still camera.

FIG. 29 is a diagram for explaining the ninth embodiment of the present invention, and is a diagram showing an example of a facsimile apparatus using a MOS sensor according to the present invention.

FIG. 30 is a view for explaining the tenth embodiment of the present invention, and is a view showing an example of an electronic copying machine using a MOS sensor according to the present invention.

FIG. 31 is a view for explaining an eleventh embodiment of the present invention, and is a view showing an example of a handy image scanner using a MOS sensor according to the present invention.

FIG. 32 is a diagram for explaining the twelfth embodiment of the present invention, and is a diagram illustrating a configuration example of an amplification type MOS sensor using a mechanical switching type color filter.

FIG. 33 is a diagram for explaining a thirteenth embodiment of the present invention, and is a diagram for explaining an application example of an amplifying MOS sensor according to the present invention to a film scanner device.

FIG. 34 is a diagram illustrating a fourteenth embodiment of the present invention, and is a diagram illustrating an example of a single-lens reflex camera with an autofocus mechanism using a MOS sensor according to the present invention.

FIG. 35 is a diagram for explaining the principle of focusing by the autofocus mechanism.

FIG. 36 is a diagram for describing the fifteenth embodiment of the present invention, and is a circuit diagram illustrating a configuration example of a MOS solid-state imaging device.

FIG. 37 is a diagram illustrating a circuit configuration example of a vertical address circuit according to a fifteenth embodiment.

FIG. 38 is a diagram illustrating another example of the circuit configuration of the vertical address circuit according to the fifteenth embodiment;

FIG. 39 is a diagram illustrating still another example of the circuit configuration of the vertical address circuit according to the fifteenth embodiment;

FIG. 40 is a timing chart showing the operation of the fifteenth embodiment.

FIG. 41 is a circuit diagram showing a configuration of a conventional example of a MOS solid-state imaging device.

FIG. 42 is a timing chart showing the operation of the conventional MOS solid-state imaging device shown in FIG.

FIG. 43 is a cross-sectional view showing a device structure of a noise canceller part according to a fifteenth embodiment.

FIG. 44 is a sectional view showing a device structure of a unit cell according to the fifteenth embodiment.

FIG. 45 is a diagram showing a modification of the semiconductor substrate in the unit cell part according to the fifteenth embodiment;

FIG. 46 is a sectional view of a conventional cell of a CCD solid-state imaging device.

FIG. 47 is a diagram showing another modification of the semiconductor substrate in the unit cell part according to the fifteenth embodiment;

FIG. 48 is a view showing still another modified example of the semiconductor substrate in the unit cell part according to the fifteenth embodiment;

FIG. 49 is a view showing still another modification of the semiconductor substrate in the unit cell part according to the fifteenth embodiment;

FIG. 50 is a diagram showing still another modification of the semiconductor substrate in the unit cell part according to the fifteenth embodiment;

FIG. 51 is a diagram showing still another modified example of the semiconductor substrate in the unit cell part according to the fifteenth embodiment;

[Explanation of symbols]

 20, 35 ... element region 21, 36 ... first diode 22, 37 ... second diode 23, 38 ... gate wiring of the first read transistor 24, 39 ... gate wiring of the second read transistor 25, 40 ... Drains of first read transistor 26, 41 Jump wiring 27, 42 Gate of amplifying transistor 28, 43 Drain of amplifying transistor 29, 44 Source of amplifying transistor 30, 45 Element region of reset transistor 31, 46 Reset transistor source 32, 47 ... reset transistor gate wiring 33, 48 ... reset transistor drain 49 ... address transistor gate wiring 50 ... photodiode 51 ... readout line 52 ... readout transistor 53 ... amplification transistor 54 ... vertical signal Line 55: Reset transistor 56: Address capacitor.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Michio Sasaki, Inventor, Toshiba R & D Center, Komukai Toshiba-cho, Kawasaki City, Kanagawa Prefecture (72) Ryohei Miyakawa, Ryohei Miyagawa Komukai Toshiba, Saiwai-ku, Kawasaki No. 1 in the Toshiba R & D Center, Inc. (72) Inventor Hiroshi Yamashita 1 in Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Prefecture In the Toshiba R & D Center, Inc. No. 1, Komukai Toshiba-cho, Tokyo, Japan Toshiba R & D Center (72) Inventor Tetsuya Yamaguchi No. 1, Komukai Toshiba-cho, Kawasaki-shi, Kanagawa, Japan Toshiba R & D Center (72) Inventor Hisanori Ihara, Kanagawa 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi

Claims (6)

[Claims] 1. A photodiode for generating an electric signal corresponding to an amount of received light, an amplification transistor for amplifying and outputting an output signal of the photodiode, a control electrode of the amplification transistor as a drain, and the photodiode as a source. A plurality of photoelectric conversion cells each having a MOS-type read transistor, wherein the drain of the read transistor has a plurality of element forming regions. apparatus. 2. A photoelectric conversion storage unit, an amplification transistor for inputting an output of the photoelectric conversion storage unit to a control electrode, a vertical selection line capacitively coupled to the control electrode of the amplification transistor, and a potential of the photoelectric conversion storage unit. An imaging region in which unit cells each having a reset transistor for resetting a transistor are arranged in a two-dimensional matrix on a semiconductor substrate; a power supply line of the amplification transistor and the reset transistor; and a first for reading a current of the amplification transistor. A plurality of vertical signal lines arranged in one direction, a plurality of horizontal selection transistors provided at one end of the vertical signal line, horizontal selection means for sequentially providing a selection pulse signal to the gate of the horizontal selection transistor, And a horizontal signal line for reading a signal current from the vertical signal line via a transistor. A lower electrode composed of a gate of the amplifying transistor, the solid-state imaging apparatus characterized by comprising a capacitance means having an upper electrode composed of the vertical selection line covering the lower electrode. 3. A photodiode, a transfer transistor for transferring a signal of the photodiode, a detection unit for detecting a signal transferred by the transfer transistor, an amplification transistor having a gate connected to the detection unit,
In a solid-state imaging device in which a unit cell including an address unit for activating this amplification transistor and a reset unit for discharging the signal of the photodiode is arranged in a matrix two-dimensionally on a semiconductor substrate, A solid-state imaging device, wherein a potential barrier is formed between the drain of the amplification transistor and the potential of the detection unit is changed to discharge electrons across the potential barrier to the drain to perform reset. 4. A unit cell comprising a photodiode, an amplifying transistor for inputting a signal of the photodiode to a gate, address means for activating the amplifying transistor, and a reset transistor for discharging the signal of the photodiode. In a solid-state imaging device arranged in a two-dimensional matrix on a semiconductor substrate, the photodiode and the drain of the amplification transistor constitute the source and the drain of the reset transistor. . 5. An imaging area in which unit cells having a photoelectric conversion unit and an amplification transistor are two-dimensionally arranged in a matrix on a semiconductor substrate; vertical selection means for selecting a readout row of the imaging area; In a solid-state imaging device comprising a signal line for reading a signal of a signal of a row selected by the means, cells in an odd-numbered row and cells in an even-numbered row are set to have mutually different photoelectric conversion efficiencies. Solid-state imaging device. 6. An optical system that receives an optical image from a subject and guides the optical image to a predetermined position, and converts the optical image guided to the predetermined position into an electric signal corresponding to the light amount of the optical image in pixel units. An image processing unit having a sensor for converting, and a signal processing unit for processing and outputting the output of the image processing unit into a predetermined form, wherein the sensor is a photoelectric conversion element arranged at the predetermined position; The solid-state imaging device according to claim 1, further comprising: an output circuit that includes an amplification MOS transistor connected to the photoelectric conversion element and amplifies and outputs an output of the photoelectric conversion element. A solid-state imaging device application system using the device.