JPH10150201A - Method for manufacturing thin film transistor - Google Patents

Abstract

(57) Abstract: A method of manufacturing a thin film transistor having an LDD structure with a simple process without using a resist mask for forming an LDD region is provided. SOLUTION: After a polysilicon thin film 50, a gate insulating film 60 and a gate electrode 70 are sequentially formed on a substrate 10,
An insulating film 80 is deposited so as to cover the gate electrode 70. When anisotropic etching is performed on the insulating film 80 from above and the etching is stopped when the surface of the gate electrode 70 appears, a sidewall 85 is formed along the side surface of the gate electrode. After this, the substrate 10
Is ion-implanted from above through the gate insulating film 60 and the sidewalls 85, a source / drain region (impurity diffusion layer) 100 and an LDD region 110 are simultaneously formed in the polysilicon thin film 50.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor used in a liquid crystal display device used for an information processing terminal or a video device.

[0002]

2. Description of the Related Art In order to improve the OFF current characteristic and characteristic fluctuation due to generation of hot carriers accompanying miniaturization of devices, an LDD structure has conventionally been adopted also in a thin film transistor. LDD is Lightly Dope
Abbreviation of d drain, drain region (impurity diffusion layer)
, A diffusion region having a lower impurity concentration than the drain region (impurity diffusion layer) (generally, this region is referred to as an LDD region) provides an impurity concentration gradient around the drain region (diffusion layer). To relax
This is to alleviate the source / drain voltage (reduce the maximum electric field strength of the drain depletion layer).

[0003]

Conventionally, when an LDD region is formed, it is necessary to add another resist mask for forming an LDD region in addition to a resist mask for forming source and drain regions (impurity diffusion layers). Yes, for this,
The addition of one resist mask increases the number of steps, resulting in a decrease in yield and an increase in cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is possible to manufacture a thin film transistor having an LDD structure by a simple process without using a resist mask for forming an LDD region. Provide a way.

[0005]

In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention is characterized in that a gate is formed on an entire surface of the glass substrate so as to cover a polysilicon thin film formed on the glass substrate. Forming an insulating film, and then forming a gate electrode on the gate insulating film, forming sidewalls along side surfaces of the gate electrode,
Thereafter, the polysilicon thin film is doped with impurities through the gate insulating film and the sidewall from above the glass substrate, so that a drain region and a lightly doped drain (LDD) region are simultaneously formed in the polysilicon thin film. . In such a method for manufacturing a thin film transistor of the present invention, it is not necessary to form a resist mask for forming an LDD region, and a drain region (impurity diffusion layer)
Since the LDD region is formed at the same time as the drain region (impurity diffusion layer) in the impurity doping step for forming a thin film transistor, a thin film transistor having an LDD structure can be easily manufactured. Further, since the LDD region is formed in a self-alignment manner between the drain region (impurity diffusion layer) and the gate electrode, a thin film transistor having a desired LDD structure can be manufactured with high yield.

In the method of manufacturing a thin film transistor according to the present invention, in the step of forming the sidewall, an insulating film is formed so as to cover the gate electrode over the entire surface of the substrate, and then the insulating film is formed on the insulating film from above. Preferably, the step of performing anisotropic etching until the upper surface of the gate electrode is exposed to leave the insulating film on a side portion of the gate electrode. With such a configuration, the shape of the sidewall is changed to the end of the gate electrode. As the distance from the portion increases, the thickness of the LDD region becomes smaller, and the LDD region has an impurity concentration gradient in which the impurity concentration is sequentially reduced from the side closer to the drain region to the side farther from the drain region corresponding to the shape of the sidewall.
As a result, a thin film transistor with further improved OFF current characteristics can be manufactured.

Further, in the method of manufacturing the thin film transistor having the preferable configuration, it is more preferable that the method further includes a step of patterning the gate insulating film in the same pattern as the gate electrode prior to the step of forming the sidewall.
With such a configuration, the sidewall is formed along the side surface of the gate electrode and the side surface of the gate insulating film, and the width of the sidewall increases according to the thickness of the gate insulating film. Therefore, by adjusting the thickness of the gate insulating film, it is possible to prevent a problem that the width of the LDD region becomes too small to such an extent that the effect of improving the OFF current characteristic or the like is not substantially obtained. be able to.

The method of manufacturing a thin film transistor according to the present invention may further include a step of doping the polysilicon thin film with impurities using the gate electrode as a mask after the step of forming the gate electrode and before the step of forming the sidewall. With such a configuration, in the first impurity doping step, both the region to be the drain region and the region to be the LDD region in the polysilicon thin film have the same impurity concentration, and the second impurity doping step In the polysilicon thin film, the impurity concentration in a region to be an LDD region can be made lower than that in a region to be a drain region. Control of impurity concentration difference between LDD region and LDD region at finer level Rukoto becomes possible.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, impurities used for impurity doping for forming source / drain regions (impurity diffusion layers) in a polysilicon thin film include:
When the source / drain region is an n-type region, a group V element such as phosphorus, arsenic, or antimony is used. When the source / drain region (impurity diffusion layer) is a p-type region, boron, aluminum, gallium, or the like is used. Group III elements are used. The doping method of the impurity doping is not particularly limited, but the controllability of the doping amount of the impurity is high, the uniformity and reproducibility of the impurity in the substrate surface are excellent, and the impurity is doped in a lateral direction in the polysilicon thin film. Since the extent of the diffusion can be reduced, an ion implantation method in which impurities are ionized, accelerated to a high energy state, and implanted into the material to be doped is preferable.

In the present invention, the impurity concentration of the source / drain region (impurity diffusion layer) and the LDD region is not particularly limited, but generally, the impurity concentration of the source / drain region (impurity diffusion layer) is 1 × 10 ^17- 1 × 10 ¹⁹ /
cm ² , and the impurity concentration of the LDD region is set to 1 ×
It is set in the range of 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² .

In the present invention, the formation of the sidewall is
For example, a method of anodizing at least the side surface of the gate electrode, or forming an insulating film on the entire surface of the substrate so as to cover the gate electrode, and exposing the insulating film to the upper surface of the gate electrode from above vertically. This is performed by a method of performing anisotropic etching up to that point. In particular, when the latter insulating film covering the gate electrode is formed by anisotropic etching, the shape of the sidewall becomes smaller as the distance from the end of the gate electrode increases. Therefore,
The LDD region formed by doping the impurity through the sidewall has a concentration gradient in which the impurity concentration is gradually reduced from the side closer to the drain region to the side farther from the drain region, and the OFF current characteristics and the like of the thin film transistor are further improved. Will be. If the gate insulating film under the gate electrode is patterned in the same pattern as the gate electrode before the gate electrode is covered with the insulating film, sidewalls are formed along both side surfaces of the gate electrode and the gate insulating film. As a result, the width of the sidewall becomes larger in accordance with the thickness of the gate insulating film than in the case where the sidewall is formed without patterning the gate insulating film. That is, if the gate insulating film under the gate electrode is patterned into the same pattern as the gate electrode before covering the gate electrode with the insulating film, the width of the sidewall is not only the thickness of the gate electrode but also the thickness of the gate insulating film. Is controlled by the thickness. Therefore, for example, when it is desired to reduce the thickness of the gate electrode, by increasing the thickness of the gate insulating film, the width of the LDD region becomes too small to such an extent that an improvement effect such as the OFF current characteristic cannot be substantially obtained. It is possible to prevent the occurrence of a problem that the data is not stored.

[0012]

【Example】

(Embodiment 1) FIG. 1 is a sectional view showing the steps of manufacturing a thin film transistor according to Embodiment 1 of the present invention. Less than,
The manufacturing process will be described with reference to FIG.

First, for example, Corning 7059
An insulating film 20 made of SiO ₂ was deposited as a coating film on a glass substrate 10 made of (trade name) 2000 Å by a CVD method (FIG. 1A).

Next, after depositing an amorphous silicon thin film 30 on the insulating film 20 by 850 angstroms using a plasma CVD method, the silicon thin film 30 is patterned into a predetermined pattern, and crystallized by an excimer laser 40. To form a polysilicon thin film 50 (FIG. 1).
(B)).

Next, a gate insulating film 60 made of SiO _{2 is} deposited on the entire surface of the substrate 1 so as to cover the polysilicon thin film 50 by about 1000 Å by using a normal pressure CVD method. An aluminum film was deposited on the film 60 to a thickness of about 3000 angstroms by a sputtering method, and the aluminum film was patterned to form a gate electrode 70 (FIG. 1C).

Next, an insulating film 80 made of SiO _{2 is} deposited to a thickness of about 3000 angstroms by, for example, a CVD method so as to cover the gate electrode 70 (FIG. 1).
(D)) Anisotropic etching was performed from above the insulating film 80 to form sidewalls 85 on the side surfaces of the gate electrode 70 (FIG. 1E). Here, by stopping the anisotropic etching when the surface of the gate electrode 70 appears, an oxide film (side wall 8) is formed on the side surface of the gate electrode 70.
5) was left. The width of this sidewall 85 is 0.3
μm. Thereafter, the polysilicon thin film 50 is formed.
Impurity ions (phosphorous ions) 90 toward 70
Are accelerated by the energy of KeV are implanted, the source-drain region (impurity diffusion layer) 100 and the impurity concentration of the impurity concentration in the polysilicon thin film 50 is 10 ¹⁷ / cm ³ is formed to 10 ¹⁵ / cm ³ of the LDD region 110 (Fig. 1
(F)). Here, a region where neither the gate electrode 70 nor the sidewall 85 is formed on the upper surface of the polysilicon thin film 50 is an impurity source / drain region (impurity diffusion layer) 100, and the sidewall 85 is formed on the upper surface. The region becomes the LDD region 110 (FIG. 1)
(F)). Thereafter, a source / drain electrode joined to the source / drain region (impurity diffusion layer) 100 was formed according to a conventional method, and a thin film transistor was completed.

In the method of manufacturing a thin film transistor according to the present embodiment, the impurity ions 90 are implanted toward the entire surface of the polysilicon thin film 50 without using a resist mask for forming an LDD region. The portion of the silicon thin film 50 located below the sidewall 85 formed on the side surface of the gate electrode 70 becomes the LDD region 110, and this LDD region 110 is formed between the source / drain region (impurity diffusion layer) 100 and the gate electrode 70. It is formed in a self-aligned manner therebetween. Therefore, a thin film transistor having good OFF current characteristics and the like can be manufactured easily and with good reproducibility.

(Embodiment 2) FIG. 2 is a sectional view showing the steps of manufacturing a thin film transistor according to Embodiment 2 of the present invention. Hereinafter, the manufacturing process will be described with reference to the drawings. Note that the steps from FIG. 2A to FIG. 2C are the same as the steps from FIG. 1A to FIG.

After forming the gate electrode 70 by performing the same steps as those shown in FIGS. 1A to 1C of the first embodiment (FIGS. 2A to 2C), Using the gate electrode 70 as a mask, impurity ions (phosphorus ions) 75 are accelerated at an energy of 90 KeV and implanted into the polysilicon thin film 50 to form an impurity diffusion layer 76 having an impurity concentration of 10 ¹⁷ / cm ³ (FIG. 2 ( d)). Note that the impurity concentration of the impurity diffusion layer 76 needs to be lower than the final impurity concentration of the target LDD region.

Next, an insulating film 80 made of SiO _{2 is} deposited to a thickness of about 3000 angstroms by, for example, a CVD method so as to cover the gate electrode 70 (FIG. 2).
(E)) Anisotropic etching was performed on the entire surface to form sidewalls 85 on the side surfaces of the gate electrode 70 (FIG. 2 (f)). Here, the anisotropic etching was stopped when the surface of the gate electrode 70 appeared, so that the insulating film (side wall 85) was left on the side surface of the gate electrode 70. The width of the sidewall 85 was 0.3 μm.

Next, impurity ions (phosphorus ions) 90 is accelerating at an energy of 70KeV ion-implanted toward the entire surface (entire surface of the substrate 1) of the polysilicon thin film 50, the impurity concentration in the polysilicon thin film 50 is 10 ¹⁷ / source and drain regions (impurity diffusion layer) 100 and the impurity concentration of cm ³ was formed LDD regions 110 of 10 ¹⁵ / cm ³ (Fig. 2 (g)). Thereafter, a source / drain electrode joined to the source / drain region (impurity diffusion layer) 100 was formed according to a conventional method, and a thin film transistor was completed.

In the method of manufacturing a thin film transistor according to the present embodiment, similarly to the method of manufacturing the thin film transistor according to the first embodiment, the side surface of the gate electrode 70 can be formed without using a resist mask for forming an LDD region. By utilizing the formed sidewall 85, the LDD region 110 can be formed between the diffusion layer (source or drain) 100 and the gate electrode 70 in a self-aligned manner. Therefore, a thin film transistor having good OFF characteristics can be easily manufactured with good reproducibility. In the manufacturing method of this embodiment, the source / drain regions (impurity diffusion layers) 1 of the polysilicon thin film 50 are formed by the first ion implantation.
Both the region to become 00 and the region to become the LDD region 110 have the same impurity concentration, and the region to become the source / drain region (impurity diffusion layer) 100 using the sidewalls 85 in the second ion implantation. And LDD region 1
Since the impurity concentration of the region to be 10 is made different, the necessary impurity in the source / drain region (impurity diffusion layer) is secured, and the impurity concentration of the source / drain region (impurity diffusion layer) 100 and the LDD region It is possible to control the difference between the impurity concentrations of 110 at a finer level. Therefore, it is possible to prevent a problem that the impurity concentration of the LDD region 110 becomes too low.

(Embodiment 3) FIG. 3 is a sectional view showing the steps of manufacturing a thin film transistor according to Embodiment 3 of the present invention. Hereinafter, the manufacturing process will be described with reference to the drawings. The steps from FIG. 3A to FIG. 3C are the same as the steps from FIG. 1A to FIG.

After forming the gate electrode 70 by performing the same steps as those shown in FIGS. 1A to 1C of the first embodiment (FIGS. 3A to 3C), The gate insulating film 60 was subjected to anisotropic etching using the gate electrode 70 as a mask to pattern the gate insulating film 60 into a pattern similar to that of the gate electrode 70 (FIG. 3D).

Next, the gate electrode 70, the gate insulating film 60 and the polysilicon thin film 50 are covered with SiO ₂
The insulating film 80 made of, for example, 3000
After depositing about Å (FIG. 3E), this was patterned by anisotropic etching to form sidewalls 85a on the side surfaces of the gate electrode 70 and the gate insulating film 60 (FIG. 3F). The width of the sidewall 85a was 0.5 μm.

Then, impurity ions (phosphorous ions) 90 are accelerated at an energy of 70 KeV and ion-implanted toward the entire surface of the polysilicon thin film 50.
The source / drain region (impurity diffusion layer) 100 having an impurity concentration of 10 ¹⁷ / cm ³ and an impurity concentration of 10 ¹⁵ / cm 3
^Three LDD regions 110 were formed (FIG. 3G). Thereafter, source / drain electrodes to be joined to the source / drain regions (impurity diffusion layers) 100 are formed according to a conventional method,
A thin film transistor was completed.

In the method of manufacturing the thin film transistor of the present embodiment, similarly to the method of manufacturing the thin film transistor of the first embodiment, the sidewalls 85a formed on the side surfaces of the gate electrode 70 are formed without using a resist mask.
, The LDD region 110 can be formed between the diffusion layer (source or drain) 100 and the gate electrode 70 in a self-aligned manner. Therefore, a thin film transistor having good OFF characteristics can be easily manufactured with good reproducibility. In the manufacturing method of the present embodiment, the sidewalls 85a are formed along the side surfaces of the gate electrode 70 and the side surfaces of the gate insulating film 60. Therefore, the width (0.5 μm) of the sidewalls 85a is The width of the sidewalls 85 formed only along the side surfaces of the gate electrode 70 in Examples 1 and 2 (0.3 μm) was larger than that of the sidewalls 85. As a result, the width of the LDD region 110 was also larger.

The present invention is not limited to the above embodiments, and it goes without saying that the materials and dimensions of each part of the thin film transistor and the method of forming each layer (film forming method) can be changed.

[0029]

As described above, according to the method of manufacturing a thin film transistor of the present invention, a gate insulating film is formed on the entire surface of a glass substrate so as to cover a polysilicon thin film formed on the glass substrate. After forming a gate electrode on the gate insulating film, a sidewall is formed along the side surface of the gate electrode, and thereafter, the polysilicon thin film is passed from above the glass substrate through the gate insulating film and the sidewall. , And simultaneously forming a drain region and an LDD region in the polysilicon thin film, it is not necessary to form a resist mask for forming an LDD region, and the LDD structure can be simply and self-aligned. As a result, thin film transistors having good OFF characteristics can be manufactured with high yield. Kill.

In the method of manufacturing a thin film transistor according to the present invention, in the step of forming a sidewall, an insulating film is formed on the entire surface of the substrate so as to cover the gate electrode, and then the insulating film is formed on the insulating film from above. In a preferred embodiment, the step of performing anisotropic etching until the upper surface of the gate electrode is exposed to leave the insulating film on the side of the gate electrode reduces the impurity concentration sequentially from the side closer to the drain region to the side farther from the drain region. LD with improved impurity concentration gradient
The D region can be formed, and as a result, a thin film transistor with further improved OFF current characteristics and the like can be manufactured.

In the method of manufacturing a thin film transistor according to the preferred embodiment of the present invention, prior to the step of forming the side wall, a step of patterning the gate insulating film in the same pattern as the gate electrode is performed, so that the width of the side wall is reduced. The thickness can be increased by the thickness of the film, and as a result, it is possible to prevent a problem that the width of the LDD region becomes too small to such an extent that the effect of improving the OFF current characteristic or the like cannot be substantially obtained. be able to. Therefore, a thin film transistor with further improved OFF current characteristics and the like can be manufactured with a higher yield.

In a preferred embodiment, the method for manufacturing a thin film transistor according to the present invention further comprises a step of doping the polysilicon thin film with impurities using the gate electrode as a mask after the step of forming the gate electrode and before the step of forming the sidewall. As a result, the difference in impurity concentration between the drain region and the LDD region can be controlled at a finer level than in the case where the LDD region is formed by a single impurity doping step, and a thin film transistor having desired characteristics can be reproduced. Can be manufactured well.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to Embodiment 2 of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to Embodiment 3 of the present invention.

[Explanation of symbols]

10 glass substrate 20 SiO ₂ 30 amorphous silicon thin film 40 excimer laser (light) 50 polysilicon thin film 60 gate insulating film 70 gate electrode 75 impurity ions 76 impurity diffusion layer 80 insulating film 85 side wall 85a sidewall 90 impurity ions 100 Source / drain region (impurity diffusion layer) 110 LDD region

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ikunori Kobayashi 1006 Kazuma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] Forming a gate insulating film on an entire surface of the glass substrate so as to cover a polysilicon thin film formed on the glass substrate; forming a gate electrode on the gate insulating film; A sidewall is formed along the side surface of the gate electrode. Thereafter, the polysilicon thin film is doped with impurities through the gate insulating film and the sidewall from above the glass substrate, and a drain region and an LDD are formed in the polysilicon thin film. (Lightly dope
d drain) A method for manufacturing a thin film transistor in which regions are simultaneously formed. 2. A method for forming a sidewall, comprising: forming an insulating film over the entire surface of a substrate so as to cover a gate electrode; and forming a sidewall on the insulating film until the upper surface of the gate electrode is exposed. 2. The method according to claim 1, wherein the step of performing anisotropic etching leaves the insulating film on a side of the gate electrode. 3. Prior to the step of forming a sidewall,
3. The method according to claim 2, wherein the gate insulating film is patterned in the same pattern as the gate electrode. 4. The thin film transistor according to claim 1, further comprising a step of doping impurities into the polysilicon thin film using the gate electrode as a mask after the step of forming the gate electrode and before the step of forming the sidewall. Manufacturing method.