JPH10164035A - Synchronization switching device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate influence supplied by phase matching detection by the frame header of frame data signals while synchronization changeover to a spare system is performed when the phases of the data signals of both systems match and when the signals of an active system are degraded at the time of the active/spare changeover of the frame data signals. SOLUTION: Based on the output frame pulse signals CF of a synchronization switching circuit 9, masking signals E are generated in a timing generation circuit 10 in the present period of the frame header. In a phase matching detection circuit 7, the matching state of the phases of the data signals AD and BD of the two systems is detected, however, the phase matching detection is suppressed during the masking signals and the influence of the frame header is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous switching device, and more particularly to a synchronous switching device, in which the phase coincidence of the same frame data signal transmitted through two redundant lines is detected and a phase coincidence state is detected when a phase coincidence state is detected. The present invention relates to a synchronous switching device that switches from one system to the other system when the frame data signal is deteriorated.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a digital microwave communication system to which a synchronous switching device of this kind is applied. Referring to FIG. 5, the input signal S21 on the transmission side is converted into a signal form suitable for signal processing, for example, an NRZ signal of eight columns in the interface circuit 21, and the working line 33
Signal processing circuit 23 and protection line 34 signal processing circuit 24
Respectively.

The signal processing circuit 23 performs signal processing such as insertion of an overhead signal on the signal of the working line 33,
The modulation circuit 25 modulates and outputs the output signal of the signal processing circuit 23. Similarly, the signal processing circuit 24 performs signal processing such as insertion of an overhead signal on the signal of the protection line 34, and the modulation circuit 26 modulates and outputs the output signal of the signal processing circuit 24.

On the receiving side, the signal received by the demodulator 27 of the working line is demodulated, and the signal processing circuit 29 performs signal processing such as termination of an overhead signal. Similarly, the signal of the protection channel is demodulated with respect to the signal received by the demodulator 28, and the signal processing circuit 30 performs signal processing such as termination of an overhead signal.

[0005] The synchronization switching circuit 31 receives the output signal of the signal processing circuit 29 of the working line and the output signal of the signal processing circuit 30 of the protection line as inputs, and switches the synchronization from one to the other when the line quality deteriorates. Output to the interface circuit 32. The interface circuit 32 converts the output signal of the synchronization switching circuit 31 into a standardized signal form such as a bipolar signal or an optical signal and outputs the signal.

FIG. 6 is a block diagram showing a conventional example of the synchronous switching circuit 31 in FIG. As shown in FIG. 6, a conventional synchronous switching circuit 31 includes a fixed delay circuit 1 and a fixed delay circuit 2 for absorbing a phase difference between a data signal AD of the working line and a data signal BD of the protection line, and outputs from the fixed delay circuit 1. Frame synchronization for generating a frame pulse signal AF indicating the head position of the data frame, and frame synchronization for the data signal output from the fixed delay circuit 2 to obtain the head of the data frame. The frame synchronization circuit 4 for generating the frame pulse signal BF indicating the position is compared with the data signal output from the frame synchronization circuit 3 and the content of the data signal output from the frame synchronization circuit 4. A phase matching detection circuit 11 that outputs the phase matching detection signal S1 to the switching control circuit 8.

Further, the synchronization switching circuit 31 monitors the line deterioration signal AA of the working line and the line deterioration signal BA of the protection line, and for example, the quality of the working line deteriorates and the line deterioration signal AA
And when the line degradation signal BA of the protection line is normal, a switching control circuit 8 that sends a switching control signal S2 to the synchronization switching circuit 9 after receiving the phase coincidence detection signal S1, In accordance with the control signal S2, the synchronous switching from the working line signal to the protection line signal is performed, and the data signal C
D, a frame pulse signal CF, and a clock signal CC, a synchronization switching circuit 9, a phase comparison circuit 5 constituting a PLL circuit for suppressing a sudden phase change of the clock signal at the time of synchronization switching, and a voltage controlled oscillator (hereinafter referred to as a voltage controlled oscillator). VCO) 6.

The fixed delay circuit 1 and the fixed delay circuit 2 are delay circuits for absorbing a phase difference between the working line AD and the protection line BD. The data signal output from the fixed delay circuit 1 is input to the frame synchronization circuit 3, and the data signal output from the fixed delay circuit 2 is input to the frame synchronization circuit 4.

A frame synchronization circuit 3 performs frame synchronization on the data signal output from the fixed delay circuit 1, and outputs a frame pulse signal AF indicating the head position of the data frame.
Is output. The frame synchronization circuit 4 performs frame synchronization on the data signal output from the fixed delay circuit 2, and outputs a frame pulse signal BF indicating the head position of the data frame.
Is output.

The phase coincidence detection circuit 11 compares the data signal output from the frame synchronization circuit 3 with the data signal output from the frame synchronization circuit 4. When the contents of the data signals are equal as a result of the fixed amount comparison, a phase coincidence detection signal S1 is output to the switching control circuit 8.

The switching control circuit 8 monitors the line deterioration signal AA of the working line and the line deterioration signal BA of the protection line.
When the quality of the working line is deteriorated and the line deterioration signal AA is received, and when the line deterioration signal BA of the protection line is normal, switching to the synchronization switching circuit 9 is performed after receiving the phase coincidence detection signal S1. The control signal S2 is transmitted.

The synchronous switching circuit 9 performs synchronous switching from a signal on the working line to a signal on the protection line in accordance with the switching control signal S2, and outputs a data signal CD, a frame pulse signal CF, and a clock signal CC.

In order to suppress a sudden phase change of the clock signal at the time of synchronization switching, the phase comparison circuit 5 and the VCO are controlled based on the clock signal CC output from the synchronization switching circuit 9.
6 constitute a PLL circuit to obtain a clock signal CC output from the VCO 6.

[0014]

In the above-mentioned conventional example,
When comparing the data signals of the working line and the protection line in the phase coincidence detection circuit, all data are compared.
For this reason, when performing synchronous switching on a line that transmits an overhead signal such as an SDH (Synchronous Digital Hierarchy) signal via an intermediate relay station, the relay station inserts the end of the overhead signal.
Extra time is consumed until the phase match is detected due to the difference in overhead data content due to the difference in line,
There is a problem that the deterioration of the line quality cannot be remedied during this time.

An object of the present invention is to provide a synchronous switching device capable of detecting a phase match of a data signal without being affected by the data content of overhead.

[0016]

According to the present invention, there is provided a phase coincidence detecting means for detecting a phase coincidence of the same frame data signal transmitted on two redundant lines and having a frame header for each frame, and said phase coincidence detecting means. A switching unit for switching from one system to the other system when the frame data signal of one system is degraded when the phase matching state is detected by the match detection unit, A synchronous switching device is provided, wherein the detecting means detects the phase coincidence between two systems of data signals excluding the period of the frame header.

And a means for generating a mask signal for a period corresponding to the frame header in synchronization with a frame pulse output from the switching means. It is characterized in that it is configured to suppress the detection of the coincidence of the phases of the data signals.

Further, the frame data signal is a data signal synchronized with a clock signal, and the phase coincidence detecting means determines whether the phase of the two frame data signals coincides with each other.
It is characterized in that it includes means for judging the mismatch while synchronizing with the clock signal except for the existence period of the mask signal, and means for counting the number of matches / mismatches as the output of the judgment.

In the operation of the present invention, a frame header portion of a frame data signal is detected to generate a mask signal corresponding to the frame header portion, and the existence period of the mask signal is a phase coincidence for performing synchronous switching. The detection of the phase coincidence of the detection circuit is suppressed, and the phase coincidence of only the true data portion is detected to improve the reliability.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, a block diagram of a digital microwave communication system to which the synchronous switching device of the present invention is applied is shown in FIG.
This will be described with reference to FIG. In FIG. 4, the same parts as those in FIG. 5 are denoted by the same reference numerals.

Referring to FIG. 4, the input signal S2 on the transmitting side is shown.
1 is converted into a signal form suitable for signal processing in the interface circuit 21, for example, an NRZ signal of eight columns, and supplied to the signal processing circuit 23 of the working line 33 and the signal processing circuit 24 of the protection line 34, respectively.

The signal processing circuit 23
Performs signal processing such as insertion of an overhead signal, and the modulation circuit 25 modulates and outputs the output signal of the signal processing circuit 23. Similarly, for the signal of the protection line, the signal processing circuit 2
4 performs signal processing such as insertion of an overhead signal, and the modulation circuit 26 modulates an output signal of the signal processing circuit 24 and sends out the modulated signal.

The relay station demodulates the signal received by the demodulator 33 of the working channel, terminates and inserts the overhead signal of the received signal in the signal processing circuit 35, modulates it with the modulation circuit 37, and transmits it. Similarly, for the protection line, the signal received by the demodulator 34 is demodulated, and the signal processing circuit 3
At 6, the overhead signal of the received signal is terminated and inserted, modulated by the modulation circuit 38 and transmitted.

On the receiving side, the signal received by the demodulator 27 of the working line is demodulated, and the signal processing circuit 29 performs signal processing such as termination of an overhead signal. Similarly, the signal of the protection line is demodulated with respect to the signal received by the demodulator 28, and the signal processing circuit 30 performs signal processing such as termination of an overhead signal.

The synchronization switching circuit 31 receives as input the output signal of the signal processing circuit 29 of the working line and the output signal of the signal processing circuit 30 of the protection line, and performs synchronization switching from one to the other when the line quality is deteriorated. , To the interface circuit 32. The interface circuit 32 is a synchronous switching circuit 31
Is converted into a standardized signal form such as a bipolar signal or an optical signal and output.

FIG. 1 is a block diagram showing the configuration of the synchronization switching circuit 31 shown in FIG. 4, and the same parts as those in FIG. 6 are denoted by the same reference numerals.

The line switching circuit of the present invention comprises a fixed delay circuit 1 and a fixed delay circuit 2 for absorbing a phase difference between the data signal AD of the working line and the data signal BD of the protection line, and data output from the fixed delay circuit 1. Frame synchronization is performed on the signal to generate a frame pulse signal AF indicating the head position of the data frame. Frame synchronization is performed on the data signal output from the fixed delay circuit 2 to indicate the head position of the data frame. Based on a frame synchronization circuit 4 for generating a frame pulse signal BF and a frame pulse signal CF output from the synchronization switching circuit 9,
And a timing generation circuit 10 for generating a mask signal E for masking the overhead signal portion.

Further, the synchronization switching circuit of the present invention can output the data signal output from the frame synchronization circuit 3 and the data signal output from the frame synchronization circuit 4 only when the mask signal E output from the timing generation circuit 10 is not received. The phase matching detection circuit 7 outputs a phase matching detection signal S1 to the switching control circuit 8, and the line deterioration signal AA of the working line and the line deterioration signal BA of the protection line when the data contents are equal. For example, when the quality of the working line is deteriorated and the line deterioration signal BA of the protection line is normal, after receiving the phase coincidence detection signal S1, the switching control signal S2 is sent to the synchronous switching circuit 9. Control signal S2 and a switching control signal S2, synchronous switching is performed from the working line signal to the protection line signal, and the data signal CD and the frame pulse signal are switched. F, has a synchronous switching circuit 9 for outputting a clock signal CC, the phase comparator circuit 5 and VCO6 constituting a PLL circuit for suppressing a rapid phase variation of the clock signal when synchronizing switching.

The fixed delay circuit 1 and the fixed delay circuit 2 are delay circuits for absorbing a phase difference between the data signal AD of the working line and the data signal BD of the protection line caused by the device configuration. The delay amount of the fixed delay circuit 1 and the fixed delay circuit 2 is such that the output of the fixed delay circuit 1 and the output of the fixed delay circuit 2 are the same when the same signal is branched on the transmitting side and transmitted to the working line and the protection line. It is adjusted so as to be in phase.

The frame synchronization circuit 3 synchronizes the data signal output from the fixed delay circuit 1 with reference to the frame synchronization bytes A1 and A2 bytes in the overhead, and generates a frame pulse signal AF indicating the head position of the data frame. Generate

The frame synchronization circuit 4 performs frame synchronization on the data signal output from the fixed delay circuit 2 with reference to the frame synchronization bytes A1 and A2 bytes in the overhead, and a frame pulse signal BF indicating the head position of the data frame. Generate

The timing generation circuit 10 is a synchronous switching circuit 9
A mask signal E indicating an overhead portion is generated with reference to the frame pulse signal CF output from.

FIG. 2 is a timing chart showing the relationship between the output data of the frame synchronization circuit 3, the output data of the frame synchronization circuit 4, and the mask signal E. The mask signal E is a signal that goes high in the overhead portion of the output data of the frame synchronization circuit and goes low in the data portion.

The phase coincidence detection circuit 7 detects a phase coincidence by comparing the data of the working line and the data content of the protection line, and outputs a phase coincidence detection signal S1.

FIG. 3 is a block diagram showing the configuration of the phase coincidence detection circuit 7. An exclusive OR circuit (hereinafter referred to as an E-OR circuit) 41 receives the output data of the frame synchronization circuit 3 and the output data of the frame synchronization circuit 4 as inputs, and when the data signal of the protection line is equal to the data signal of the working line. It outputs a low level and outputs a high level if the data is different.

An AND circuit (hereinafter referred to as an AND circuit) 44 has an E-
An output of the OR circuit 41 is inverted by an inverting circuit (hereinafter referred to as an INV circuit) 43.
, And the signal obtained by inverting the mask signal E by the INV circuit 42 is input. The output of the AND circuit 44 outputs a high level when the mask signal E is at a low level and the signal of the working line and the signal of the protection line are equal, and otherwise outputs a low level.

The AND circuit 45 receives as input the output signal of the E-OR circuit 41 and a signal obtained by inverting the mask signal E by the INV circuit 42. The output of the AND circuit 45 outputs a high level when the mask signal E is at a low level and the signal of the working line is different from the signal of the protection line, and otherwise outputs a low level.

The coincidence counter 46 counts the number of high-level outputs of the AND circuit 44, and outputs a high-level pulse when the number exceeds a preset number. The non-coincidence counter 47 counts the number of high-level outputs of the AND circuit 45, and outputs a high-level pulse when the number exceeds a preset number.

The set-reset type flip-flop circuit (hereinafter referred to as RSF / F circuit) 48 changes its output to a high level when receiving a high-level pulse from the coincidence counter 46 and receives a high-level pulse from the non-coincidence counter 47. In this case, the output is set to low level. The output of the RSF / F circuit 48 is the phase coincidence detection signal S1.

The switching control circuit 8 monitors the line deterioration signal AA of the working line and the line deterioration signal BA of the protection line, and confirms that the phase match detection signal S1 is at a high level when the quality of the working line is deteriorated. After that, a switching control signal S2 is sent to the synchronous switching circuit 9. The synchronization switching circuit 9 performs synchronous switching from the signal on the working line to the signal on the protection line in accordance with the switching control signal S2, and outputs a data signal CD, a frame pulse signal CF, and a clock signal CC.

In order to suppress a sudden phase change of the clock signal at the time of synchronization switching, the phase comparison circuit 5 and the VCO are controlled based on the clock signal CC output from the synchronization switching circuit 9.
6 constitute a PLL circuit to obtain a clock signal CC output from the VCO 6.

[0043]

According to the present invention, a circuit for detecting the phases of a working line and a protection line includes a timing generating circuit for generating a mask signal used for masking an overhead signal portion in a data signal. Therefore, S
When performing synchronous switching of a signal having an overhead such as a DH signal, even if the data content of the overhead is different due to the difference of the line, the phase of the data frame of the working line and the protection line is correctly detected and the synchronization is performed. There is an effect that switching can be performed.

In the above embodiment, the case where the circuit configuration is the 1 + 1 configuration (the number of working lines: 1 line, the number of protection lines: 1 line) has been described, but the N + 1 configuration (the number of working lines: N lines, the number of protection lines: The effect is the same in the case of (one line).

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a configuration diagram of a phase coincidence detection circuit.

FIG. 4 is a block diagram of a digital microwave communication system having a relay station.

FIG. 5 is a block diagram of a digital microwave communication system.

FIG. 6 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1, 2 fixed delay circuit 3, 4 frame synchronization circuit 5 phase comparison circuit 6 VCO 7 phase coincidence detection circuit 8 switching control circuit 9 synchronization switching circuit 10 timing generation circuit 41 exclusive OR circuit 42, 43 inverter 44, 45 AND circuit 46 Match counter 47 Non-match counter 48 SR-FF (flip-flop)

Claims (3)

[Claims] 1. A phase matching detecting means for detecting the phase matching of the same frame data signal transmitted on two redundant lines and having a frame header for each frame, and a phase matching state is detected by the phase matching detecting means. When
Switching means for switching from one to the other system when degradation of the frame data signal of one of the systems occurs, wherein the phase coincidence detecting means detects the phase coincidence with the frame header. A synchronous switching device characterized in that it is performed between two systems of data signals excluding a period. 2. A means for generating a mask signal for a period corresponding to the frame header in synchronization with a frame pulse output from the switching means, wherein the phase coincidence detecting means comprises: 2. The synchronization switching device according to claim 1, wherein the synchronization switching device is configured to suppress the detection of the coincidence of the phases of the data signals. 3. The frame data signal is a data signal synchronized with a clock signal, and the phase coincidence detecting means determines whether or not the phases of the two frame data signals coincide with each other except for the existence period of the mask signal. 3. The synchronization switching device according to claim 2, further comprising: means for making a determination while synchronizing with the clock signal; and means for counting the number of matches / mismatches which are the output of the determination.