JPH10164764A - Battery capacity monitoring method - Google Patents

Abstract

(57) Abstract: In a battery capacity monitoring method used in a battery management device that calculates a battery capacity by a CPU, the power consumption when the battery is left unused is sufficiently reduced to prevent a decrease in the remaining capacity of the battery. At the same time, the remaining capacity is accurately determined in consideration of the self-discharge capacity during standing. A CPU switches to a low power consumption mode and stops operation of peripheral devices for capacity monitoring when the battery is left without any charge and discharge commands for a predetermined time or more. Is returned to the normal operation mode, and only a part of the peripheral devices necessary for the calculation of the self-discharge amount is started to calculate the self-discharge amount, and the battery capacity is obtained and stored. Peripheral devices for monitoring the capacity include, for example, a battery temperature detecting section, a battery current detecting section, a battery voltage detecting section, a display section of the remaining capacity, and the like. Some of the peripheral devices that are activated when the self-discharge amount is calculated at regular intervals during the idle time include at least a battery temperature detection unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery capacity monitoring method applied to a battery management device used in combination with a chargeable / dischargeable battery.

[0002]

2. Description of the Related Art Nickel-cadmium batteries (Ni-Cd
For rechargeable batteries (rechargeable batteries) such as batteries, it is necessary to select an appropriate charging method that takes into account various conditions depending on conditions such as the battery type, discharge state, charge current value, ambient temperature, and number of times of charge / discharge. There is. It is also necessary to allow the user to know the remaining capacity by monitoring the amount of discharge.

Conventionally, while the charging capacity is stored in memory,
It is known that the discharge capacity is constantly monitored and the remaining capacity is indicated by the difference between the two (charge capacity-discharge capacity). In this case, as the charge capacity, a value obtained by integrating the ampere hour, which is the product of the charge current and the charge time, with respect to time is used. As the discharge capacity, a value obtained by integrating an ampere hour, which is a product of a discharge current and a discharge time, with respect to time is used.

[0004] In the case of using such a device for monitoring the remaining capacity, it is necessary to keep the monitoring device operating even while the battery is left without being discharged. For this reason, it is considered that the consumption capacity of the battery is reduced as much as possible during the leaving. For example, Japanese Patent Publication No. 6-81425 proposes setting a part of an electronic circuit to a “light sleep mode” (light sleep mode) when there is no charge or discharge operation within a predetermined time. . In the proposed method, the microprocessor is set in the low power consumption mode in the "light sleep mode", and the clock pulse frequency of the microprocessor is reduced from that in the normal operation.

[0005]

2. Description of the Related Art The conventional method changes a microprocessor to a low power consumption mode when left for a certain period of time. However, it has been found that the power saving effect is relatively small. That is, in this type of monitoring device, it is necessary to constantly monitor the battery temperature, the charging / discharging current, the voltage, and the like, and the power consumed for these monitoring must be so large that it cannot be ignored compared to the power consumption of the microprocessor. I understand.

When a battery is left for a long period of time, the remaining capacity decreases due to self-discharge. Conventionally, the remaining capacity is simply obtained as the difference between the charge capacity and the discharge capacity without considering the self-discharge, and there is a problem that the remaining capacity cannot be accurately detected and displayed.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and it is possible to sufficiently reduce the power consumption when the battery is left unattended, thereby preventing a decrease in the remaining capacity of the battery. It is an object of the present invention to provide a battery capacity monitoring method capable of accurately calculating the remaining capacity in consideration of the self-discharge capacity of the battery.

[0008]

According to the present invention, an object of the present invention is to provide a battery capacity monitoring method used in a battery management device for calculating a battery capacity by a CPU. Switch to power mode and stop operation of peripheral devices for capacity monitoring,
During this idle time, the CPU is returned to the normal operation mode at regular time intervals, and only a part of peripheral devices necessary for the calculation of the self-discharge amount is started to calculate the self-discharge amount. This is achieved by a battery capacity monitoring method characterized in that:

[0009] Peripheral devices for monitoring the capacity include, for example, a battery temperature detecting section, a battery current detecting section, a battery voltage detecting section, a remaining capacity display section, and the like. Some peripheral devices that are activated when calculating the amount of self-discharge at regular intervals during standing are:
At least a battery temperature detector is included. In this case, the amount of self-discharge is calculated using the capacity reduction rate characteristic with respect to the battery temperature stored in advance.

In calculating the self-discharge amount, the battery voltage detecting section is also started to check that the battery voltage is equal to or higher than a specified voltage. When the voltage falls below the specified voltage, measures are taken to prevent overdischarge of the battery. For example, a charge command is issued, discharging is prohibited, and the operation of the CPU is stopped (power down).

The power supply circuit includes a large-capacity main power supply circuit and a small-capacity sub-power supply circuit having a large energy saving effect.
It is better to use both depending on the mode. That is, a relatively large-capacity Zener diode that can flow a large current is usually used for the main power supply circuit. However, it is extremely inefficient to use this with a small current in the low power consumption mode. A power supply circuit is used.

The CPU can reduce power consumption by setting the frequency of the clock pulse used in the low power consumption mode lower than the frequency of the clock pulse used in the normal operation mode. For this purpose, it is preferable to provide first and second clock generation circuits for outputting these two types of clock pulses, and to select and use them in accordance with one of the modes.

The calculation result of the self-discharge amount and other data (battery temperature, battery voltage, current, etc.) are stored in a non-volatile memory, for example, an EEPROM, and can be read out and displayed on a display device in a timely manner.

[0014]

FIG. 1 is a diagram schematically showing an entire embodiment of the present invention, FIG. 2 is a block diagram mainly showing the functions of a CPU,
3 is a transition diagram of the operation mode, FIG. 4 is a diagram showing an example of the capacity reduction rate characteristic, and FIG. 5 is a flowchart of the operation.

1 and 2, reference numeral 10 denotes a motor, 12
Is a controller, 14 is a battery management device, and 16 is a charger. The battery management device 14 includes a battery 18. The alternating current supplied from the alternating current power supply 20 is rectified by the charger 16 and passes through the diode 22 in a predetermined charging mode.
Charge 8.

The controller 12 supplies a predetermined current and voltage to the motor 10 using the battery 18 as a power source, and
Drive 0. For example, when the motor 10 is a DC motor, the controller 12 may be of a chopper type that controls on / off of the output voltage of the battery 18 at a predetermined duty.

Reference numeral 24 denotes a CPU (microprocessor). Its function will be described later. Reference numeral 26 denotes a power supply circuit (FIG. 2), which has a main power supply circuit 26A and a sub power supply circuit 26B (FIG. 1). The main power supply circuit 26A is a switch (SW)
3, the voltage of the battery 18 (for example, 24 V) is reduced to a predetermined voltage (for example, 5 V). The sub power supply circuit 26B lowers the voltage of the battery 18 to a predetermined voltage via the switch (SW) 24. The CPU 24 operates these power supply circuits 26 (26
A, 26B) is selected and used in accordance with the operation mode, and is driven by the output voltage.

Reference numeral 28 denotes an external communication circuit, 30 denotes a current detection circuit, and 32 denotes a watch dog timer (WDT).
These are driven by the output voltages of the main and sub power supply circuits 24 and 26 supplied through the switch (SW) 1. The external communication circuit 28 operates in the normal operation mode of the CPU 24, and inputs and outputs data to and from the controller 12 and other external devices.

The current detection circuit 30 detects the charge / discharge current of the battery 18, converts the current into a predetermined voltage range for input to the CPU, and outputs it to the CPU 22. The WDT 32 is an intermittent timer for detecting an operation error of the CPU 24.
In the normal operation of No. 4, a reset pulse is output at regular intervals.

Reference numeral 34 denotes an amplifier circuit, 36 denotes an A / D interface, and 38 denotes an EEPROM (Electrically Erasable).
/ Programmable Read Only Memory).

The amplifying circuit 34 forms a battery temperature detecting section together with a temperature sensor such as a thermistor 40 provided on the battery 18. Specifically, the amplifier circuit 34 supplies a current to the thermistor 40 and amplifies a change in the current. The voltage is converted and input to the CPU 24.

The A / D interface 36 detects the positive voltage of the battery 18 and converts it to a voltage,
Send to The EEPROM 38 stores various data used for the calculation by the CPU 24, for example, the type of the battery 18 and its characteristic data, the capacity reduction characteristic shown in FIG. 4, and also stores data during the calculation and the remaining capacity as the calculation result. .

Reference numeral 42 denotes a first clock generation circuit. The clock generation circuit 42 is connected to the main power supply circuit 26 via SW2.
The output of A is used as a power source to generate a high-speed clock pulse during normal operation of the CPU 24. A second clock generation circuit 44 uses the output of the sub power supply circuit 26B as a power supply and generates a low-speed clock pulse in the low power consumption mode of the CPU 24.

Reference numeral 46 denotes an external interrupt interface, which uses the output of the auxiliary power supply circuit 26B as a power supply and waits for an external signal for instructing an interrupt process to be input. For example, C
When the controller 12 outputs a start command while the PU 24 is left unattended, the interface 46 outputs this start command to the C
It is sent to the PU 24 to change the CPU 24 to the normal operation mode.

Next, the function of the CPU 24 will be described. CPU
24 performs an initialization process when a start command is received from the controller 12 or the charger 16 (FIG. 3, step 10).
0). That is, SW3 is turned on to activate the main power supply circuit 26A. Then, SW1 and SW2 are turned on to activate the first clock generator 42 to output a high-speed clock pulse. Thereafter, the CPU 24 operates by the high-speed clock pulse. Although the CPU 24 operates by software, its function is shown as a block in FIG.

First, the CPU 24 performs mode determination in the mode determination section 50 (FIG. 2) (step 102). If charging or discharging is to be performed, a normal operation mode is entered, and peripheral devices are started (step 104). Here, the peripheral device is an external communication circuit 2 activated by turning on SW1.
8, the current detector 30, W.W. P. T. 32, a battery temperature detecting section (34, 40) activated when SW2 is turned on, a battery voltage detecting section 36, an EEPROM 38, a first clock generating circuit 4
2 and so on.

In the charging mode, the CPU 24 calculates the charged amount in the remaining capacity calculating section 52 (FIG. 2). That is, the amount of charge is determined by the product (ampere hour) of the current and the charge time detected by the battery current detector 30. On the other hand, the CPU 24 obtains power from the product of the voltage and the current being charged by the power integration unit 54, and corrects the charge amount according to the magnitude of the power. This correction is performed in consideration of the fact that the charging efficiency changes depending on the magnitude of the charging current and the charging method.
Perform in step 6. The result is stored in the EEPROM 38,
The information is sent to the controller 12 via the communication interface 28 as necessary, and is displayed on the display device 58.

If it is determined in step 102 that discharge is being performed, the CPU 24 calculates the amount of discharge. That is, the amount of discharge (ampere hours) is obtained by integrating time with the discharge current detected by the battery current detection unit 30. The CPU 24 sets this to EEP
The current value of the remaining capacity is obtained by subtracting from the remaining capacity stored in the ROM 38. It is needless to say that the remaining capacity correction unit 56 may add a correction based on a power change to the current value. The remaining capacity after this correction is stored in EEPROM 3
8 is stored. The result is sent to the controller 12 via the communication interface 28 and the display device 5
8 is displayed.

When neither charging nor discharging is performed, that is, when the idle state continues for a predetermined time (for example, 30 minutes) (steps 102 and 106), the CPU 24 determines that the idle state is being performed and enters the low power consumption mode (steps 102 and 106). Step 108). When entering this mode, the peripheral devices are stopped. That is, SW3 is turned off, the main power supply circuit 26A is stopped, and SW3 is turned off.
4 to turn on the sub power supply circuit 26B. Therefore, the CPU 24 is thereafter driven by a low-speed clock pulse output from the second clock generation circuit 44.

In this mode, the external interrupt interface 46 is activated, and both the switches SW1 and SW2 are turned off. Therefore, the external communication circuit 28, the current detection unit 3
0, W. D. T. 32, an amplifier circuit 34 as a battery temperature detector, an interface 3 as a battery voltage detector
6. The EEPROM 38 and the first clock generation circuit 42 stop. For this reason, in this low power consumption mode, the energy consumption of the battery 18 is extremely reduced.

In the low power consumption mode, the external interrupt interface 46 is in operation. For example, when a charge or discharge command is received from the controller 12 (step 110), the process returns to step 102 to enter the normal operation mode and start the peripheral device. (Step 104).

Without an external interrupt (step 11)
0), after a lapse of a predetermined time (for example, 30 minutes) (step 112), the CPU 24 returns to the normal operation mode to calculate the self-discharge amount (step 114). That is, SW
3 is turned on to activate the main power supply circuit 26A, and SW4 is turned off to stop the sub power supply circuit 26B. Further, the switch SW2 is turned on to activate a part of the peripheral device.

The peripheral devices activated at this time are the amplifier circuit 34 of the battery temperature detecting section, the interface 36 of the battery voltage detecting section, the EEPROM 38, and the first clock generating circuit 42. Therefore, thereafter, the CPU 24 operates by the high-speed clock pulse output from the first clock generation circuit 42.

In this state, the CPU 24 calculates the amount of self-discharge (step 116). For this calculation, the characteristic of the decrease rate of the remaining capacity with respect to the battery temperature θ shown in FIG. 4 is used. 4 (A) and 4 (B) show the same contents, but one (A) shows the rate of decrease in the remaining capacity with respect to the temperature using the standing time T as a parameter. (B) shows the remaining capacity reduction rate with respect to the standing time T using the battery temperature θ as a parameter.

In the CPU 24, the battery temperature θ is obtained by the temperature measuring section 60 based on the signal output from the amplifier circuit 34.
The remaining capacity reduction rate is determined from the characteristics of (1). And EEPRO
The remaining capacity is corrected by integrating the rate of decrease with the remaining capacity stored a predetermined time ago in M38. The result is stored in the EEPROM 38, and is stored in the step 1 again.
Return to the low power consumption mode of 08.

When a stop signal is sent from the controller 12 during the operation of the CPU 24 in the normal mode, the CPU 2
In step 4, after storing predetermined data in the EEPROM 38, SW1 and SW2 are turned off to end the operation by the CPU 24, and finally, SW3 is turned off to stop the main power supply circuit 26A. If a stop signal is sent during the low power consumption mode of the CPU 24, the CPU 24 ends the processing of all programs, turns off the SW4, and turns off the sub power supply circuit 2.
Stop 6B. As a result, the CPU 24 ends all operations.

[0037]

As described above, according to the first aspect of the present invention, if the idle state without charge / discharge instruction continues for a predetermined time or more, the CPU
To the low power consumption mode to stop the peripheral devices for capacity monitoring, return the CPU to the normal operation mode at regular intervals during this leaving, and remove only some of the peripheral devices necessary for calculating the amount of self-discharge. Since the battery is activated to calculate the amount of self-discharge, and the remaining capacity is obtained and stored in the memory, the power consumption of the battery when left unattended is reduced, and a decrease in the remaining capacity of the battery can be prevented.

Further, the self-discharge amount is obtained at regular intervals during the standing, and the remaining capacity is corrected, so that an accurate remaining capacity can always be known.

Peripheral devices for monitoring the capacity include, for example, a battery temperature detecting section, a battery voltage detecting section, a battery current detecting section, and a display section. Some of the peripheral devices that are started to calculate the self-discharge amount during standing are, for example, a battery temperature detecting unit (Claim 3). In this case, the capacity reduction rate characteristic with respect to the battery temperature stored in advance is used. Then, the self-discharge amount is calculated using the calculated value (claim 4).

When calculating the amount of self-discharge, the battery voltage is also detected, and if the battery voltage drops below a specified value, a process for preventing overdischarge may be performed. . In this case, protection of the battery is ensured.

The power supply circuit has a large-capacity main power supply circuit for a normal operation mode and a small-capacity sub-power supply circuit for a low-power consumption mode. Attrition is less. That is, an auxiliary power supply circuit having a small capacity and an optimum configuration with low power consumption can be used (claim 6).

In addition, a clock generation circuit for generating a high-speed clock pulse and a clock generation circuit for separately generating a low-speed clock pulse are prepared separately, and these are selected and used in accordance with each mode. It is possible to use a pulse generation circuit that is optimal and efficient in the above (7).

[Brief description of the drawings]

FIG. 1 is a schematic view of a main body according to an embodiment of the present invention.

FIG. 2 is a block diagram mainly showing functions of a CPU;

FIG. 3 is a transition diagram of an operation mode.

FIG. 4 is a characteristic diagram of a capacity reduction rate.

FIG. 5 is an operation flowchart.

[Explanation of symbols]

 Reference Signs List 10 motor 12 controller 14 battery management device 16 charger 18 battery 24 CPU 26 power supply circuit 26A main power supply circuit 26B sub power supply circuit 30 battery current detection unit 34 amplifier as battery current detection unit 36 A / D interface as battery voltage detection unit Reference Signs List 38 EEPROM as memory 40 Temperature sensor (thermistor) 42 First clock generation circuit 44 Second clock generation circuit 46 External interrupt interface 50 Mode discrimination unit 52 Remaining capacity calculation unit 54 Power integration unit 56 Remaining capacity correction unit 58 Display device 60 Temperature Detection unit

Claims (7)

[Claims] 1. A battery capacity monitoring method used in a battery management device for calculating a battery capacity by a CPU, wherein the CPU is switched to a low power consumption mode when the charge and discharge commands are not provided for a predetermined time or more, and the capacity is monitored. The operation of the peripheral devices is stopped, the CPU is returned to the normal operation mode at regular time intervals during the idle time, and only some of the peripheral devices necessary for the calculation of the self-discharge amount are activated to reduce the self-discharge amount. A battery capacity monitoring method, comprising calculating and storing a battery capacity. 2. The battery capacity monitoring method according to claim 1, wherein the peripheral device for monitoring the capacity includes a battery temperature detecting unit, a battery voltage detecting unit and a current detecting unit, and a display unit. 3. The battery capacity monitoring method according to claim 2, wherein some of the peripheral devices activated when calculating the self-discharge amount at regular intervals during the idle time are battery temperature detection units. 4. The battery capacity monitoring method according to claim 3, wherein the capacity reduction rate characteristics with respect to the idle time and the battery temperature are stored in advance, and the self-discharge amount is calculated based on the capacity reduction rate properties. 5. A peripheral device which is activated when calculating a self-discharge amount at regular intervals during a standing time includes a battery temperature detecting unit and a battery voltage detecting unit, and the battery voltage detecting unit detects the battery temperature detecting unit and the battery voltage detecting unit. 3. The battery capacity monitoring method according to claim 2, wherein an overdischarge prevention process is performed when the battery voltage is equal to or lower than a specified value. 6. The power supply circuit includes a large-capacity main power supply circuit used in a normal operation mode of the CPU, and a small-capacity and low-power consumption sub-power supply circuit used in a low-power consumption mode of the CPU. 6. The battery capacity monitoring method according to claim 1, wherein one of the main and sub power supply circuits is selectively operated according to the mode. 7. A first clock generation circuit for outputting a high-speed clock pulse for driving a CPU in a normal operation mode;
7. A second clock generation circuit for outputting a low-speed clock pulse for driving the CPU in a low power consumption mode, wherein one of the clock generation circuits is selectively operated in accordance with each mode. Battery capacity monitoring method.