JPH10171402A - Method for displaying gradation of video signal and display device using the same - Google Patents

Abstract

(57) [Summary] [Problem] In gradation expression by a subfield method,
Image quality deterioration due to pseudo contour noise is reduced. SOLUTION: The level of an input video signal x is converted, a subfield weighted according to a predetermined value is set for each bit of the converted output, and light emission display of each pixel is performed using the subfield to perform a level display. When performing key display,
Two nonlinear conversion functions fA are used for the level conversion.
(X) and fB (x) are set, and the non-linear conversion functions fA (x) and fB (x) are alternately used for each pixel of the video signal x, so that three-dimensional space-time adjacent pixels can be used. Level conversion is performed using different nonlinear conversion functions. As the nonlinear conversion functions fA (x) and fB (x), their average is equal to the level of the video signal x,
And when one of them changes according to the level of the video signal x,
The other is at the maximum or minimum level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gradation expression method for displaying a video signal such as a television signal or a high-definition signal, and divides one field of the video signal into several subfields. The present invention relates to a gray scale display method for expressing the gray scale of light emission luminance by controlling the presence or absence of light emission of the subfield, and a display device using the gray scale display method.

[0002]

2. Description of the Related Art As a conventional method for realizing gradation display in a display device in which it is difficult to perform gradation display between light emission and non-light emission with a single element, a method of controlling a light emission time width of a light emitting element is known. .

For example, Japanese Patent Application Laid-Open No. 4-195188 discloses a gradation driving method for a flat display device using a subfield method as shown in FIG. In this method, one field is divided into five subfields SF each including a pair of an address period and a light emission period.
By dividing the data into 0 to SF4 and controlling the presence or absence of light emission in each subfield, a gray scale of luminance is expressed. The ratio of the light emission amount in the light emission period of each subfield is made to match the weight of the binary code, and each bit of the input digital data is made to correspond according to the light emission weight.

[0004]

In such a conventional gradation display method using the subfield method, an object having a gradual gradation change is displayed, and when the object moves, an outline is formed at a gradation change point. The disturbance referred to as "pseudo-contour noise" is perceived. Such pseudo-contour noise causes the noise on the contour to be superimposed on the face, skin, etc. intensely when the person moves, and significantly degrades the image quality.

As a method of improving the quality of a moving image by reducing such pseudo contour noise, for example, Japanese Patent Laid-Open No.
Japanese Patent Application Laid-Open No. 211294 discloses a method of dividing and displaying several bits out of the most significant bit or the most significant bit in the gradation expression method using the subfield method.

However, even if this method is used, the reduction of the pseudo contour noise is not sufficient, and there is a problem that the effect of improvement is small, especially for fast moving images.

There is also a problem that the number of subfields for forming one field increases with the division of the upper bits, and the timing margin for driving the display element decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gradation display method and a display device using the same, which can solve such a problem and greatly reduce image quality deterioration due to pseudo contour noise in a moving image. It is in.

[0009]

In order to achieve the above object, according to the present invention, two level conversion characteristics represented by nonlinear functions fA (x) and fB (x) are alternately provided for each pixel of an input video signal. In this method, the luminance level of the input video signal is converted by applying the same non-linear function between adjacent pixels in space and time.

Further, assuming that the amplitude of the video signal is 0 to 1, these two nonlinear functions fA (x) and fB (x)
Is configured so as to satisfy the following three conditions shown in Expressions 1, 2, and 3.

[0011]

(Equation 1)

[0012]

(Equation 2)

[0013]

(Equation 3)

Further, the nonlinear functions fA (x), fB
By the level conversion according to (x), the least significant bit that always becomes 0 is not displayed as a subfield, and the display is performed with the number of subfields smaller than the number of quantization bits of the input video signal by one.

Alternatively, the nonlinear function fA (x), f
By the level conversion using B (x), the least significant bit which always becomes 0 is not displayed as a subfield, and the subfield of upper several bits including at least the most significant bit is divided into two and displayed.

Also, in order to prevent flicker occurring at the edge of the input video signal by the level conversion according to the present invention, an edge detection signal indicating the edge is generated from the input video signal, and the conversion characteristic of the level conversion process is generated based on this signal. Is changed.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a video signal gradation display method and a display device using the same according to the present invention, wherein 1R, 1G, and 1B are A / D (analog / digital) conversion circuits; Is a level conversion circuit, 3 is a subfield conversion circuit, 4 is a subfield sequential conversion circuit, 4A is a frame memory, 5 is a drive circuit, 6 is a matrix display panel, and 7 is a control circuit.

In FIG. 1, A / D conversion circuits 1R, 1R
G and 1B are the respective color signals R and R of the input analog video signal, respectively.
G and B are converted into digital signals. Level conversion circuit 2
Are two different nonlinear functions f to the digital color signals R, G, B (hereinafter, these are collectively referred to as video signals).
A (x) and fB (x) are alternately applied to each pixel, and the luminance level of the input video signal is converted so that the same non-linear function is not applied between adjacent pixels in three dimensions in space and time. The subfield conversion circuit 3 converts the binary signal level-converted by the level conversion circuit 2 (hereinafter referred to as a conversion output) into subfield data indicating the presence or absence of light emission in a subfield. The subfield sequential conversion circuit 4 converts the subfield data expressed in pixel units from the subfield conversion circuit 3 into a field sequential format in subfield units. The subfield sequential conversion circuit 4 is provided with a frame memory 4A for realizing frame sequential in bit units. The driving circuit 5
A pulse necessary for driving the display device is additionally inserted into the video signal converted into the field sequential format in the unit of subfield, and converted into a voltage (or current) for driving the display device. The matrix display panel 6 is driven by the drive circuit 5, and performs display by gradation expression by a subfield method. The control circuit 7 generates a control signal necessary for each block from the dot clock CK, the horizontal synchronization signal H, the vertical synchronization signal V, etc., which are timing information of the input video signal.

Next, the operation of this embodiment will be described.

The R, G, and B input video signals are A / D
It is converted into a digital video signal by the conversion circuits 1R, 1G, 1B. This digital video signal is based on general binary notation, and includes bits d0, d1,.
When quantizing (digitizing) into an 8-bit signal of 6, d7, it is assumed that b0 represents the least significant bit and b7 represents the most significant bit.

This digital video signal is subjected to level conversion by the level conversion circuit 2 with characteristics based on nonlinear functions fA (x) and fB (x). Conversion characteristics based on these nonlinear functions (hereinafter, nonlinear conversion characteristics fA (x), fB
(X) will be described in detail later. By alternately switching these two types of non-linear conversion characteristics for each pixel, horizontally and vertically adjacent pixels are level-converted by different non-linear conversion characteristics. Even for pixels having the same coordinates, control is performed such that these two nonlinear conversion characteristics are alternately switched for each field.

The digital video signal thus level-converted is converted by the sub-field conversion circuit 3 into sub-field data indicating the presence or absence of light emission in the sub-field.

The sub-field data is supplied to the sub-field sequential conversion circuit 4, and is written in a frame memory 4A provided in the sub-field sequential conversion circuit 4 in pixel units. Reading from the frame memory 4A is performed in a frame-sequential manner on a subfield basis. That is, assuming that SF0, SF1, SF2,..., SF8 in one field in this order from the first subfield, the bit S0 indicating the presence or absence of light emission in the subfield SF0 is read for one field, The bit S1 indicating whether or not light emission is present in the subfield SF1 is read out, and the bits S2, S3,..., S8 are read out in this order to form a subfield. The matrix display panel 6 is driven by performing signal conversion and pulse insertion necessary for the operation.

FIG. 3 is a diagram showing a specific example of the nonlinear conversion characteristic used in the level conversion circuit 2 in FIG.

FIG. 3A shows a non-linear conversion characteristic fA (x).
FIG. 3B shows the non-linear conversion characteristics fB (x), which are alternately used for each pixel. Here, the luminance level (input level) of the input video signal
x is normalized to satisfy 0 ≦ x ≦ 1, where 0 corresponds to the black luminance level and 1 corresponds to the 100% white luminance level. Further, 0 ≦ fA (x) and fB (x) x ≦ 1. In this specific example, fA (x) = 0 (0 ≦ x <0.5) = 2x−1 (0.5 ≦ x ≦ 1) fB (x) = 2x (0 ≦ x <0.5) = 1 (0.5 ≦ x ≦ 1) When the input video signal is quantized with 8 bits, 0 to 1 may be made to correspond to gradations 0 to 255.

In the nonlinear conversion characteristic fA (x), when the input level x is less than 0.5, the level of the converted output is 0, and when the input level x exceeds 0.5, the linear output As a result, the conversion output level increases. FIG.
In the non-linear conversion characteristic fB (x) shown in (b), when the input level x is 0.5 or more, the conversion output level is 1.0.
The conversion output level increases at input levels x up to 0.5.

These nonlinear conversion characteristics fA (x), fB
The feature of (x) is that converted outputs obtained by level-converting the same input level x by these are fA (x) and fB, respectively.
(X), these converted outputs fA
That is, the average level of (x) and fB (x) becomes equal to the input level x as shown in the following Expression 1. That is, the average level of the converted output by the nonlinear function corresponds to the input level on a one-to-one basis.

[0028]

(Equation 1)

As shown in the following equations (2) and (3), one of the nonlinear conversion characteristics fA (x) and fB (x) is 0.
When a halftone value other than 1 and 1 is taken, the other has a characteristic of taking either 0 or 1 value.

[0030]

(Equation 2)

[0031]

(Equation 3)

FIG. 4 shows a specific example of a method of switching the level conversion characteristics by the non-linear functions fA (x) and fB for each pixel in the level conversion circuit 2 in FIG. 1, and FIG. FIG. 4B shows the case of an odd field, and FIG. 5B shows the case of an even field. A indicates a pixel whose level is converted by a nonlinear function fA (x), and B indicates a pixel whose level is converted by a nonlinear function fB (x). , Respectively.

As shown in FIGS. 4A and 4B, the non-linear characteristics fA (x), fB
The checker flag pattern in which (x) alternates is a switching pattern that is further inverted for each field. As a result, when a still image is displayed, pixels at the same coordinates in the display screen are alternately switched between the non-linear characteristic fA (x) and the non-linear characteristic fB (x) for each field, and the level is converted. For this reason, the non-linear characteristics fA (x), fB
The average value of (x) is perceived. Further, even in the case of a moving image, in a flat portion, the gradation between adjacent pixels is almost equal,
Since the non-linear characteristics fA (x) and fB (x) are switched by a high frequency which is hardly perceived on the spatial frequency, the average level of the peripheral pixels is recognized as a whole.

As described above, by switching the non-linear functions fA (x) and fB (x) with a high-frequency pattern that is hardly perceived on the spatial frequency and the time frequency, the influence of flicker and the like is reduced, and the desired level conversion is performed. Can be realized.

The principle of the pseudo contour noise reduction method by level conversion in this embodiment will be briefly described below.

The image perceived when the line of sight follows a moving object tends to be perceived as a subfield that emits light with a delay in time shifted to a position in the opposite direction to the motion, even for the same pixel. is there. This phenomenon in which the subfields appear to be shifted causes a phenomenon in which the data of the adjacent pixels are mixed in units of bits (subfields), and the disturbance of the gradation occurs as a pseudo contour.

For example, when the level conversion in the pixel unit is not applied as in this embodiment, for example, the gradation 1
Assuming that an image whose luminance gradually changes from 27 to gradation 128 moves, a subfield having the largest light emission amount corresponding to the most significant bit representing gradation 128 is adjacent to gradation 1.
A phenomenon occurs in which the light emission amount is mixed into the 27th pixel or the light emission amount is lost from the pixel of interest, and disturbance occurs at a change in gradation. In an image in which the gradation changes more gradually, the gradation change point exists in a continuous linear area on the display screen, such as a contour line of a map. Are superimposed.

In a system for performing level conversion on a pixel basis as shown in this embodiment, for example, a gray scale 127
Assuming that an image in which the luminance gradually changes to the gradation 128 is displayed, when the nonlinear functions fA (x) and fB (x) for the two level conversions are as shown in FIG.
The signal of the tone 127 or the tone 128 (around x = 0.5) is converted into a signal near the black level by the nonlinear function fA (x), and is converted by the nonlinear function fB (x).
It is converted to a signal near the level of 100% white. Therefore,
According to the conversion pattern shown in FIG. 4, "black" and "white" pixels appear alternately, and this pattern is displayed as a signal that is inverted every field. Such a signal having both a high horizontal and vertical frequency and a high time frequency that reverses for each field is difficult to be directly recognized due to human visual characteristics,
Usually, it is recognized as a gray flat signal which is a peripheral pixel and a temporal average value.

As described above, since the average value of the conversion output by the two nonlinear functions has a linear characteristic corresponding to the input on a one-to-one basis, the perceived gradation is 127 or 12
8 corresponding to 8 input gradations. Furthermore, such a level conversion process disperses the gradation change points without concentrating on a specific area. Therefore, even if the gradation is disturbed due to the motion, the noise does not become a continuous contour noise. In addition, it is possible to reduce image quality deterioration due to pseudo contour noise.

It should be noted that the method of displaying a gradation of a video signal according to the present invention is not limited to gradations 127 and 128, and is not limited to gradations of 0% and black.
If the signal is at a level other than 100% white, display is performed using two pairs of signals having a luminance higher than the input level and a signal having a lower luminance, so that continuous gradation change points can be dispersed. Thus, it is possible to reduce image quality deterioration due to pseudo contour noise.

In particular, in this embodiment, as shown in FIG. 3, one of the characteristics of the non-linear functions fA (x) and fB (x) is used when performing level conversion to an intermediate gradation. Has selected the characteristic that the other performs a level conversion to either white or black, so that the signals of all gradations are signals of intermediate gradation and white, or signals of intermediate gradation and black. A gradation is expressed by a combination of signals. When performing gradation display by the subfield method, when black, no subfield emits light,
When white (100%), all subfields emit light. As described above, since the pixel converted to the white or black level has a uniform subfield structure, even if the line of sight follows the movement and the subfield is mixed with the adjacent pixels, the pixel is specified by light emission / non-light emission. Only the subfields of are not affected. Thereby, the disturbance of the gradation can be minimized, and the image quality deterioration due to the pseudo contour noise can be reduced.

Next, a specific example of the main part in FIG. 1 will be described.

FIG. 5 is a circuit diagram showing a part of a specific example of the control circuit 7 in FIG.
This is an XOR (exclusive OR) circuit.

In the figure, an EXOR circuit 701 is supplied with a field inversion signal FI which is inverted for each field and a line odd / even signal VL indicating an odd / even line number of an input video signal. The EXOR circuit 702 has an EXOR circuit
An output signal of the circuit 701 and a dot odd / even signal HD indicating an odd / even horizontal dot number of an input video signal are supplied.
It outputs a level conversion characteristic selection signal ABSL.

Here, the field inversion signal FI is "H" (high level) for each field of the input video signal,
The line odd / even signal VL is a signal that repeats “L” (low level) and level inversion. The line odd / even signal VL is a signal that becomes “H” when the line number of the input video signal is odd and “L” when the line number is even. It consists of the least significant bit of the count value of the line counter provided in the control circuit 7 (FIG. 1). Also,
The dot odd / even signal HD is a signal that becomes “H” when the horizontal dot number of the input video signal is odd and “L” when the horizontal dot number is even, and is the lowest count value of the horizontal dot counter provided in the control circuit 7. It consists of bits. Further, the level conversion characteristic selection signal ABSL is one of the control signals output from the control circuit 7 of FIG. 1 to the level conversion circuit 2 (FIG. 1), and has a function fA as a nonlinear function for level conversion.
The logic signal is "L" when (x) is used and "H" when the function fB (x) is used.

Then, by the operation of the EXOR circuits 701 and 702, the inversion is performed for each field, and for each line,
Further, a level conversion characteristic selection signal ABSL as shown in FIGS. 4A and 4B that is inverted for each dot is generated and supplied to the level conversion circuit 2 in FIG.

FIG. 6 is a circuit diagram showing one specific example of the level conversion circuit 2 in FIG. 1. Reference numerals 21 and 22 denote non-linear conversion circuits, and reference numeral 23 denotes a switching circuit. Digitized color signals from the A / D conversion circuits 1R, 1G or 1B are supplied to the level conversion circuit 2 and are converted respectively. As described above, these color signals are collectively referred to as video. Signal x.

In the figure, a nonlinear conversion circuit 21 converts a video signal x into a nonlinear function fA (x) as shown in FIG.
, And the nonlinear conversion circuit 22 converts the same video signal x into a nonlinear function fB (x) as shown in FIG.
To convert the level. The switching circuit 23 receives the level conversion characteristic selection signal A formed by the control circuit 7 as described with reference to FIG.
With the BSL, the video signal whose level has been converted by the nonlinear conversion circuit 21 (ie, the converted output fA (x)) and the video signal whose level has been converted by the nonlinear conversion circuit 22 (ie, the converted output f
B (x)) for each pixel (dot) and outputs the converted output K.

FIG. 7 is a circuit diagram showing a specific example of the nonlinear conversion circuit 21 in FIG.
213 is an AND gate.

In the figure, the video signal x is generally digitized in about 8 bits, but in order to simplify the explanation, it is digitized in 4 bits here.
The respective bits are d0, d1, d2, and d3, d0 is the least significant bit (MLB), and d3 is the most significant bit (MSB). The level (that is, gradation) of the video signal x is represented by (d0, d1, d2, d3).

The lower three bits d0, d1, of the video signal x
d2 are AND gates 211, 212, and 213, respectively.
And the most significant bit d3 is supplied to these AND gates 2
11, 212, and 213. And A
Output bit a from ND gates 211, 212, 213
A 3-bit converted output fA (x) consisting of 0, a1, and a2 is obtained. Here, this conversion output f
The level (gradation) of A (x) is represented by (a0, a1, a2). When the most significant bit d3 of the video signal x is "1", a0 = d0, a1 = d1, a2 = d2, and the level of the converted output fA (x) is (d0, d1, d2). However, when the most significant bit d3 of the video signal x is “0”, a0 = a1 = a3 = “0”, and the level of the converted output fA (x) is (0, 0,
0,), that is, the value is 0.

In the following description, numerical values enclosed in parentheses such as () and “” represent binary numbers, and other numerical values represent decimal numbers.

Therefore, (d0, d1, d2, d3) =
(1,1,1,0) is 7, (d0, d1, d2, d3)
= (0,0,0,1) is 8, the converted output fA
The level of (x), that is, the gradation (a0, a1, a2) is
When the gradation of the video signal x is 7 or less, it is fixed to 0, and when the gradation of the video signal x is 8 or more, it becomes equal to this video signal x (d0, d1, d2), and the video signal x is 8
, The conversion output fA (x) changes from gradation 0 to gradation 7.

Here, the video signal x has 16 gradations of 0 to 15.
3A, which is standardized by the numerical value 15 and compared with FIG. 3A, the gray scale of the converted output fA (x) is 0 to 0.
Although it is halved to 47, a conversion characteristic similar to the conversion characteristic shown in FIG. This is further illustrated in FIG.
In order to match the conversion characteristics shown in (a), a 3-bit signal (a0, a0) from the AND gates 211, 212, 213 is used.
a1, a2) may be doubled, and therefore the conversion output fA
(X) may be set to (0, a0, a1, a2) by adding the least significant bit of “0”. According to this, the gradation of the conversion output fA (x) is 0 to 0.93 with respect to the gradation 0.53 to 1.0 of the video signal x, and FIG.
The conversion characteristics shown in FIG.

FIG. 8 is a circuit diagram showing a specific example of the nonlinear conversion circuit 22 in FIG.
223 is an OR circuit.

In the figure, the same video signal x as the video signal x input to the non-linear conversion circuit 21 shown in FIG. 7 is supplied, and the least significant bit d0 of this video signal x is ORed by the OR circuit 2.
21, the second least significant bit d1 is the OR circuit 222
The third least significant bit d3 is supplied to the OR circuit 223, and the most significant bit d3 is supplied to these OR circuits 221 and 221.
222, 223. And the OR circuit 223
, The most significant bit b2 of the conversion output fB (x), the second highest bit b1 of the conversion output fB (x) from the OR circuit 222, and the three bits of the conversion output fB (x) from the OR circuit 221.
The second most significant bit b0 is obtained.

In this configuration, assuming that the most significant bit d3 of the video signal x is "0", the conversion output fB
The respective bits b0, b1, b2 of (x) are b0 = d0, b1 = d1, b2 = d2, and the level (d0, d1, d2, d) of the video signal x
3) is smaller than 1/2 of the maximum level, the level (b0, b1, b2) of the converted output fB (x) is the level (d0, d1, d1) represented by the lower three bits of the video signal x.
d2). Also, the most significant bit d3 of the video signal x
= "1", b0 = b1 = b2 = "1", so that the level of the conversion output fB (x) is (1,
1, 1).

According to the level conversion, the video signal x has 16 gradations from gradation 0 to 15, and the converted output fB (x)
Is within the range of gradations 0 to 7 of the video signal x.
Of the video signal x, and
In the range of 5, the signal is fixed at gradation 7.

The level conversion characteristic is similar to the non-linear conversion characteristic shown in FIG. 3B, but is further similar to the nonlinear conversion circuit 21 described with reference to FIG.
As B (x), a “0” bit is added as the least significant bit to bits b0, b1, and b2 obtained from the OR circuits 221, 222, and 223 to obtain a signal of (0, b0, b1, b2). FIG.
The conversion characteristics shown in (b) can be provided.

In the description of FIGS. 7 and 8, the number of bits of the video signal x is set to 4 for simplicity, but it is generally digitized to 8 bits.
In this case, as the nonlinear conversion circuit 21 shown in FIG. 7, seven ANs to which the lower 7 bits of the video signal x are supplied are provided.
D gates may be used to supply the most significant bits to these AND gates. Similarly, the nonlinear conversion circuit 22 shown in FIG. , And the most significant bit may be supplied to these OR circuits.

In this case, the conversion outputs fA (x), fB
(X) is a 7-bit signal that is one bit smaller than the input video signal x, but in order to obtain an 8-bit signal equal to the video signal x, as described above, these converted outputs fA ( It is sufficient to add a "0" bit as the least significant bit to x) and fB (x). Thereby, the characteristics of the converted output fA (x) become as shown in FIG. 3A, and the characteristics of the converted output fB (x) also become as shown in FIG. 3B. By performing such a level conversion process, since the least significant bits of the converted outputs fA (x) and fB (x) are always “0” bits, they are not emitted at the time of display. It is not necessary to set a subfield for. That is, the gradation can be expressed by the number of subfields one less than the number of quantization bits of the video signal x.

FIG. 9 is a diagram showing a specific example of an arrangement configuration of subfields for gradation display in this embodiment when an input video signal is digitalized by 8 bits.

In the figure, for the 8-bit video signal x, the least significant bit of the conversion output K (FIG. 6) of the level conversion circuit 2 is a "0" bit. No field is provided, and there are seven subfields in one field. These seven subfields are SF0, SF1, SF2, SF3, and
SF4, SF5, and SF6.

Light emission weights (percentage of light emission time) are assigned to these subfields.
In order from the first subfield SF0, 4 (= 2 ² ), 16 (= 2 ⁴ ), 64 (= 2 ⁶ ), 1
28 (= 2 ⁷ ), 32 (= 2 ⁵ ), 8 (= 2 ³ ), 2 (=
As 2 ¹ ), each subfield corresponds to each bit of the conversion output. That is, now, the bits of the conversion output K are k6, k5, k4, k3, k
2, k1 and k0 (except because the least significant bit is “0”).
3 corresponds to the most significant bit k6 of the converted output K, the subfield SF2 of the emission weight 64 corresponds to the second upper bit k5 of the converted output K, and so on. The bits correspond to the higher-order bits k4, k3, k2, k1, and k0 in the order of SF5, SF0, and SF6. Thus, for example, for a pixel displaying a gray scale 100, since it is 100 = ²⁶ + 2 ⁵ + 2 ^2,
Light is emitted in subfields SF0, SF2, and SF4.

The subfield corresponding to the least significant bit of the light emission weight 1 is not assigned because this bit is “0” and the light is always not emitted. For this reason,
The emission time allocated to each subfield in one field can be increased, the degree of freedom in setting the pulse width for driving the display element is increased, the display element drive waveform is optimized, and the emission of the display element is controlled stably. Can be. In addition, the time occupancy of the light emitting period can be increased by expanding the time width of the subfield, whereby the luminance and the contrast can be improved.

In this specific example, as shown in FIG. 9, the subfield of the most significant bit having the largest light emission weight is substantially centered, and the subfields are arranged such that the light emission weight becomes smaller as the distance from the center increases. As a result, fluctuations in the center of gravity of light emission can be reduced, and pseudo contour noise can be reduced.

The arrangement of the subfields for reducing the variation of the center of gravity of the light emission is not limited to that shown in FIG. 9. The subfields corresponding to the upper bits having a large light emission weight are arranged at the center and are arranged from the center. The arrangement may be such that subfields having smaller emission weights are arranged in order as the distance increases. Specifically, 1: 2: 4: 8: 16
The subfield arrangement having a binary emission weight of
4: 16: 8: 2 or 1: 2: 16: 8: 4, 1: 8: 1
As in the case of 6: 4: 2 (or an arrangement in which these are reversed), the arrangement is such that the light emission weight monotonously decreases around the subfield, thereby suppressing the change in the center of gravity of the emission. The pseudo contour noise can be effectively reduced in combination with the level conversion processing using the nonlinear function described above.

FIG. 10 is a diagram showing another specific example of the arrangement of subfields for gradation display in this embodiment when the input video signal x is digitized by 8 bits. In this specific example, the subfield corresponding to the most significant bit is divided into two using the subfield corresponding to the least significant bit reduced by the above-described nonlinear level conversion processing.

In this example, in this specific example, one field is equal to the number of bits of the video signal x and is composed of eight subfields, and the subfields SF0, SF1, SF2 and SF3 are sequentially arranged from the head. , SF4
SF5, SF6, SF7 are arranged, and subfield S
The emission weight of F0 is 64, the emission weight of subfield SF1 is 4, the emission weight of subfield SF2 is 16, the emission weight of subfield SF3 is 64, and so on.
F4, SF5, SF6 and SF7 are 32, 8, 2, 6 respectively
It has an emission weight of 4.

The two subfields SF0 and SF7 arranged at the beginning and end are the most significant bit k6 of the converted output K.
And the emission weight 128 is originally assigned to the most significant bit k6. In this specific example, this is divided into two equal parts and these subfields S6 are divided into two.
Light emission weights are assigned to F0 and SF7 in units of 64. The emission weights of the subfields other than these have powers of 2 and correspond to bits other than the most significant bit k6. That is, the subfield SF3 to which the light emission weight 64 is assigned corresponds to the bit k5 of the conversion output K. Hereinafter, the subfield SF4, SF2, SF5
SF1 and SF6 are bits k4, k3, k2, k1, respectively.
It corresponds to k0. In this case, as in the specific example shown in FIG. 9, the subfield corresponding to the least significant bit of the light emission weight 1 is not allocated. Instead, one subfield is added to the most significant bit k6 to correspond to the two subfields SF0 and SF7, and the most significant bit k6 is maintained while keeping the number of subfields equal to the number of quantization bits of the video signal. Is divided into two. Conventionally, it is known that in a gradation display method using subfields, pseudo contour noise can be reduced by dividing upper bits, but in this specific example, upper bits are divided without adding a new subfield. In addition to the effect of pseudo contour reduction by the non-linear level conversion processing, a display device with higher image quality can be realized.

In a specific example of the arrangement of the subfields, as shown in FIG.
Are arranged at the beginning and end of the field as SF0 and SF7, and the remaining subfields are arranged substantially at the center between these subfields of the field. Further, the subfields corresponding to the bits other than the most significant bit k6, which are divided and arranged, have the subfield SF3 having the large light emission weight 64 arranged substantially at the center of the field, and the other subfields have the light emission weight reduced as the distance from the subfield SF3 decreases. The field is located. With such an arrangement of the sub-fields, it is possible to reduce the variation of the center of gravity of the light emission, thereby reducing the pseudo contour noise.

The arrangement of subfields having a small variation in the center of gravity of light emission is not limited to that shown in FIG. 10, but the divided upper bit subfields can be arranged before and after in one field. It is sufficient to arrange the subfields of the remaining lower bits as shown in FIG. 9 such that the light emission weight decreases as the distance from the center increases.

FIG. 11 is a diagram showing still another specific example of the arrangement of subfields for gradation display in this embodiment when the input video signal x is digitized by 8 bits. In this specific example, the number of subfields constituting one field is increased by one from the number of bits of the input video signal x, and the subfield corresponding to the upper two bits is divided into two and displayed. .

In the figure, while the input video signal x is an 8-bit digital signal, there are nine subfields SF0 to SF8 for each bit of the converted output K, and light is emitted from the head of the field to the subfield SF0. The weight 32 is a light emission weight 64 in the subfield SF1,
The subfield SF2 has a light emission weight of 4, the subfield SF3 has a light emission weight of 16, and the subfield S3 has the following order.
Light emission weights 32, 8, 2, 64, and 32 are assigned to F4, SF5, SF6, SF7, and SF8, respectively. The two subfields SF1 and SF7 have the conversion output K
, And the subfield of the emission weight 128 originally corresponds to the most significant bit k6. In this specific example, the emission weight 128 is divided into two equal parts. Thus, two subfields SF1 and SF7 each having an emission weight of 64 correspond to each other.

The two subfields SF0 and SF8 arranged at the beginning and end correspond to the second most significant bit k5 of the converted output K. The bit k5 originally has the light emission weight. Although 64 subfields should correspond to each other, in this specific example, the emission weight 64 is divided into two equal parts, and the two subfields SF having the emission weight 32 are divided.
0 and SF8.

Bits other than the above-mentioned upper bits correspond to one subfield having a power-of-two light emission weight. That is, the subfield SF4 of the light emission weight 32 corresponds to the bit k4 of the converted output K. Hereinafter, the subfields SF3, SF5, SF2, S
F6 corresponds to bits k4, k3, k2, k1, and k0, respectively.

Note that, similarly to the above specific example, in this specific example, too, the least significant bit (“0” bit) of the converted output K is not assigned a subfield (a light emission weight of 1 is allocated). Instead, the most significant bit k
6 and the second most significant bit k5, the corresponding subfields are added one by one, so that the number of subfields is increased by one more than the quantization bit number of the video signal x, and the two higher The subfield of bits can be split into two. Conventionally, it is known that the pseudo contour noise can be reduced by dividing the subfield corresponding to the upper bits into two, but in this specific example, the addition of one new subfield makes the upper two bits smaller. The corresponding sub-fields can be split, FIG.
It is possible to realize a display device with higher image quality than the arrangement configuration of the subfields shown in FIG.

In this specific example, as shown in FIG. 11, subfields corresponding to two bits including the divided most significant bit are arranged at the beginning and end of the field.
The remaining subfields having emission powers of powers of 2 are arranged substantially at the center. Further, the lower subfield excluding the upper 2 bits which are divided and arranged has a subfield SF4 having a light emission weight as large as 32 as in the configuration of FIG.
And the light emission weight decreases as the distance from the center increases. With such a subfield arrangement, it is possible to reduce the variation in the center of gravity of light emission, and thereby reduce pseudo contour noise.

As described above, in the arrangement of the subfields shown in FIGS. 9 to 11, the input video signal x is an 8-bit digital signal, but the present invention is not limited to this.
May be reduced by 1 bit to 7 bits. In this case, the subfields each having the minimum light emission weight may be deleted, the time of the deleted subfield may be reduced, and the time distribution of each subfield in one field may be increased.

Similarly, when the number of quantization bits of the video signal x is further reduced to 6 bits or 5 bits, the corresponding lower sub-field is deleted and 1
The time distribution in the field can be changed. Conversely, the number of quantization bits of the video signal x is increased by 1 bit to 9 bits.
It may be a bit. In this case, a subfield having an emission ratio of 1/2 of the current minimum emission weight may be added to correspond to the newly added least significant bit.
In this case, the position at which this subfield is inserted is, as described above, similar to the subfield having a light-emitting ratio of a power of 2, with the center of the subfield having a large emission weight as the distance from the center increases. The subfield arrangement may be such that the weight is small.

The sub-field arrangement is shown in FIG. 9, FIG. 10 and FIG.
However, the present invention is not limited to these, and may have completely different configurations. The same number of gradations can be expressed by reducing the number of data bits of the video signal x by one by the level conversion process. However, the number of subfields can be reduced by one. As a result, the occupation time width of the subfield in one field can be widened, and high luminance and high contrast due to a long light emission period can be realized. Alternatively, by providing a margin for the drive pulse width in the address period, the display element can be driven stably, and a high-quality display device can be realized.

Further, by reducing the number of data bits of the video signal x by one by the level conversion processing,
The storage capacity of the frame memory 4A provided in the subfield sequential conversion circuit 4 (FIG. 1) can be reduced,
At the same time, effects such as downsizing and cost reduction by reducing the circuit scale can be obtained.

Further, as shown in FIGS. 10 and 11, even when the display is performed by dividing the subfield corresponding to the upper bits, all the subfields correspond to the data bits of the video signal. In this case, the subfield conversion circuit 3 (FIG. 1) does not convert the data into the subfield data corresponding to the light emission of the subfield on a one-to-one basis. Data reading from 4A may be controlled in accordance with the configuration of the subfield. Specifically, in the arrangement of the subfields shown in FIG. 10, the subfield corresponding to the most significant bit k6 of the conversion output K is divided into two subfields SF0 and SF7. In order to realize such an arrangement configuration of the subfields, it is sufficient to read the data of the most significant bit k6 twice, when outputting the subfield SF0 and when outputting the subfield SF7. With such a configuration, the storage capacity of the frame memory 4A provided inside the subfield sequential conversion circuit 4 can be reduced, and there is an economic effect by reducing the circuit scale.

The circuit configuration of the level conversion circuit 2 shown in FIG. 6 shows processing of one of three color signals of R, G, and B. However, the level conversion circuit 2 shown in FIG. Includes three color signal processing circuits of R, G, and B.

In a color display device,
When there is a difference between the light emission characteristics of R, G, and B, the nonlinear characteristics of the R, G, and B color signals in the level conversion circuit 2 (FIG. 1) may be made different.

In the embodiment shown in FIG. 1, the input color signals R, G, B are analog video signals, which are converted into digital signals by A / D conversion circuits 1R, 1G, 1B. However, the input video signal may be a digital signal. In this case, these A /
The D conversion circuits 1R, 1G, and 1B become unnecessary, and an external digital video signal is directly supplied to the level conversion circuit 2.

In this embodiment, in order to reduce the circuit scale, the level conversion circuit 2 is constituted by a combinational logic circuit, as shown in FIGS. 6 to 8, but a ROM (read only memory). And a level conversion may be performed. Also in this case, in FIG. 6, two nonlinear functions f
The output of the look-up table corresponding to A (x) and fB (x) may be switched by the level conversion characteristic selection signal ABSL and output. Alternatively, a look-up table having twice the capacity may be configured by a ROM, and the level conversion characteristic selection signal ABSL may be input to the highest address to switch the page.

Further, a process for reversely correcting the gamma characteristic of the input video signal may be included in the lookup table of the level conversion. FIG. 12 shows characteristics when the gamma inverse correction and the level conversion by the nonlinear function are performed simultaneously.

FIG. 12 shows a specific example of the non-linear conversion characteristic when the gamma characteristic of γ = 2.0 and the non-linear level conversion for reducing the pseudo contour are simultaneously realized. The conversion characteristic f′A (x) is shown, and FIG. 2B shows the nonlinear conversion characteristic f′B (x).

Similarly to the non-linear conversion characteristic shown in FIG. 3, also in this specific example, the input and output signal levels are expressed as being normalized from 0 to 1.0, and the luminance level 0 (black level) is 0. , The level of 100% white corresponds to 1.0. In order to realize the gamma characteristic, the nonlinear conversion characteristic fA shown in FIG.
(X) and fB (x), the nonlinear conversion characteristic f′A
(X) and f′B (x) are expressed by the following equations (4) and (5), respectively.
The characteristic shown by.

[0091]

(Equation 4)

[0092]

(Equation 5)

The average value of the non-linear conversion characteristics f′A (x) and f′B (x) for the same input video signal x is given by
It is confirmed that the gamma inverse correction can be correctly realized.

[0094]

(Equation 6)

As described above, the nonlinear conversion characteristic f ′
By setting A (x) and f'B (x), inverse gamma correction and non-linear level conversion for pseudo contour reduction can be realized at the same time, and there is an economic effect by reducing the circuit scale.

In the specific example described above, the nonlinear conversion characteristic is switched by the level conversion characteristic selection signal ABSL, and the arrangement of the subfields is such that the same pattern is used in each field. This may be configured such that the temporal arrangement in one field is inverted for each field. Specifically, the subfield arrangement shown in FIG. 13 is obtained by inverting the emission weight arrangement of the subfields in terms of weighting time with respect to the arrangement of the subfields shown in FIG. 9. 9, and in the odd field,
The subfield arrangement shown in FIG. As shown in the specific examples so far, level conversion in pixel units is similarly performed.

By the above-described processing, a change in the center of light emission caused by light emission / non-light emission in the subfield occurs almost every target in each field, and the remaining pseudo contour pattern can be flickered. As a result, the remaining pseudo contour noise can be made less noticeable.

The nonlinear conversion characteristics fA (x), fB
Although (x) has been described with reference to FIG. 3 or FIG. 12, the present invention is not limited to this, and any type may be used as long as it satisfies the conditions of Equations 1, 2, and 3. However, the effect of reducing the pseudo contour can be obtained. For example,
The characteristics shown in FIGS. 14A and 14B may be used. FIG.
Also in the non-linear conversion characteristics fA (x) and fB (x) shown in FIG. 4, the average is a characteristic that increases linearly from 0 to 1 as shown by the broken line, and satisfies the condition of Equation 1. Further, since the nonlinear conversion characteristic fB (x) always takes 1.0 or 0, there is no x satisfying 0 <fB (x) <1 in Equation 2, and the nonlinear conversion characteristic fA (x) is Equation 1 Is determined only by the condition By setting such characteristics, it is possible to disperse the transition points of the level of the smooth intermediate gradation, and it is possible to reduce the image quality deterioration due to the pseudo contour.

In this embodiment, level conversion is performed by alternately switching two non-linear conversion characteristics between adjacent pixels in space and time, and the switching pattern of these characteristics is shown in FIGS. 4 (a) and 4 (b). As shown in (1), since all of the horizontal, vertical, and time are high frequency components, it has characteristics that are hard to detect due to human visual characteristics. However, when displaying an edge portion of a video signal or a fine pattern, this high-frequency component interferes with a high-frequency component of the video signal, and is detected as dot rotation or granular noise at the edge portion.

FIG. 15 is a circuit diagram showing another specific example of the level conversion circuit 2 in FIG. 1 capable of reducing the disturbance due to the switching pattern.
Is a conversion circuit, 25 is an edge detection circuit, and 26 is a switching circuit. The parts corresponding to those in FIG.

In the figure, a conversion circuit 24 outputs a video signal x
Is converted by the conversion characteristic fC (x), and the edge detection circuit 25
Detects that the image content of the video signal x is an edge portion or a fine pattern, and outputs an edge detection signal EDGD. Further, the switching circuit 26 supplies the edge detection signal EDG
By D, the output signal (conversion output) K ′ of the switching circuit 23 and the output signal of the conversion circuit 24 are switched and output as the conversion output K of the level conversion circuit 2.

Here, the configurations and operations of the nonlinear conversion circuits 21 and 22 and the switching circuit 23 are the same as those of the specific example shown in FIG. Therefore, the output signal K 'of the switching circuit 23 is level-converted and output according to the characteristic selected by the control signal ABSL which is inverted for each pixel, line and field, similarly to the conversion output K in FIG. .

In this specific example, in addition to this, when the edge detection circuit 25 detects that the image content of the video signal x includes a fine pattern or edge, and when the fine pattern or edge is detected, By controlling the switching circuit 26, the output signal of the conversion circuit 24 is output as the conversion output K of the level conversion circuit 2. Therefore, in an image region where the gradation of the video signal x changes smoothly without detecting an edge, the switching circuit 26 selects and outputs the output signal K ′ of the switching circuit 23. Such an operation is exactly the same as the specific example shown in FIG. 6, and as described above, the pseudo contour noise is reduced by the level conversion.

The conversion characteristic fC (x) of the conversion circuit 24 is to take the average value of the non-linear conversion characteristics fA (x) and fB (x). Usually, fC (x) = x. .
Therefore, when an edge or a fine pattern is detected, the video signal x passes through the conversion circuit 24 and is output from the switching circuit 26 as it is without undergoing nonlinear conversion processing by the edge detection signal EDGD.

By the above processing, in a flat portion where pseudo contour noise is liable to occur, image quality deterioration due to pseudo contour can be reduced by non-linear level conversion, and dot rotation in the edge portion and generation of granular noise in a fine pattern can be prevented. be able to.

The non-linear conversion characteristic fA (x) shown in FIG.
Nonlinear conversion circuit 21 having a nonlinear conversion characteristic fB
The nonlinear conversion circuit 22 having (x) can be realized by the configurations shown in FIGS. 7 and 8, respectively.

FIG. 16 is a circuit diagram showing a specific example of the conversion circuit 24 in FIG.

In the figure, the video signal x shown in FIG. 6 and the like is supplied to the conversion circuit 24. As described above, the video signal x is generally quantized with about 8 bits. However, for simplicity, here, the video signal x is quantized with 4 bits, and each bit is most often quantized. From the lower bits, d0, d1, d2, and d3 are set in order, and the level of the video signal x, that is, the gradation is expressed as (d0, d1, d2, d3).

The conversion output from the conversion circuit 24 having the conversion characteristic fC (x) is defined as fC (x).
Each bit of (x) is c0, c1,
Assuming that c2, these bits c0, c1, and c2 are set to have a relationship of c0 = d1, c1 = d2, and c2 = d3 with respect to the bits of the video signal x, whereby the converted output fC (x) is ,
The level of the video signal x excluding the least significant bit d0 is (c
(0, c1, c2).

As described above, in this specific example, the conversion output f
C (x) is a 3-bit signal excluding the least significant bit d0 of the video signal x.
As described with reference to FIGS. 7 and 8, the converted outputs fA (x) and fB (x) from the signals 1 and 22 are signals having a bit number reduced by one bit from the quantization bit number of the video signal x. , And the converted output fC (x) is also adapted to this.

By this processing, the number of gradations of the conversion output fC (x) from the conversion circuit 24 is insufficient by one bit of the least significant bit as compared with the flat portion having a smooth gradation. Is selected at the edge portion of the video signal x, so that there is no need to increase the number of subfields because the image quality does not deteriorate significantly.

In the specific example shown in FIG. 16, the number of bits of the video signal x is four for the sake of simplicity.
Even when the circuit is realized by general 8 bits, the configuration may be such that the lower bits are simply ignored and output.

Further, as shown in FIG. 12, when the non-linear level conversion and the gamma inverse correction for reducing the pseudo contour are realized by one look-up table, the conversion characteristic fC (x) of the edge portion is obtained. As shown in the following Expression 7, the characteristic may be such that only the gamma inverse correction is realized.

[0114]

(Equation 7)

The edge detection circuit 25 shown in FIG. 15 detects edge information using a horizontal high-pass filter and a vertical high-pass filter, and generates an edge detection signal EDGD based on the output of these high-pass filters. What is necessary is just to be a structure. FIG. 17 is a circuit diagram showing a specific example of the edge detection circuit 25.
Is a line delay circuit, 252 and 253 are pixel delay circuits, 2
54 is a line delay circuit, 255 and 256 are arithmetic circuits, 2
57 and 258 are discrimination circuits, and 259 is an OR circuit.

In the figure, line delay circuits 251, 251
Numerals 54 denote one horizontal scanning period of the input video signal x (hereinafter, referred to as a horizontal scanning period).
1H).
Each of the pixel delay circuits 252 and 253 has a delay time of one dot of the input video signal x. Arithmetic circuits 255, 25
6 are -0.5, -0.5, +
Weighting of 1.0 is performed, and these are added. The determination circuits 257 and 258 each determine whether the amplitude of the input signal exceeds a predetermined value.

The input video signal x is supplied to the line delay circuit 2
The delayed video signal x1 is obtained by being delayed at 51, and the delayed video signal x1 is further delayed by the pixel delay circuit 252 to obtain the delayed video signal x '. The delayed video signal x ′ is further delayed by the pixel delay circuit 253 to obtain a video signal x2.
Delayed by the line delay circuit 254, a delayed video signal x3 is obtained. Here, the delayed video signal x ′ output from the pixel delay circuit 252 is delayed by 1H from the input video signal x, and the delayed video signal x3 output from the line delay circuit 254 is the input video signal x 2H. In addition, the delayed video signal x1 output from the line delay circuit 251 is one more than the delayed video signal x ′.
The delayed video signal x2 output from the pixel delay circuit 253 is one dot ahead of the delayed video signal x ′.
This is delayed by a dot.

In the arithmetic circuit 255, the line delay circuit 25
The delayed video signal x1 from the pixel delay circuit 252 is weighted by -0.5.
1.0 is weighted, and the delayed video signal x2 from the pixel delay circuit 253 is weighted by -0.5, and the three weighted delayed video signals are added. The output video signal x4 of the arithmetic circuit 255 is supplied to the discriminating circuit 257 and is converted into a binary logic signal.

In the arithmetic circuit 256, the input video signal x is weighted by -0.5, and the pixel delay circuit 252
Is weighted by +1.0, and the delayed video signal x3 from the line delay circuit 254 is −
The weighting of 0.5 is performed, and these three delayed video signals thus weighted are added. The output video signal 5 from the arithmetic circuit 256 is supplied to a discriminating circuit 258 and converted into a binary logic signal.

The outputs of the discriminating circuits 258 and 257 are supplied to an OR circuit 259 to perform a logical OR process, and the result of the logical OR process is output as an edge discriminating signal EDGD.

Here, a horizontal transversal filter is constituted by the pixel delay circuits 252 and 253 and the arithmetic circuit 255, and the tap coefficients -0.5, +1.0,-.
With 0.5, a high-pass filter having a peak at half the dot frequency of the pixel is formed. That is, the maximum output is obtained when a pattern with the highest horizontal frequency, in which black and white are inverted for each dot, is input, and the output for DC is 0.

The output video signal x 'of the pixel delay circuit 252 is a signal obtained by delaying the input video signal x by 1H, and the output video signal x3 of the line delay circuit 254 is
52 is a signal obtained by further delaying the output video signal x ′ by 1H. As a result, the input image signal x, the output image signal x 'of the pixel delay circuit 252, and the output image signal x3 of the line delay circuit 254 are subjected to coefficient addition by the arithmetic circuit 256, thereby forming a vertical transversal filter. . This vertical transversal filter has a maximum output when a pattern having the highest vertical frequency in which black and white is inverted for each line is input, and the output for DC is zero.

The output signals x4 and x5 of the horizontal and vertical high-pass filters are discriminated by the decision circuits 257 and 258, respectively.
When the amplitude is equal to or larger than the predetermined amplitude, the logic signal corresponding to the determination result output from the determination circuits 257 and 258 becomes “H”. The logical signals from the horizontal and vertical discriminating circuits 257 and 258 are ORed by the OR circuit 2.
An OR operation is performed at 59, whereby an edge detection signal EDGD indicating that there is an edge in at least one of the horizontal and vertical directions of the image is obtained. In this case, the horizontal and vertical edges are determined independently, and the result of the determination is subjected to the logical OR processing, so that the horizontal and vertical edges or the diagonal edges can be detected.

In the edge detection method shown in FIG. 17, the detection signal E is determined by the delay time of the transversal filter.
Although DGD is delayed by 1H, the pixel delay circuit 252 outputs 1H.
Since the delayed video signal x 'is obtained, the timing of the video signal x' coincides with the detection signal EDGD, and the video signal x 'is converted into the nonlinear conversion circuits 21 and 22 and the conversion circuit in FIG. By using 24 input video signals, there is no timing deviation from the detection signal EDGD.

With the above-described configuration, it is possible to reduce the false contour disturbance without the dot rotation at the edge portion of the video signal or the image quality deterioration due to the granular noise in the fine pattern.

In the embodiment described above, each subfield has a time occupancy rate proportional to the light emission weight. However, in actuality, the subfield has a light emission period and a light emission period as shown in FIG. When the address period is formed and the time occupancy of the address period is high, the light emission intervals of the subfields may be substantially equal. Alternatively, gradation display is performed by dividing one field into a plurality of subfields, even if the number of pulses having a constant light emission amount and the light emitting time are varied to control the light emission amount during the light emission period. If it is a display element,
With the gradation display method of the present invention, it is possible to reduce image quality deterioration due to pseudo contour noise. Further, as shown in FIG. 2, in the driving method in which the address period and the light emission period are not separated and the light emission is sequentially performed by the subfield while performing the address processing, the subfield configuration is temporally shifted according to the vertical scanning. However, even such a display method is in accordance with the gist of the present invention.

[0127]

As described above, according to the present invention,
Even in a fast-moving image, image quality degradation due to pseudo contour noise can be reduced, and a high-quality display device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a method for displaying a gray scale of a video signal and a display device using the same according to the present invention.

FIG. 2 is an explanatory diagram of a conventional gradation expression method using a subfield method.

FIG. 3 is a characteristic diagram showing a specific example of a non-linear conversion characteristic of the level conversion circuit in FIG.

FIG. 4 is a diagram showing a switching state of a non-linear conversion characteristic in the level conversion circuit in FIG. 1;

FIG. 5 is a circuit configuration diagram showing a part of a specific example of the control circuit in FIG. 1;

FIG. 6 is a circuit configuration diagram showing a specific example of a level conversion circuit in FIG. 1;

7 is a circuit configuration diagram showing a specific example of a nonlinear conversion circuit having a nonlinear conversion characteristic fA (x) in FIG. 6;

8 is a circuit diagram showing a specific example of a nonlinear conversion circuit having a nonlinear conversion characteristic fB (x) in FIG. 6;

FIG. 9 is a diagram showing a specific example of an arrangement configuration of subfields in the embodiment shown in FIG. 1;

FIG. 10 is a diagram showing another specific example of a subfield arrangement configuration in the embodiment shown in FIG. 1;

11 is a diagram showing still another specific example of the arrangement configuration of the subfields in the embodiment shown in FIG.

FIG. 12 is a characteristic diagram showing another specific example of the nonlinear conversion characteristic of the level conversion circuit in FIG. 1;

FIG. 13 is a diagram showing still another specific example of the arrangement configuration of the subfields in the embodiment shown in FIG. 1;

14 is a characteristic diagram showing still another specific example of the nonlinear conversion characteristic of the level conversion circuit in FIG.

FIG. 15 is a circuit configuration diagram showing another specific example of the level conversion circuit in FIG. 1;

16 is a circuit configuration diagram showing a specific example of a conversion circuit of the conversion characteristic fC (x) in FIG.

FIG. 17 is a circuit configuration diagram showing a specific example of an edge detection circuit in FIG.

[Explanation of symbols]

 1R, 1G, 1B A / D conversion circuit 2 Level conversion circuit 3 Subfield conversion circuit 4 Subfield sequential conversion circuit 4A Frame memory 5 Drive circuit 6 Matrix display panel 7 Control circuit 21, 22 Nonlinear conversion circuit 23 Switching circuit 24 Conversion circuit Reference Signs List 25 edge detection circuit 26 switching circuit 211 AND gate circuit 221 OR gate circuit 251 line delay circuit 252, 253 pixel delay circuit 254 line delay circuit 255, 256 arithmetic circuit 257, 258 determination circuit 259 OR gate circuit 701, 702 EXOR circuit

Continuation of front page (72) Inventor Hiroshi Otaka 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo Inside the Home Appliances and Information Media Business Division, Hitachi, Ltd.

Claims (14)

[Claims] 1. A gradation display of a video signal in which one field period of a video signal is divided into a plurality of subfields, and the presence or absence of light emission at a light emission amount determined in each subfield is controlled to perform gradation expression. In the method, two types of different conversion characteristics fA (x) and fB (x) are alternately used for each pixel of the video signal, and the conversion characteristics different between adjacent pixels in three dimensions in space and time are used. Converting the luminance level x of the video signal and performing display in accordance with the level-converted luminance level of the video signal. 2. The conversion characteristic fA (x), fB (x) whose average value monotonically increases with respect to the luminance level x of the video signal.
And, for the same luminance level x, the conversion characteristic f
When one of A (x) and fB (x) converts the luminance level x of the video signal to an intermediate gradation, the other converts the level to either 0% black or 100% white. A gradation display method for a video signal, characterized in that: 3. The method according to claim 1, wherein the number of gradations of the video signal after the level conversion is about の of the number of gradations of the video signal before the level conversion. A gradation display method for video signals. 4. The display device according to claim 3, wherein when performing display in accordance with the luminance level of said video signal whose level has been converted, the number of subfields constituting one frame is equal to the quantum of said video signal before said level conversion. A gradation display method for a video signal, wherein the gradation display method is one less than the number of digitized bits. 5. The display according to claim 3, wherein when performing display in accordance with the luminance level of the video signal whose level has been converted, at least two subfields having the same light emission amount are provided, and
A gradation display method for a video signal, wherein the number of subfields constituting one frame is equal to the number of quantization bits of the video signal. 6. A display device according to claim 3, wherein when performing display in accordance with the brightness level of said level-converted video signal, n subfield groups consisting of two or more subfields having the same light emission amount are provided. Where n is an integer of 1 or more), and one frame is constituted by the number of subfields (n-1) more than the number of quantization bits of the video signal. Display method. 7. A gradation display of a video signal in which one field period of a video signal is divided into a plurality of subfields, and the presence or absence of light emission at a light emission amount determined in each subfield is controlled to perform gradation expression. In the method, two different conversion characteristics fA (x), fB (x)
Are alternately used for each pixel of the video signal, and by using the conversion characteristics different between adjacent pixels in three-dimensional space-time, by converting the luminance level x of the video signal,
A first level-converted video signal is generated, and the luminance level x of the video signal is converted with a conversion characteristic fC (x) different from any of the conversion characteristics fA (x) and fB (x). Generating a second level-converted video signal, detecting the presence or absence of an edge from the video signal, and selecting one of the first and second level-converted video signals according to the presence or absence of the edge; And performing display in accordance with the selected luminance level of the level-converted video signal. 8. A gradation display of a video signal in which one field period of a video signal is divided into a plurality of subfields, and the presence or absence of light emission at a light emission amount determined in each subfield is controlled to perform gradation expression. In the device, two different conversion characteristics fA (x) and fB (x)
A first means for converting the luminance level x of the video signal by alternately using for each pixel of the video signal and using the conversion characteristic different between adjacent pixels in three dimensions in space and time. And a second means for performing display in accordance with the luminance level of the video signal whose level has been converted by the first means. 9. The conversion characteristic fA (x) and fB (x) according to claim 8, wherein an average value of the conversion characteristics fA (x) and fB (x) monotonically increases with respect to the luminance level x of the video signal.
And, for the same luminance level x, the conversion characteristic f
When one of A (x) and fB (x) converts the luminance level x of the video signal to an intermediate gradation, the other converts the level to either 0% black or 100% white. A video signal display device, characterized in that: 10. The gray scale number of the video signal after level conversion by the first means is about の of the gray scale number of the video signal before level conversion.
A video signal display device, characterized in that: 11. The display device according to claim 10, wherein when displaying by the second means in accordance with the luminance level of the level-converted video signal, the number of sub-fields forming one frame is reduced before the level conversion. A video signal display device, wherein the number of quantization bits of the video signal is one less. 12. The display device according to claim 10, wherein, when the second means performs display in accordance with the luminance level of the level-converted video signal, at least two sub-fields having the same light emission amount as the light emission amount are the largest. A video signal display device, wherein the number of subfields constituting one frame is equal to the number of quantization bits of the video signal before level conversion. 13. A subfield comprising two or more subfields having an equal light emission amount when displaying according to the luminance level of the level-converted video signal by the second means. The video signal includes n groups (where n is an integer of 1 or more), and the number of quantization bits (n−
1) A video signal display device, wherein one frame is composed of a larger number of subfields. 14. A video signal display device which divides one field period of a video signal into a plurality of subfields and controls the presence or absence of light emission at a light emission amount defined in each subfield to perform gradation expression. , Two different conversion characteristics fA (x), fB (x)
A first means for converting the luminance level x of the video signal by alternately using for each pixel of the video signal and using the conversion characteristic different between adjacent pixels in three dimensions in space and time. Second means for performing display in accordance with the luminance level of the video signal whose level has been converted by the first means, and the conversion characteristic fA
(X), conversion characteristic fC different from fB (x)
(x) a second means for converting the luminance level of the video signal, detecting the presence or absence of an edge from the video signal, and performing level conversion by the first and second means in accordance with the presence or absence of the edge A video signal display device, comprising: third means for selecting one of the video signals; and fourth means for performing display in accordance with the luminance level of the video signal selected by the third means. .