JPH10177366A - Drive controller for plasma display panel display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive controller capable of effectively executing the improvement of contrast and the reduction of power consumption. SOLUTION: One field is divided into plural sub-fields to execute the half tone display of a picture signal and each sub-field is constituted of a reset period, an address period and a holding discharge period. A field picture bit information judging circuit 21 judges the existence of picture bit information in one field within a picture area. A sub-field picture bit information judging circuit 23 judges the existence of picture bit information in one sub-field within the picture area. A reset period drive pulse batch stop circuit 22 stops a drive pulse in the reset period as to a field or a sub-field judged that there is no picture bit information in one field or one sub-field.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive control device for a plasma display panel display device for displaying an image on the plasma display panel display device, and more particularly, to a drive control device for the plasma display panel display device.
The present invention relates to a drive control device for a plasma display panel display device that performs an auxiliary discharge (an auxiliary discharge that is not directly related to a display discharge) in addition to performing a display discharge (a display writing discharge and a sustain discharge).

[0002]

2. Description of the Related Art A plasma display panel has a different panel structure due to a difference between two types of driving systems, a direct current (DC) system and an alternating current (AC) system. Generally, in the DC method, the electrodes are exposed above the discharge space,
The AC method is characterized in that the electrodes are covered with a dielectric layer. In the AC method, a discharge cell itself has a memory function by the action of a dielectric. For this, various documents (for example, Nikkei Electronics 10-23, 1995)
(No. 647) Special Issue “Wall-mounted TVs Will Become Popular in 2000” and the like, and detailed description is omitted here.

FIG. 29 is a plan view schematically showing a three-electrode type surface discharge type plasma display panel among general AC type plasma display panels. In FIG. 29, the plasma display panel 1 has A1
To address electrodes 2, X electrodes 3, Y electrodes 4, Y1 to Yn 4, discharge cell portions 5, and barriers 6. Here, for simplicity, the number of X electrodes 3 is set to 1 with respect to the number n of Y electrodes 4, but depending on the driving conditions of the X electrodes 3, the number of X electrodes 3 may be changed with respect to the number n of Y electrodes 4.
May be plural. Also, one discharge cell section 5 is shown with diagonal lines.

FIG. 30 is a partial perspective view showing an example of a cross section of the plasma display panel 1 shown in FIG. In FIG. 30, the discharge cell section 5 includes a front glass substrate 7, X
Electrode 3, Y electrode 4, dielectric layer 8, MgO (magnesium oxide) protective layer 9, barrier 6, R (red) phosphor 10 (or G (green) phosphor 11, B (blue) phosphor 12), This is a discharge space surrounded by the address electrodes 2 and the back glass substrate 13. A gas mixture of He (helium), Ne (neon), Xe (xenon) or the like is sealed in the discharge space to cause a discharge between the address electrode 2, the X electrode 3, and the Y electrode 4, and the discharge is generated. Phosphors 10 to 12
Is excited to obtain emission of R, G, B three primary colors.

FIG. 31 is a diagram showing an example of a driving waveform for explaining a display operation by the plasma display panel display device provided with the plasma display panel 1 shown in FIG. FIG. 31 shows driving waveforms supplied to the address electrodes 2 of A1 to Am, the X electrodes 3 of X, and the Y electrodes 4 of Y1 to Yn. As shown in FIG. 31, one subfield includes three types of periods: a reset period, an address period, and a sustain discharge period. It should be noted that the subfield forms a part of the field, and will be described later in detail.

First, the discharging operation in the reset period will be described in order. In the reset period in this example, three-stage discharge of all-screen batch erasing, all-screen batch writing, and all-screen batch erasure is performed in order. The discharge in this reset period is called a reset discharge, and is an auxiliary discharge that is not directly related to the display discharge. As described above, the main reason that the reset period is constituted by the three-stage operation is as follows.
This is for stabilizing the display write discharge in the address period next to the reset period, and for suppressing the power consumption of the driver IC and performing the display write discharge at a high speed at a low address voltage.

In the above-described all-screen batch erasure, the display state during the sustain discharge period in the previous subfield, that is, the influence of the wall charge due to the ratio of the discharge cell portion 5 discharging to the entire screen, is prevented. Therefore, the X electrode 3
An erase pulse having a voltage Ve for erasing only the remaining wall charges is applied, and erasure discharge is performed on all the discharge cell units 5. The erase pulse has the purpose of erasing only the residual wall charge, and therefore, for example, a pulse having a higher voltage and a smaller width than the erase pulse shown in FIG. 31 has the same effect.

Next, in the above-described all-screen batch writing,
A write pulse having a voltage Vw at which the discharge starts only at that voltage is applied to all the Y electrodes Y1 to Yn, and the writing is forcibly performed between the X electrodes 3 and the Y electrodes 4 of all the discharge cell units 5. Perform discharge. At this time, the address electrode 2 is connected to the X electrode 3
Since the potential is equal to (0 V), the ions are divided into two by the address electrode 2 and the X electrode 3, and the ions accumulate on the surface of each electrode. On the other hand, the total number of electrons, the number of ions on the address electrode 2 and the number of ions on the X electrode 3, is accumulated on the surface of the Y electrode 4.

In the above-described all-screen batch erasing, an erasing pulse is again applied to the X electrode 3, and all erasing discharges for erasing unnecessary wall charges for the display writing discharge in the address period next to the reset period are performed. Discharge cell part 5
Do for Even after the erasing discharge, the state where ions remain on the phosphor surface on the address electrode 2 and the same number of electrons as the ions on the address electrode 2 remain on the Y electrode 4 is maintained.

Next, a display operation in an address period for performing a display write discharge will be described. First, the address electrode 2 sequentially outputs image bit information for n rows corresponding to the number of display lines as serial data one row at a time from the Y1 row. At this time, in each of the address electrodes A1 to Am,
An address pulse is selectively applied only to the discharge cell unit 5 to be displayed. On the other hand, during the address period, a sustain voltage hold pulse that is fixed at a voltage of Vs of the same potential as the sustain pulse (sustain pulse) applied in the sustain discharge period following the address period is applied to the X electrode 3. In addition,
The voltage value of the sustain pulse is set to a voltage value at which discharge does not start with the total voltage of the wall charges remaining after the reset period and the voltage Vs.

The Y electrode 4 is fixed at a voltage of Va, which is the same potential as the address pulse, during most of the address period. Y1 to electrode Yn
, A scan pulse for applying a voltage of 0 V in the same phase as the address pulse is applied in order one row at a time. Thus, only when the address pulse is applied to the address electrode 2 and the scan pulse is applied to the Y electrode 4, the total voltage of the address pulse and the sustain pulse is reduced by the remaining wall charge after the reset period. Since it is superimposed and becomes equal to or higher than the discharge starting voltage, a display writing discharge occurs, and image bit information is written. Further, at this time, wall charges remain in the discharge cell portion 5 as in the above-described all-screen batch writing in the reset period.

In the sustain discharge period, the Y electrode 4 and the X electrode
Sustain pulses for maintaining discharge are applied to the electrodes 3 alternately. At this time, although the address electrode 2 is fixed to 0 V, the amount of wall charges remaining in the discharge cell unit 5 in which the image bit information is written during the address period is:
Since the amount of unnecessary wall charges is larger than the amount of wall charges remaining after the reset period, re-discharge (sustain discharge) is performed only with the sustain pulse. Therefore, in the sustain discharge period, the discharge continues only as many times as the number of times the sustain pulse is applied, only in the discharge cell unit 5 in which the image bit information is written in the address period. As described above, in the AC type plasma display panel, the panel can have a memory function by remaining wall charges in the cell itself.

FIG. 32 is a diagram showing an example of an operation in the case of performing halftone display by subfield division by the driving method shown in FIG. The vertical axes Y1 to Yn in FIG. 32 indicate the number of display lines, and the horizontal axis indicates a time axis. In FIG. 32, in order to obtain 256 gradations (8 bits), one field (16.6 ms) is divided into eight subfields (SF1 to SF8) having different relative ratios of luminance, and the LSB (LSB) of the image bit information is divided. The subfields are configured in order from the least significant bit) to the MSB (most significant bit). As described above, one field is divided into M subfields, and a gray scale of 2M is applied to the plasma display panel 1 by utilizing a visual integration effect by weighting bits based on image bit information. Image representation.

Each subfield is composed of a reset period, an address period, and a sustain discharge period, as described above. The reason why the length of the sustain discharge period differs for each subfield is that the number of sustain pulses (sustain pulses) corresponding to bit weighting is applied. The number of sustain pulses actually applied is 1, 2, 2,
4,..., 128, and the pulse number N times larger (N is a positive integer) is applied in order to increase the emission luminance.

FIGS. 33 and 34 are diagrams systematically showing a driving method by a driving control device of a conventional plasma display panel display device. FIG. 33 shows that, when performing the halftone display by the sub-field division shown in FIG. 32 with the conventional driving method shown in FIG. 31, all the image bits in one field in all the effective image areas displayed by the plasma display panel display device. The state of supply of pulses to be supplied to each of the electrodes 2 to 4 when there is no information is simply shown. FIG. 34 shows an example in which there is no image bit information of a specific subfield in one field.

In FIGS. 33 and 34, RST is a reset period, ADR is an address period, and SUS is a sustain discharge period. In the address electrodes 2 indicated by A1 to Am, the presence / absence of an address pulse is indicated by “present” and “absent”, and the X electrode 3 indicated by X and the Y electrode indicated by Y1 to Yn
In the electrode 4, the presence of drive pulses (erase pulse, write pulse, sustain voltage hold pulse, scan pulse, sustain pulse) is indicated by “○”.

As shown in FIG. 33, when there is no image bit information in one field, no address pulse to be supplied to the address electrode 2 in the address period is applied. Therefore, even if the sustain voltage hold pulse or the scan pulse is supplied to the X electrode 3 or the Y electrode 4, the display write discharge does not occur. Also,
Since no display write discharge occurs, no sustain discharge (re-discharge) occurs even if a sustain pulse is supplied to the X electrode 3 or the Y electrode 4 during the sustain discharge period.

As shown in FIG. 34, for example, when no image bit information exists in only the subfield SF8, no address pulse to be supplied to the address electrode 2 in the address period is applied in the subfield SF8. Therefore, even if the sustain voltage hold pulse or the scan pulse is supplied to the X electrode 3 or the Y electrode 4, the display write discharge does not occur. Further, since no display write discharge occurs, no sustain discharge (re-discharge) occurs even if a sustain pulse is supplied to the X electrode 3 or the Y electrode 4 during the sustain discharge period.

[0019]

As can be seen from FIGS. 33 and 34, when driving the three-electrode type surface discharge type plasma display panel 1 in the AC type plasma display panel, the discharge cell unit 5 is used. In addition to the display writing discharge and the sustaining discharge, the full-screen writing discharge and the full-screen erasing discharge are always performed during the reset period of each sub-field, so that there is a problem that the contrast is significantly reduced. To solve this problem, the contrast is improved by, for example, reducing the number of full-screen writing discharges or full-screen erasing discharges during the reset period, and the apparent contrast ratio is increased by increasing the white peak luminance. Is not a fundamental solution.

Further, when the screen is dark as a whole, or when a scene change occurs, or when only a synchronization signal is input and the image signal is absent, the floating of black is particularly noticeable. There is also a problem that it will. In addition, this problem is not limited to the above-described AC type panel, and is not limited to a plasma display panel which performs an auxiliary discharge which is not directly related to a display discharge in addition to a display writing discharge and a sustain discharge in the same discharge cell portion. Exactly the same exists in all cases.

On the other hand, in a plasma display panel of the DC type, a plasma display panel having an auxiliary cell for performing an auxiliary discharge which is not directly related to the display discharge, in addition to a display cell for performing a display write discharge and a sustain discharge. Then, the black level can be made completely black by forming the auxiliary cells in a black matrix. Thus, improving the contrast, especially the black level,
This is an essential issue for a plasma display panel without an auxiliary cell.

Further, in the conventional drive control device,
Even when the input image signal is no signal or when there is no input image bit information of a specific subfield, in the address period and the sustain discharge period of each subfield,
Since a drive pulse such as a scan pulse or a sustain pulse is always applied every time, there is a problem that wasteful power consumption that does not contribute to display discharge consumed in the drive circuit unit occurs. As the number of display pixels increases to increase the definition and size of the panel, wasteful power consumption that does not contribute to display discharge consumed by the drive circuit unit increases significantly.

The present invention has been made in view of such a problem, and in addition to performing display discharge (display writing discharge and sustain discharge), auxiliary discharge (auxiliary discharge not directly related to display discharge) is also performed. It is an object of the present invention to provide a plasma display panel drive control device capable of lowering a black level, improving contrast, and efficiently reducing power consumption.

[0024]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention divides one field into a plurality of subfields and performs halftone display of an image signal. Comprises a reset period, an address period, and a sustain discharge period. In the address period and the sustain discharge period, a display discharge relating to a halftone display of the image signal is performed, and in the reset period or the address period, the half tone is displayed. In a drive control device for a plasma display panel display device driven to perform an auxiliary discharge not directly related to display, a memory (14) for storing the image signal, and a memory for controlling writing of the image signal to the memory. A write control circuit (15) for reading the image signal from the memory for each subfield Memory readout control circuit (16) for performing control as described above, and a field image information determination circuit for determining whether image bit information exists in one field or whether the image bit information is equal to or less than a preset value (21) A driving method for a plasma display panel display device, comprising: a subfield image bit information determination circuit (23) for determining whether image bit information exists in one subfield. A control device is provided.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a drive control device for a plasma display panel display device according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a first embodiment of a drive control device according to the present invention, and FIG. 2 is a block diagram showing FIGS.
7, a block diagram showing an example of a specific configuration of the field image information determining circuit 21 in FIG. 23, FIG. 3 is a timing chart for explaining the operation of FIG. 2, and FIG. 4 is FIGS. 23 is a block diagram showing an example of a specific configuration of the subfield image bit information determination circuit 23 in FIG. 23, FIG. 5 is a timing chart for explaining the operation of FIG. 4, and FIG. FIGS. 7 and 8 are diagrams showing an example of driving waveforms for explaining a display operation according to the first embodiment, FIGS. 7 and 8 are diagrams systematically showing the first embodiment of the driving control device of the present invention, and FIGS.
And FIG. 10 is a diagram showing an example of an operation in the case of performing halftone display by subfield division in the first embodiment of the drive control device of the present invention, and FIG. 11 is a diagram showing a second embodiment of the drive control device of the present invention. FIG. 12 is a block diagram, FIG. 12 is a diagram showing an example of a drive waveform for explaining a display operation according to a second embodiment of the drive control device of the present invention, and FIGS. 13 and 14 are second embodiment of the drive control device of the present invention. FIG. 15 and FIG. 16 are diagrams showing an example of an operation when halftone display is performed by subfield division in the second embodiment of the drive control device of the present invention.
FIG. 17 is a block diagram showing a third embodiment of the drive control device of the present invention, and FIG. 18 is a diagram showing an example of drive waveforms for explaining a display operation according to the third embodiment of the drive control device of the present invention. 19 and 20 systematically show a third embodiment of the drive control device according to the present invention. FIGS. 21 and 22 show a third embodiment of the drive control device according to the present invention, in which halftone display is performed by subfield division. FIG. 23 is a diagram showing an example of the operation in the case, FIG. 23 is a block diagram showing a fourth embodiment of the drive control device of the present invention, and FIG. 24 is a view for explaining a display operation by the fourth embodiment of the drive control device of the present invention. FIGS. 25 and 26 are diagrams showing an example of a drive waveform, FIGS. 25 and 26 are diagrams systematically showing a fourth embodiment of the drive control device of the present invention, and FIGS. 27 and 28 are fourth embodiments of the drive control device of the present invention. Example of operation when displaying halftone by subfield division It illustrates.

In the conventional drive control device, as described above,
Even if the display writing discharge and the sustain discharge related to the display discharge do not occur, during the reset period of each subfield,
Since the entire screen is always erased or written between the X electrode 3 and the Y electrode 4 every time, a reset discharge (full screen erase or full screen) is performed in the discharge cell unit 5 for each subfield regardless of the presence or absence of display discharge. (Writing). Further, even if the display writing discharge or the sustain discharge related to the display discharge does not occur, the drive pulse related to the display discharge (display writing discharge or the sustain discharge) is always applied during the address period and the sustain discharge period of each subfield. Therefore, wasteful power consumption that does not contribute to the display discharge consumed in the drive circuit unit is generated.

Therefore, the contents of the input image in which the image bit information of the entire one field does not exist at all, that is, when a scene change or only a synchronization signal is input and the image signal is no signal, or when a certain test signal, If there is no bit information of a specific subfield image in one field such as a personal computer input signal or an animation image, this is detected. In this case, the reset pulse is stopped by stopping the drive pulse in the reset period, and the black level is lowered to improve the contrast. Further, power consumption is reduced by stopping driving pulses during the address period and the sustain discharge period.

<First Embodiment> First, a first embodiment of a drive control device for a plasma display panel display device according to the present invention will be described. FIG. 2 shows a plasma display panel used in the plasma display panel display device of the present invention.
9 and FIG.

First, a first embodiment of the drive control device of the present invention will be systematically described with reference to FIGS. 7 and 8, RST is a reset period, ADR is an address period, and SUS is a sustain discharge period. A1 to Am
The presence / absence of an address pulse is indicated by “present” or “absent” in the address electrode 2 indicated by “X”.
And drive pulses (erase pulse, write pulse, sustain voltage hold pulse, scan pulse, sustain pulse) in the Y electrode 4 indicated by Y1 to Yn.
Are represented by “○” and “×”. In addition, FIG.
FIG. 8 shows a case where all the image bit information of one field does not exist at all in the effective image area displayed by the plasma display panel display device. FIG. 8 shows all the effective image areas displayed by the plasma display panel display device. Shows a case where no image bit information exists in only the subfield SF8.

As can be seen from FIG. 7, when a state where no image bit information is present in all one field is detected, a drive pulse (erase pulse, write pulse) to the X electrode 3 and the Y electrode 4 during the reset period. By stopping the supply, all reset discharges to be discharged between the X electrode 3 and the Y electrode 4 are stopped. As can be seen from FIG. 8, when a state where no image bit information exists in the subfield is detected, supply of drive pulses (erase pulse, write pulse) to the X electrode 3 and the Y electrode 4 during the reset period. By stopping, all the reset discharges to be discharged between the X electrode 3 and the Y electrode 4 are stopped.

More specifically, when there is no image bit information in all of one field, in all subfields, as shown in FIG. Is stopped to force no pulse to be applied. When no image bit is present in a certain subfield, in the subfield (here, subfield SF8), as shown in FIG. 6, the image bit is supplied to each of the electrodes 3 and 4 in the reset period and the address period. All necessary pulses are stopped to forcibly apply no pulse. In the other subfields SF1 to SF7 where the image bit information exists, a pulse is supplied to each of the electrodes 3 and 4 during the reset period and the address period as shown in FIG.

According to the driving method shown in FIG. 6, FIG.
Similarly, in order to obtain 256 gradations (8 bits), one field (16.6 ms) is divided into eight subfields (SF1 to SF8) having different relative ratios of luminance, and the LSB (LSB) of the image bit information is divided. When the subfields are sequentially formed from the least significant bit) to the MSB (most significant bit), if there is no image bit information for all of the one field, as shown in FIG. It is a suspension period. In FIG. 9, the reset period of the subfield SF7 is shown as a pause period, but other subfields SF1 to SF
6, the reset period of SF8 is also a pause period.

When no image bit information exists in a certain subfield, as shown in FIG. 10, the reset period in each subfield becomes a pause period in the subfield SF8 in which no image bit information exists, and In other subfields SF1 to SF7, the reset period is the same as the conventional one.

Here, the configuration of the drive control device of the plasma display panel display device for realizing the first embodiment will be described with reference to FIGS. In FIG. 1, an image signal (R, G, B signal) converted into, for example, an 8-bit digital signal is input to a frame memory 14. The frame memory 14 is composed of two field memories, and writing and reading are alternately switched for each field. In the case where the signal form of the image signal has three separate R, G, and B signals, three frame memories 14 are required, and the R, G, and B signals are combined into one.
In the case of a system, the frame memory 14 is constituted by one. The memory write control circuit 15 inputs a write control signal to the frame memory 14 and controls writing of an image signal to the frame memory 14. The memory read control circuit 16 inputs a read control signal to the frame memory 14 and controls reading of a subfield image bit signal from the frame memory 14.

The subfield image bit signal, which is a display data signal read from the frame memory 14, is input to the address electrode driving circuit 18. The drive pulse generation circuit 17 generates various drive pulses to be supplied to the electrodes 2 to 4 in order to drive the plasma display panel 1. That is, the drive pulse generation circuit 17 supplies an address electrode drive pulse to the address electrode drive circuit 18, supplies an X electrode drive pulse to the X electrode drive circuit 19, and supplies a Y electrode drive pulse to the Y electrode drive circuit 20. . The address electrode drive circuit 18, the X electrode drive circuit 19, and the Y electrode drive circuit 20 convert each drive pulse into a high voltage pulse and supply it to each of the electrodes 2 to 4. Thus, the plasma display panel 1 is driven.

On the other hand, the image signal input to the frame memory 14 is also input to the field image information determination circuit 21 and the subfield image bit information determination circuit 23.
The field image information determination circuit 21
It is determined whether or not there is a signal of an image level equal to or higher than a preset gradation (for example, gradation 1) in all the effective image areas of the image signal input to 4 displayed on the plasma display panel 1. The field image information is input to the drive pulse batch stop circuit 22 and the drive pulse generation circuit 17 during the reset period. Further, the subfield image bit information determination circuit 23 determines whether or not there is image bit information for each subfield in all effective image areas of the image signal input to the frame memory 14 displayed on the plasma display panel 1. Is determined, and the subfield image bit information is input to the drive pulse batch stop circuit 22 and the drive pulse generation circuit 17 during the reset period.

Reset pulse driving pulse batch stop circuit 22
While the field image information determination circuit 21 determines that the field image information does not reach the preset gradation, all drive pulses supplied to the electrodes 3 and 4 are forcibly reset during the reset period. Is supplied to the drive pulse generation circuit 17. As a result, the reset discharge in the reset period is stopped for the field in which it is determined that no image bit information exists in one field.

The reset period drive pulse batch stop circuit 22 includes a sub-field image bit information determination circuit 23.
For a subfield determined to have no image bit information, a reset period drive pulse batch stop signal for forcibly stopping all drive pulses supplied to each of the electrodes 3 and 4 during the reset period is provided by a drive pulse generation circuit. 17. As a result, the reset discharge in the reset period is stopped for the subfield for which it is determined that no image bit information exists.

In this embodiment, in the effective image area, 1
The reset discharge in the reset period is stopped for the field in which it is determined that no image bit information exists in the field, but the image bit information in one field is equal to or less than a preset value. It may be configured to stop the reset discharge in the reset period for the field determined to be. That is, in the case of an image darker than the luminance at the time of the reset discharge in the reset period or a dark image slightly brighter than the luminance at the time of the reset discharge, the reset discharge in the reset period may be stopped. At least the reset discharge in the reset period is stopped for a field in which no image bit information exists in one field and a field whose image is darker than the luminance at the time of the reset discharge in the reset period.

The field image information judgment circuit 21 in FIG.
As an example, as shown in FIG.
K flip-flop 212, D flip-flop 213
It is comprised including. An image signal input to the frame memory 14 is input to a terminal A of the comparison circuit 211, and a reference value is input to a terminal B. This reference value is 01H (H represents a hexadecimal number) if it is determined whether or not image bit information in one field exists, and it is determined whether or not the reference value is equal to or less than a preset value. If, the value is in accordance with the set value.

If the data inputted to the terminal A is larger than the reference value inputted to the terminal B, the comparison circuit 211
Outputs a higher signal. JK flip-flop 21
The output of the comparison circuit 211 is input to the terminal J of the second device, the vertical synchronization pulse VD is input to the terminal K, and the write clock CKW is input to the clock terminal. In addition,
Although not shown here, this write clock CKW is also supplied to the frame memory 14 and is used as a write clock for an image signal input to the frame memory 14. Once a high signal is input to the terminal J during one field period, the JK flip-flop 212 holds the output from the terminal Q high during that field period.

The output of the JK flip-flop 212 is input to the terminal D of the D flip-flop 213. The vertical synchronizing pulse V is applied to the clock terminal of the D flip-flop 213.
D is input. The D flip-flop 213 operates as a delay element, and outputs the output of the JK flip-flop 212 with a delay of one field. That is, the output from the terminal Q of the D flip-flop 213 is
It is high if image bit information in one field exists or exceeds a preset value, and if image bit information in one field does not exist at all or is equal to or less than the preset value. , Goes low. The image signal is delayed by one field by the frame memory 14, and the field image information determined by the field image information determination circuit 21 is also transmitted to the D flip-flop 2.
13 will be delayed by one field,
The image signal and the field image information are synchronized.

Since the output of the D flip-flop 213 is input to the drive pulse batch stop circuit 22 for the reset period as described above, there is no image bit information in one field, or a value equal to or less than a preset value. , The reset discharge during the reset period can be stopped.

Here, the operation of the field image information determining circuit 21 shown in FIG. 2 will be further described with reference to FIG. In FIG. 3, (A) shows a vertical synchronization pulse VD,
4B illustrates an example of data (image signal) input to a terminal A of the comparison circuit 211, and FIG. 4C illustrates a terminal B of the comparison circuit 211.
(D) shows the output waveform of the comparison circuit 211, (E) shows the output waveform of the JK flip-flop 212, and (F) shows the output waveform of the D flip-flop 213.

In the example shown in FIG. 3, in order to determine whether or not the image bit information in one field is equal to or less than a preset value, the reference value input to the terminal B of the comparison circuit 211 is determined as shown in FIG. 04H (H represents a hexadecimal number) as shown in C). In one field on the left side shown in FIG. 3, the image signal input to the terminal A of the comparison circuit 211 is smaller than the reference value 04H as shown in FIG. Is low as shown in FIG. Also, the output of the JK flip-flop 212 is low as shown in FIG. Since the output of the D flip-flop 213 does not show the state of the previous field, it is hatched as shown in FIG.

Then, in one field on the right side shown in FIG. 3, the image signal input to the terminal A of the comparison circuit 211 has data larger than the reference value 04H as shown in FIG. 3B. Therefore, as shown in FIG. 3D, the output of the comparison circuit 211 becomes high at a portion of data larger than 04H and becomes low at a portion smaller than 04H. As described above, the output of the JK flip-flop 212 keeps high once the high is input to the terminal J, so that the output of the JK flip-flop 212 first becomes as shown in FIG. ) Becomes high from the time when the output of the comparison circuit 211 becomes high. Since the output of the D flip-flop 213 is a signal obtained by delaying the field of FIG. 3E by one field, as shown in FIG.
It goes low in the field and goes high in the next field.

The sub-field image bit information determination circuit 23 in FIG. 1 is, as shown in FIG.
K flip-flop 231, D flip-flop 23
2. It comprises a selector 233. In this embodiment, since one field is divided into eight subfields in this embodiment, the number of the JK flip-flops 231 is eight, which is the number corresponding to the number of subfields in one field. The terminal J of the JK flip-flop 231 has an MSB
, The data of each bit of LSB is input, the vertical synchronization pulse VD is input to the terminal K, and the write clock CKW is input to the clock terminal. Although not shown here, this write clock CKW is also supplied to the frame memory 14 and is used as a clock for writing an image signal input to the frame memory 14.

Once a high signal is input to the terminal J during one field period, the JK flip-flop 231 holds the output from the terminal Q high during that field period. The output of each of the eight JK flip-flops 231 is the terminal D1 of the D flip-flop 232.
To D8. The vertical synchronization pulse VD is input to the clock terminal of the D flip-flop 232. This D
The flip-flop 232 operates as a delay element, and outputs the output of the JK flip-flop 231 with a delay of one field. That is, the output from the terminals Q1 to Q8 of the D flip-flop 232 is high when the image bit information of the subfield exists, and becomes low when the image bit information of the subfield does not exist at all.

The output of the D flip-flop 232 is input to the terminals SF1 to SF8 of the selector 233. The memory read control signal from the memory read control circuit 16 is input to the selector 233. In response to the memory read control signal, the selector 233 sends the frame memory 1
The sub-field image bit information corresponding to the sub-field image bit signal output from No. 4 is selectively output. The image signal is stored in the frame memory 14 as 1
The image bit information of the subfield determined by the subfield image bit information determination circuit 23 is also delayed by one field by the D flip-flop 232, so that the image signal and the image bit information of the subfield are synchronized. doing.

Since the output of the selector 233 is inputted to the reset period drive pulse batch stop circuit 22 as described above, it is necessary to stop the reset discharge in the reset period for a subfield in which no image bit information exists. Can be.

The operation of the subfield image bit information determination circuit 23 shown in FIG. 4 will be further described with reference to FIG. In FIG. 5, (A) shows a vertical synchronization pulse V
D, (B)-(I) show eight JK flip-flops 23
1 Examples of output waveforms at each terminal Q, (J) to (Q)
Represents output waveforms of the terminals Q1 to Q8 of the D flip-flop 232, (R) represents a memory read control signal input to the selector 233, and (S) represents an output waveform of the selector 233.

In one field on the left side shown in FIG. 5, eight JK flip-flops 231 are shown in FIG.
When the waveforms shown in (B) to (I) are output, the D flip-flop 232 holds high or low in one field on the right side, which is the next field, as shown in FIG.
The waveforms shown in (J) to (Q) are output. In addition, 1 on the left
In the field, since the output of the D flip-flop 232 and the output of the selector 233 do not show the state of the previous field, they are hatched as shown in FIGS. 5 (J) to (Q) and (S). Indeterminate.

Then, in one field on the right side shown in FIG. 5, the waveforms shown in FIGS. 5J to 5Q are selected by the memory read control signal shown in FIG. Therefore, the output waveform of the selector 233 becomes the waveform shown in FIG. In the example shown in FIG. 5 (S), the subfields SF1, SF3, S
Since F6 to SF8 are low, these subfields have no signal, and the driving pulse during the reset period is stopped.

As described above, all auxiliary discharges (reset discharges) which have not been directly related to the display discharge of the discharge cell section 5 and which have been generated when the input image signal is in a state of no signal (or lower than a predetermined level) are conventionally obtained. Can be eliminated. Also,
In a certain subfield, it is possible to eliminate all auxiliary discharges (reset discharges) which are not directly related to the display discharge of the discharge cell unit 5 and have occurred when the input image signal is in a no-signal state. Therefore, the floating of black is suppressed, and the sense of contrast is increased, and accordingly, the display quality is improved. Also,
Since the drive pulse in the reset period is stopped, wasteful power consumption that does not directly contribute to display discharge can be reduced.

In the present invention, the field image information judgment circuit 21 and the subfield image bit information judgment circuit 2
3, the objective of improving the contrast and reducing the power consumption can be achieved even when there is no image bit information only in a certain subfield.
Further, since the field image information determination circuit 21 is provided separately from the subfield image bit information determination circuit 23, even when the image bit information in one field is equal to or less than a preset value, the improvement of the contrast and the power consumption can be achieved. It is possible to achieve the purpose of reduction of the number.

<Second Embodiment> Next, a description will be given of a second embodiment of a drive control device for a plasma display panel display device according to the present invention. FIG. 2 shows a plasma display panel used in the plasma display panel display device of the present invention.
9 and FIG.

First, a second embodiment of the drive control device of the present invention will be systematically described with reference to FIGS.
In FIGS. 13 and 14, RST is a reset period, AD
R is an address period, and SUS is a sustain discharge period. A1
In the address electrodes 2 indicated by .about.Am, the presence or absence of an address pulse is indicated by "present" and "absent".
In the electrode 3 and the Y electrode 4 represented by Y1 to Yn,
The presence / absence of drive pulses (erase pulse, write pulse, sustain voltage hold pulse, scan pulse, sustain pulse) is represented by “” ”and“ × ”. FIG. 13 shows a case where all the image bit information of one field does not exist in all the effective image areas displayed by the plasma display panel display device. FIG. 14 shows a case where the image bit information is displayed by the plasma display panel display device. Sub-field SF in all effective image areas
8 shows a case where no image bit information exists at all.

As can be seen from FIG. 13, when a state where no image bit information is present in all one field is detected, the X electrode 3 and the Y electrode 4 are reset during the reset period.
By stopping the supply of the drive pulses (erase pulse, write pulse) to the X-axis, all the reset discharges between the X electrode 3 and the Y electrode 4 are stopped. Further, in the address period, the supply of drive pulses (sustain voltage hold pulse and scan pulse) to the X electrode 3 and the Y electrode 4 is all stopped.

As can be seen from FIG. 14, when a state in which no image bit information exists in the subfield is detected, drive pulses (erase pulse, write pulse) to the X electrode 3 and the Y electrode 4 during the reset period. Is stopped, all the reset discharges to be discharged between the X electrode 3 and the Y electrode 4 are stopped.
Further, during the address period, the X electrode 3 and the Y electrode 4
All the supply of the drive pulses (sustain voltage hold pulse, scan pulse) to the controller is stopped.

More specifically, when there is no image bit information in all of one field, as shown in FIG. 12, in all subfields, supply to each of the electrodes 3 and 4 is performed in the reset period and the address period. Stop all pulses to be performed and force no pulses to be applied. When no image bit information is present in a certain subfield, in the subfield (here, subfield SF8), as shown in FIG. 12, the image bit information is supplied to each of the electrodes 3 and 4 in the reset period and the address period. All necessary pulses are stopped to forcibly apply no pulse.
Other subfields SF1 to SF1 where image bit information exists
In SF7, as in the prior art, as shown in FIG.
Each of the electrodes 3, 4 is also used during the reset period and the address period.
To the pulse.

According to the driving method shown in FIG. 12, FIG.
Similarly to 2, in order to obtain 256 gradations (8 bits), 1
Field (16.6 ms) with different relative ratio of luminance 8
When the image data is divided into subfields (SF1 to SF8) and the subfields are sequentially formed from the LSB (least significant bit) to the MSB (most significant bit) of the image bit information, 1
When there is no image bit information of all the fields, as shown in FIG. 15, the reset period and the address period in each subfield are all idle periods.
In FIG. 15, the reset period and the address period of the subfield SF6 are shown as the idle periods, but other subfields SF1 to SF5, SF7, S
The reset period and address period of F8 are also idle periods.

When no image bit information exists in a certain subfield, as shown in FIG. 16, the reset period and the address period in each subfield are suspended in the subfield SF8 in which no image bit information exists. Period and other subfield S
In F1 to SF7, the reset period and the address period are the same as those in the related art.

Here, the configuration of the drive control device of the plasma display panel display device for realizing the second embodiment will be described with reference to FIG. 11, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The field image information output from the field image information determination circuit 21 and the subfield image bit information output from the subfield image bit information determination circuit 23 are combined into a reset period drive pulse batch stop circuit 22 and an address period drive pulse batch stop circuit 24. , Are input to the drive pulse generation circuit 17.

Drive pulse batch stop circuit 22 for reset period
While the field image information determination circuit 21 determines that the field image information does not reach the preset gradation, all drive pulses supplied to the electrodes 3 and 4 are forcibly reset during the reset period. Is supplied to the drive pulse generation circuit 17. As a result, the reset discharge in the reset period is stopped for the field in which it is determined that no image bit information exists in one field.

The reset period drive pulse batch stop circuit 22 includes a subfield image bit information determination circuit 23.
For a subfield determined to have no image bit information, a reset period drive pulse batch stop signal for forcibly stopping all drive pulses supplied to each of the electrodes 3 and 4 during the reset period is provided by a drive pulse generation circuit. 17. As a result, the reset discharge in the reset period is stopped for the subfield for which it is determined that no image bit information exists.

Further, the address period drive pulse collective stop circuit 24 determines whether each of the electrodes 3 is in the address period while the field image information determination circuit 21 determines that the field image information does not reach the preset gradation. , 4 are supplied to the drive pulse generation circuit 17 in an address period drive pulse batch stop signal for forcibly stopping all the drive pulses. As a result, the drive pulse in the address period is stopped for the field in which it is determined that no image bit information exists in one field.

The address period drive pulse batch stop circuit 24 is provided with a sub-field image bit information determination circuit 23.
For the sub-field determined to have no image bit information, the driving pulse generation circuit generates an address period driving pulse batch stop signal for forcibly stopping all the driving pulses supplied to each of the electrodes 3 and 4 during the address period. 17. Thus, the drive pulse in the address period is stopped for the subfield for which it is determined that no image bit information exists.

In this embodiment, in the effective image area, 1
The drive pulse in the reset period and the address period is stopped for a field in which it is determined that there is no image bit information in the field, but the image bit information in one field is set to a preset value. The drive pulse in the reset period and the address period may be stopped for the field determined to be the following. That is, in the case of an image darker than the luminance during the auxiliary discharge in the reset period or a dark image slightly brighter than the luminance during the auxiliary discharge, the driving pulse in the reset period and the address period may be stopped.
At least for a field in which no image bit information is present in one field and a field which is an image darker than the luminance at the time of the auxiliary discharge in the reset period,
The driving pulse in the reset period and the address period is stopped.

As described above, all auxiliary discharges (reset discharges) which have not been directly related to the display discharge of the discharge cell unit 5 and which have been generated when the input image signal is in a state of no signal (or a predetermined level or less) are conventionally obtained. Can be eliminated. Also,
In a specific subfield, it is possible to eliminate all auxiliary discharges (reset discharges) which are not directly related to the display discharge of the discharge cell unit 5 and occurred when no input image bit information is present. Therefore, the floating of black is suppressed, and the sense of contrast is enhanced, and accordingly, the display quality is improved.
Further, since the driving pulses in the reset period and the address period are stopped, power consumption can be further reduced as compared with the first embodiment.

In the present invention, the field image information judgment circuit 21 and the subfield image bit information judgment circuit 2
3, the objective of improving the contrast and reducing the power consumption can be achieved even when there is no image bit information only in a certain subfield.
Further, since the field image information determination circuit 21 is provided separately from the subfield image bit information determination circuit 23, even when the image bit information in one field is equal to or less than a preset value, the improvement of the contrast and the power consumption can be achieved. It is possible to achieve the purpose of reduction of the number.

<Third Embodiment> Further, a description will be given of a third embodiment of the drive control device for a plasma display panel display device according to the present invention. The plasma display panel used for the plasma display panel display device of the present invention is the same as that shown in FIGS.

First, a third embodiment of the drive control device according to the present invention will be systematically described with reference to FIGS. 19 and 20.
In FIGS. 19 and 20, RST is a reset period, AD
R is an address period, and SUS is a sustain discharge period. A1
In the address electrodes 2 indicated by .about.Am, the presence or absence of an address pulse is indicated by "present" and "absent".
In the electrode 3 and the Y electrode 4 represented by Y1 to Yn,
The presence / absence of drive pulses (erase pulse, write pulse, sustain voltage hold pulse, scan pulse, sustain pulse) is represented by “” ”and“ × ”. FIG. 19 shows a case where image bit information of all one field does not exist at all in all effective image areas displayed by the plasma display panel display device, and FIG. Sub-field SF in all effective image areas
8 shows a case where no image bit information exists at all.

As can be seen from FIG. 19, when a state where no image bit information is present in all one field is detected, the X electrode 3 and the Y electrode 4
By stopping the supply of the drive pulses (erase pulse, write pulse) to the X-axis, all the reset discharges between the X electrode 3 and the Y electrode 4 are stopped. Further, in the sustain discharge period, all the supply of the driving pulse (sustain pulse) to the X electrode 3 and the Y electrode 4 is stopped.

As can be seen from FIG. 20, when a state where no image bit information exists in the subfield is detected, drive pulses (erase pulse, write pulse) to the X electrode 3 and the Y electrode 4 during the reset period. Is stopped, all the reset discharges to be discharged between the X electrode 3 and the Y electrode 4 are stopped.
Further, during the sustain discharge period, the X electrode 3 and the Y electrode 4
All the supply of the drive pulse (sustain pulse) to is stopped.

Specifically, when there is no image bit information in all of one field, as shown in FIG. 18, in each of the subfields, the electrodes 3 and 4 are applied to the electrodes 3 and 4 during the reset period and the sustain discharge period. Stop all pulses to be supplied, forcing no pulses to be applied. When no image bit information is present in a certain subfield, in the subfield (here, subfield SF8), as shown in FIG. Stop all pulses to be performed and force no pulses to be applied.
Other subfields SF1 to SF1 where image bit information exists
In SF7, as in the prior art, as shown in FIG.
Even during the reset period and the sustain discharge period, each of the electrodes 3, 4
To the pulse.

According to the driving method shown in FIG. 18, FIG.
Similarly to 2, in order to obtain 256 gradations (8 bits), 1
Field (16.6 ms) with different relative ratio of luminance 8
When the image data is divided into subfields (SF1 to SF8) and the subfields are sequentially formed from the LSB (least significant bit) to the MSB (most significant bit) of the image bit information, 1
When the image bit information of all the fields does not exist at all, as shown in FIG. 21, the reset period and the sustain discharge period in each subfield are all idle periods.
In FIG. 14, the reset period and the sustain discharge period of the subfield SF6 are shown as the idle periods, but other subfields SF1 to SF5, SF7, S
The reset period and the sustain discharge period of F8 are also idle periods.

When there is no image bit information in a certain subfield, as shown in FIG. 22, the reset period and the sustain discharge period in each subfield are performed in subfield SF8 in which no image bit information exists. During the suspension period, another subfield S
In F1 to SF7, the reset period and the sustain discharge period are the same as in the related art.

Here, the configuration of a plasma display panel display device for realizing the third embodiment will be described with reference to FIG. 17, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. The field image information output from the field image information determination circuit 21 and the subfield image bit information output from the subfield image bit information determination circuit 23 are combined into a reset period drive pulse batch stop circuit 22 and a sustain discharge period drive pulse batch stop circuit. 25, which is input to the drive pulse generation circuit 17.

Reset pulse driving pulse batch stop circuit 22
While the field image information determination circuit 21 determines that the field image information does not reach the preset gradation, all drive pulses supplied to the electrodes 3 and 4 are forcibly reset during the reset period. Is supplied to the drive pulse generation circuit 17. As a result, the reset discharge in the reset period is stopped for the field in which it is determined that no image bit information exists in one field.

The reset period drive pulse batch stop circuit 22 includes a subfield image bit information determination circuit 23.
For a subfield determined to have no image bit information, a reset period drive pulse batch stop signal for forcibly stopping all drive pulses supplied to each of the electrodes 3 and 4 during the reset period is provided by a drive pulse generation circuit. 17. As a result, the reset discharge in the reset period is stopped for the subfield for which it is determined that no image bit information exists.

Further, the sustain discharge period drive pulse collective stop circuit 25 performs each sustain discharge period during the sustain discharge period while the field image information determination circuit 21 determines that the field image information does not reach the preset gradation. A sustaining discharge period drive pulse collective stop signal for forcibly stopping all drive pulses supplied to the electrodes 3 and 4 is supplied to the drive pulse generation circuit 17. As a result, the drive pulse in the sustain discharge period is stopped for a field in which it is determined that no image bit information exists in one field.

The sustain discharge period drive pulse collective stop circuit 25 includes a subfield image bit information determination circuit 23.
For the subfield determined to have no image bit information, the driving pulse for the sustain discharge period drive pulse collective stop signal for forcibly stopping all the drive pulses supplied to the electrodes 3 and 4 during the sustain discharge period It is supplied to the generation circuit 17. Thus, the drive pulse in the sustain discharge period is stopped for the subfield for which it is determined that no image bit information exists.

In this embodiment, in the effective image area, 1
The configuration is such that the drive pulse in the reset period and the sustain discharge period is stopped for a field in which it is determined that there is no image bit information in the field. The drive pulse in the reset period or the sustain discharge period may be stopped for the field determined to be equal to or less than the value. That is, in the case of an image darker than the luminance during the auxiliary discharge in the reset period or a dark image slightly brighter than the luminance during the auxiliary discharge, the driving pulse in the reset period or the sustain discharge period may be stopped. At least the drive pulse in the reset period and the sustain discharge period is stopped for a field in which no image bit information is present in one field and a field whose image is darker than the luminance during the auxiliary discharge in the reset period.

As described above, all auxiliary discharges (reset discharges) which have not been directly related to the display discharge of the discharge cell unit 5 and which have been generated when the input image signal is in a state of no signal (or lower than a predetermined level) are conventionally obtained. Can be eliminated. Also,
In a specific subfield, it is possible to eliminate all auxiliary discharges (reset discharges) which are not directly related to the display discharge of the discharge cell unit 5 and occurred when no input image bit information is present. Therefore, the floating of black is suppressed, and the sense of contrast is enhanced, and accordingly, the display quality is improved.
Further, since the driving pulses in the reset period and the sustain discharge period are stopped, the power consumption can be further reduced as compared with the first embodiment.

In the present invention, the field image information judgment circuit 21 and the subfield image bit information judgment circuit 2
3, the objective of improving the contrast and reducing the power consumption can be achieved even when there is no image bit information only in a certain subfield.
Further, since the field image information determination circuit 21 is provided separately from the subfield image bit information determination circuit 23, even when the image bit information in one field is equal to or less than a preset value, the improvement of the contrast and the power consumption can be achieved. It is possible to achieve the purpose of reduction of the number.

<Fourth Embodiment> Next, a description will be given of a fourth embodiment of the drive control device for a plasma display panel display device according to the present invention. The plasma display panel used for the plasma display panel display device of the present invention is the same as that shown in FIGS.

First, a fourth embodiment of the driving method according to the present invention will be systematically described with reference to FIGS. 25 and 26. FIG.
5, in FIG. 26, RST is a reset period, ADR is an address period, and SUS is a sustain discharge period. A1 to A
The presence / absence of an address pulse is indicated by “present” or “absent” in the address electrode 2 indicated by m, and the drive pulse (erase pulse) is indicated by the X electrode 3 indicated by X and the Y electrode 4 indicated by Y1 to Yn. , Write pulse, sustain voltage hold pulse, scan pulse, sustain pulse) are represented by ““ ”and“ × ”. Note that FIG.
5 shows a case where image bit information of all one field does not exist at all in all effective image areas displayed by the plasma display panel display device.
Reference numeral 6 denotes a subfield SF8 in all effective image areas displayed by the plasma display panel display device.
Only the case where there is no image bit information is shown.

As can be seen from FIG. 25, when a state where no image bit information is present in all one field is detected, drive pulses (erase pulse, write pulse) to the X electrode 3 and the Y electrode 4 during the reset period.
Is stopped, all the reset discharges to be discharged between the X electrode 3 and the Y electrode 4 are stopped. Further, in both the address period and the sustain discharge period, the supply of the driving pulses (sustain voltage hold pulse, scan pulse, sustain pulse) to the X electrode 3 and the Y electrode 4 is all stopped.

As can be seen from FIG. 26, when a state where no image bit information exists in the subfield is detected, drive pulses (erase pulse, write pulse) to the X electrode 3 and the Y electrode 4 during the reset period. Is stopped, all the reset discharges to be discharged between the X electrode 3 and the Y electrode 4 are stopped.
Furthermore, in both the address period and the sustain discharge period,
Driving pulses (sustain voltage hold pulse, scan pulse, sustain pulse) to X electrode 3 and Y electrode 4
Stop all supply of.

More specifically, when there is no image bit information in all of one field, as shown in FIG. 24, in all of the subfields, in each of the reset period, the address period, and the sustain discharge period, Electrodes 3, 4
Is stopped, and no pulse is applied. If there is no image bit information in a certain subfield, the subfield (here, subfield S
In F8), as shown in FIG.
In each of the address period and the sustain discharge period, each electrode 3,
Stop all the pulses to be supplied to 4 and force no pulses to be applied. In the other subfields SF1 to SF7 where the image bit information exists, a pulse is supplied to each of the electrodes 3 and 4 during the reset period and the address period as shown in FIG.

According to the driving method shown in FIG.
Similarly to 2, in order to obtain 256 gradations (8 bits), 1
Field (16.6 ms) with different relative ratio of luminance 8
When the image data is divided into subfields (SF1 to SF8) and the subfields are sequentially formed from the LSB (least significant bit) to the MSB (most significant bit) of the image bit information, 1
If there is no image bit information in all fields, the reset period, address period, and sustain discharge period in each subfield are all idle periods as shown in FIG.

When there is no image bit information in a certain subfield, as shown in FIG. 28, the reset period, address period, and sustain discharge period in each subfield correspond to a subfield in which no image bit information exists. In the field SF8, a rest period is set, and in the other subfields SF1 to SF7, a reset period, an address period, and a sustain discharge period are performed as in the related art.

Here, the configuration of the plasma display panel display of the fourth embodiment will be described with reference to FIG. 23, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. The field image information output from the field image information determination circuit 21 and the subfield image bit information output from the subfield image bit information determination circuit 23 are combined into a reset period drive pulse batch stop circuit 22 and an address period drive pulse batch stop circuit 24. , Sustain discharge period drive pulse batch stop circuit 25,
It is input to the drive pulse generation circuit 17.

Reset period drive pulse batch stop circuit 22
While the field image information determination circuit 21 determines that the field image information does not reach the preset gradation, all drive pulses supplied to the electrodes 3 and 4 are forcibly reset during the reset period. Is supplied to the drive pulse generation circuit 17. As a result, the auxiliary discharge during the reset period is stopped for the field in which it is determined that no image bit information exists in one field.

The reset period drive pulse batch stop circuit 22 includes a subfield image bit information determination circuit 23.
For a subfield determined to have no image bit information, a reset period drive pulse batch stop signal for forcibly stopping all drive pulses supplied to each of the electrodes 3 and 4 during the reset period is provided by a drive pulse generation circuit. 17. As a result, the reset discharge in the reset period is stopped for the subfield for which it is determined that no image bit information exists.

Further, the address period drive pulse collective stop circuit 24 controls each electrode 3 during the address period while the field image information determination circuit 21 determines that the field image information does not reach the preset gradation. , 4 are supplied to the drive pulse generation circuit 17 in an address period drive pulse batch stop signal for forcibly stopping all the drive pulses. As a result, the drive pulse in the address period is stopped for the field in which it is determined that no image bit information exists in one field.

The address period drive pulse batch stop circuit 24 is provided with a sub-field image bit information determination circuit 23.
For the sub-field determined to have no image bit information, the driving pulse generation circuit generates an address period driving pulse batch stop signal for forcibly stopping all the driving pulses supplied to each of the electrodes 3 and 4 during the address period. 17. Thus, the drive pulse in the address period is stopped for the subfield for which it is determined that no image bit information exists.

Furthermore, the sustain discharge period drive pulse collectively stopping circuit 25 performs each sustain discharge period during the sustain discharge period while the field image information determination circuit 21 determines that the field image information does not reach the preset gradation. A sustaining discharge period drive pulse collective stop signal for forcibly stopping all drive pulses supplied to the electrodes 3 and 4 is supplied to the drive pulse generation circuit 17. As a result, the drive pulse in the sustain discharge period is stopped for a field in which it is determined that no image bit information exists in one field.

The sustain discharge period drive pulse batch stop circuit 25 includes a subfield image bit information determination circuit 23.
For the subfield determined to have no image bit information, the driving pulse for the sustain discharge period drive pulse collective stop signal for forcibly stopping all the drive pulses supplied to the electrodes 3 and 4 during the sustain discharge period It is supplied to the generation circuit 17. Thus, the drive pulse in the sustain discharge period is stopped for the subfield for which it is determined that no image bit information exists.

In this embodiment, in the effective image area, 1
The drive pulse in the reset period, the address period, and the sustain discharge period is stopped for a field in which it is determined that no image bit information exists in the field. The drive pulse in the reset period, the address period, and the sustain discharge period may be stopped for the field determined to be equal to or less than the set value. That is, in the case of an image darker than the luminance during the auxiliary discharge during the reset period or a dark image slightly brighter than the luminance during the auxiliary discharge, the driving pulse during the reset period, the address period, and the sustain discharge period may be stopped. Good. At least one
For a field in which no image bit information is present in the field and a field whose image is darker than the luminance at the time of the auxiliary discharge in the reset period, the reset period,
The drive pulse in the address period and the sustain discharge period is stopped.

As described above, all auxiliary discharges (reset discharges) which have not been directly related to the display discharge of the discharge cell unit 5 and which have been generated when the input image signal is in the state of no signal (or lower than a predetermined level) are conventionally obtained. Can be eliminated. Also,
In a specific subfield, it is possible to eliminate all auxiliary discharges (reset discharges) which are not directly related to the display discharge of the discharge cell unit 5 and occurred when no input image bit information is present. Therefore, the floating of black is suppressed, and the sense of contrast is enhanced, and accordingly, the display quality is improved.
Further, since the driving pulses in the reset period, the address period, and the sustain discharge period are stopped, the power consumption can be further reduced as compared with the first to third embodiments.

In the present invention, the field image information judgment circuit 21 and the subfield image bit information judgment circuit 2
3, the objective of improving the contrast and reducing the power consumption can be achieved even when there is no image bit information only in a certain subfield.
Further, since the field image information determination circuit 21 is provided separately from the subfield image bit information determination circuit 23, even when the image bit information in one field is equal to or less than a preset value, the improvement of the contrast and the power consumption can be achieved. It is possible to achieve the purpose of reduction of the number.

In the first to fourth embodiments, the plasma display panel display device having the AC plasma display panel 1 has been described. However, the drive control device of the present invention is not limited to the plasma display panel having the DC plasma display panel. In addition to performing display discharge (display write discharge and sustain discharge), including display panel display devices,
The present invention can be similarly applied to all plasma display panel display devices that also perform auxiliary discharge (auxiliary discharge not directly related to display discharge). For example, in a plasma display panel display device in which an auxiliary discharge not directly related to the halftone display is performed in the address period, similarly, the driving pulse related to the auxiliary discharge is stopped.

Further, the present invention relates to FIG.
The configuration is not limited to those shown in FIGS. 11, 17, and 23, and can be variously changed without departing from the gist of the present invention. As an example, in the present embodiment, the reset period drive pulse batch stop circuit 22, the address period drive pulse batch stop circuit 24, and the sustain discharge period drive pulse batch stop circuit 2
5, the driving pulse in each period is stopped. However, the driving pulse may be configured as follows. That is, the subfield image bit information output from the subfield image bit information determination circuit 22 is input to the X electrode driving circuit 19 and the Y electrode driving circuit 20, and the X electrode driving circuit 19 and the Y electrode driving circuit 20 By setting the voltage value to 0, the drive pulse supplied (applied) to the plasma display panel 1 in each period can be stopped.

[0105]

As described in detail above, the drive control device for a plasma display panel display device of the present invention is:
A memory for storing image signals, a memory write control circuit for controlling writing of image signals to the memory, a memory read control circuit for controlling to read image bit signals from the memory for each subfield, and A field image information determination circuit that determines whether bit information is present or whether image bit information is equal to or less than a preset value, and determines whether image bit information is present in one subfield. And a sub-field image bit information determination circuit that performs
The black level is reduced by lowering the black level both when the image bit information does not exist in the field or when the image bit information is equal to or less than a preset value and when the image bit information does not exist in one subfield. Can be improved. In addition, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a specific configuration of a field image information determination circuit 21 in FIGS. 1, 11, 17, and 23;

FIG. 3 is a timing chart for explaining the operation of FIG. 2;

FIG. 4 is a block diagram showing an example of a specific configuration of a sub-field image bit information determination circuit 23 in FIGS. 1, 11, 17, and 23;

FIG. 5 is a timing chart for explaining the operation of FIG. 4;

FIG. 6 is a diagram showing an example of a driving waveform for explaining a display operation according to the first embodiment of the present invention.

FIG. 7 is a diagram systematically showing a first embodiment of the present invention.

FIG. 8 is a diagram systematically showing a first embodiment of the present invention.

FIG. 9 is a diagram showing an example of an operation in the case of performing halftone display by subfield division in the first embodiment of the present invention.

FIG. 10 is a diagram showing an example of an operation in the case where halftone display is performed by subfield division in the first embodiment of the present invention.

FIG. 11 is a block diagram showing a second embodiment of the present invention.

FIG. 12 is a diagram showing an example of a driving waveform for explaining a display operation according to a second embodiment of the present invention.

FIG. 13 is a diagram systematically showing a second embodiment of the present invention.

FIG. 14 is a view systematically showing a second embodiment of the present invention.

FIG. 15 is a diagram illustrating an example of an operation when displaying a halftone by subfield division according to the second embodiment of the present invention.

FIG. 16 is a diagram illustrating an example of an operation when displaying a halftone by subfield division in the second embodiment of the present invention.

FIG. 17 is a block diagram showing a third embodiment of the present invention.

FIG. 18 is a diagram showing an example of a driving waveform for explaining a display operation according to a third embodiment of the present invention.

FIG. 19 is a view systematically showing a third embodiment of the present invention.

FIG. 20 is a diagram systematically showing a third embodiment of the present invention.

FIG. 21 is a diagram illustrating an example of an operation when halftone display is performed by subfield division according to the third embodiment of the present invention.

FIG. 22 is a diagram illustrating an example of an operation when halftone display is performed by subfield division according to the third embodiment of the present invention.

FIG. 23 is a block diagram showing a fourth embodiment of the present invention.

FIG. 24 is a diagram showing an example of a driving waveform for explaining a display operation according to a fourth embodiment of the present invention.

FIG. 25 is a view systematically showing a fourth embodiment of the present invention.

FIG. 26 is a diagram systematically showing a fourth embodiment of the present invention.

FIG. 27 is a diagram illustrating an example of an operation when halftone display is performed by subfield division according to the fourth embodiment of the present invention.

FIG. 28 is a diagram illustrating an example of an operation when halftone display is performed by subfield division according to the fourth embodiment of the present invention.

FIG. 29 is a plan view schematically showing a three-electrode type surface discharge type plasma display panel.

FIG. 30 is a partial perspective view showing an example of a cross section of a three-electrode type surface discharge type plasma display panel.

FIG. 31 is a diagram showing an example of a driving waveform for explaining a display operation according to a conventional example.

FIG. 32 is a diagram showing an example of an operation in the case of performing a halftone display by subfield division in a conventional example.

FIG. 33 is a view systematically showing a conventional example.

FIG. 34 is a view systematically showing a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Plasma display panel 2 Address electrode 3 X electrode 4 Y electrode 5 Discharge cell part 14 Frame memory 15 Memory write control circuit 16 Memory read control circuit 17 Drive pulse generation circuit 18 Address electrode drive circuit 19 X electrode drive circuit 20 Y electrode drive circuit 21 Field Image Information Judgment Circuit 22 Reset Period Drive Pulse Batch Stop Circuit (Reset Period Drive Pulse Stopping Means) 23 Subfield Image Bit Information Judgment Circuit 24 Address Period Drive Pulse Batch Stop Circuit (Address Period Drive Pulse Stop Means) 25 Sustain Discharge Period Drive pulse batch stop circuit (sustain discharge period drive pulse stop means)

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 7, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

The Y electrode 4 is fixed at a voltage of Va, which is the same potential as the address pulse, during most of the address period. Y1 to electrode Yn
, A scan pulse for applying a voltage of 0 V in the same phase as the address pulse is applied in order one row at a time. Thus, only when the address pulse is applied to the address electrode 2 and the scan pulse is applied to the Y electrode 4, the voltage Va is superimposed on the remaining wall charge after the reset period, and the discharge start voltage As described above, a display write discharge occurs, and image bit information is written. Further, at this time, wall charges remain in the discharge cell portion 5 as in the above-described all-screen batch writing in the reset period.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

In the sustain discharge period, the Y electrode 4 and the X electrode
Sustain pulses for maintaining discharge are applied to the electrodes 3 alternately. At this time, the address electrode 2 has been fixed to 0V, and re-discharge only in amounts and sub <br/> stearyl impulses wall charges remaining on the image bit information discharge cell unit 5 which is written in the address period (Sustain discharge). Therefore, in the sustain discharge period, the discharge continues only as many times as the number of times the sustain pulse is applied, only in the discharge cell unit 5 in which the image bit information is written in the address period. As described above, in the AC type plasma display panel, the panel can have a memory function by remaining wall charges in the cell itself.

Claims (4)

[Claims] 1. A method according to claim 1, wherein one sub-field is divided into a plurality of sub-fields to perform halftone display of an image signal, and said sub-field is composed of a reset period, an address period, and a sustain discharge period. In the plasma display panel display device, a display discharge related to the halftone display of the image signal is performed in the sustain discharge period, and an auxiliary discharge not directly related to the halftone display is performed in the reset period or the address period. In the drive control device, a memory that stores the image signal; a memory write control circuit that controls writing of the image signal to the memory; and a memory read control that controls the image signal to be read from the memory for each subfield. Circuit and image bit information in one field A field image information determining circuit for determining whether or not the image bit information is equal to or less than a preset value, and a subfield image for determining whether or not image bit information exists in one subfield. A drive control device for a plasma display panel display device, comprising: a bit information determination circuit. 2. The driving pulse during the reset period is stopped for a field for which it is determined by the field image information determining circuit that the image bit information does not exist at all or is equal to or less than a preset value. In addition, the sub-field image bit information determination circuit further includes a reset period drive pulse stopping unit for stopping a drive pulse in the reset period for a subfield for which it is determined that the image bit information does not exist at all. 2. The drive control device for a plasma display panel display device according to claim 1, wherein: 3. The driving pulse in the address period is stopped for a field determined by the field image information determination circuit that the image bit information does not exist at all or is equal to or less than a preset value. In addition, the subfield image bit information determination circuit further includes an address period drive pulse stop unit for stopping a drive pulse in the address period for a subfield for which it is determined that the image bit information does not exist at all. 3. The drive control device for a plasma display panel display device according to claim 1, wherein: 4. The driving pulse in the sustain discharge period is stopped for a field in which the image bit information is determined not to exist at all or to be equal to or less than a preset value by the field image information determining circuit. And a sustain discharge period drive pulse stopping means for stopping a drive pulse in the sustain discharge period for a subfield for which the subfield image bit information determination circuit determines that the image bit information does not exist at all. 4. The driving control device for a plasma display panel display device according to claim 1, wherein the driving control device is configured as follows.