JPH10178527A - Image data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image data processor which controls access to a memory device that stores digital image data and optionally changes the arrangement of divided images by having a means which adds information that optionally designates a heading address of access start to a part of an address designating signal. SOLUTION: This device has DRAM 1 which stores digital image data of prescribed image numbers and an address designating circuit 2 which accesses an image data storage area of the DRAM 1. The circuit 2 has an address generating part and a means which adds information that optionally designates a heading address of access start to a part of an address designating signal, i.e., a preset register which can optionally designate a write start address. That is, the circuit 2 has a RAS(row address strobe) address counter 21, a CAS (column address strobe) address counter 22, a R preset register 23 and a C preset register 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing apparatus capable of expressing a special image by controlling a process of writing a digital image signal to a memory device and a process of reading a digital image signal from the memory device. .

[0002]

2. Description of the Related Art In recent years, with the development and spread of computers and their peripheral devices, video equipment has been increasingly processed by digital signals, and image signal processing devices adapted to digital image signals have been actively developed. It is.

In electronic cameras such as television cameras and video devices, electronic cameras and computer graphics devices, and storage devices (magnetic tapes, magnetic disks, optical disks and semiconductor memories), signal processing is performed in the form of digital image signals. It is often said.

For example, in an electronic still camera, a built-in memory device can store a plurality of still images,
One image is read out and displayed on a monitor, and a plurality of divided images are displayed on a screen at one time. If a plurality of divided images are displayed on the screen at one time, the user can select a desired image among them and display it alone on the screen or transfer it to another device.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image data processing apparatus capable of controlling access to a memory device for storing digital image data and changing the arrangement of divided images arbitrarily. .

[0006]

According to the present invention, there is provided an image data processing apparatus comprising: a memory device for storing digital image data of a predetermined number of pixels; and an address designating means for accessing an image data storage area of the memory device. An address generating unit for sequentially generating an address specifying signal for specifying an address to be accessed in a data storage area of the image memory device in accordance with a clock signal; Means for adding information for arbitrarily designating the start address of the access start to a part thereof.

[0007]

FIG. 1 shows an embodiment of an image display method which can be performed by using an image data processing apparatus according to the present invention. Now, DRAM (Dynamic Lando)
m Access Memory) is divided into four equal areas as shown in FIG. 1A, and four different image data of A, B, C, and D are stored in those areas. Is stored. The pixel data is horizontally scanned and read from the upper left corner of the memory in the right direction of the screen, and after reading one horizontal scanning line extending over the areas A and B, the next immediately lower pixel is first set to 1
The data is read by scanning the lines. In this way, the pixel data up to the bottom line is sequentially scanned and read.
If they are sequentially displayed on the display device, the displayed four divided images A, B, C, and D have exactly the same address arrangement relationship of the data stored in the memory ((a) in FIG. 1). This is a normal read scan.

However, when reading is started from the pixel data shown in FIG. 1B and the pixel data is horizontally scanned in the right direction of the screen and read for one horizontal scanning line,
Next, as shown in FIG. 1B, data is read by scanning one line starting from the pixel data immediately below, as a start point, and the pixel data up to the lowest line is sequentially scanned and read. If these are sequentially displayed on the display device, the display screen becomes as shown in FIG. 1C, and an image different from the original data arrangement relation in the memory is displayed. In this case, the relationship is such that the divided images are arranged left and right with respect to the original image arrangement at the center of the screen.

Further, reading is started from the pixel data shown in FIG. 2A, and the pixel data is horizontally scanned in the right direction of the screen as shown in FIG. Then, data is read out by scanning one line with the next pixel data immediately below as a start point, and the pixel data up to the lowest line is sequentially scanned and read out. After the scanning of the bottom line is completed, the process moves to the scanning of the top line. If they are sequentially displayed on the display device, the display screen becomes as shown in FIG. In this case, the divided image is switched between the upper half and the lower half with respect to the original image arrangement.

Further, reading is started from the pixel data shown in FIG. 3A, and the pixel data is horizontally scanned in the right direction of the screen as shown in FIG. Then, data is read out by scanning one line with the next pixel data immediately below as a start point, and the pixel data up to the lowest line is sequentially scanned and read out. The top line is read next to the bottom line, and one screen is read. If they are displayed sequentially on the display device,
The display screen is as shown in FIG.

[0011] Such a movement of the divided screen can be performed by changing the start address of reading data from the memory. Also, by changing the write start address when writing the original image data to the memory, the arrangement of the divided images in the memory can be changed,
If data is read out from the memory in a normal order and displayed as an image, an arrangement different from the arrangement of the divided images in the original image data is displayed.

In the embodiment of the image data processing apparatus of the present invention, a preset register capable of arbitrarily designating a write start address (or a read start address) is provided.

FIG. 4 is a block diagram showing a configuration of an image data processing device according to an embodiment of the present invention. In the figure, 1 is a DRAM, 2 is an address designating circuit, and 3 is a display device. The DRAM 1 and the address designating circuit 2 are connected by an address bus 11, and the DRAM 1
And the display device 3 are connected by a data bus 12.

The address designating circuit 2 has a RAS (Row)
Address Strobe) Address counter 21
And CAS (Column Address Stro)
be) It has an address counter 22, an R preset register 23 and a C preset register 24. The addressing circuit 2 operates in synchronization with a clock signal from a clock signal generator (not shown).

Now, in the DRAM 1, as shown in FIG.
It is assumed that image data consisting of a pixel data array of 512 rows × 512 columns is stored in which four divided images each having a pixel array of 256 rows × 256 columns are arranged. This D
The address designation signal for accessing the RAM 1 is shown in FIG.
As shown in the figure, the RAS signal and the CAS signal are included. R
Both the AS signal and the CAS signal consist of 9 bits. By changing the one most significant bit, the scan head position is determined. For example, when the most significant bits of the RAS and CAS signals are “0, 0”, the access start address is the pixel of FIG. 5, and when the most significant bit is “0, 1”, the start address is “0”. The pixel whose address is “1, 0”
In the case of, the pixel is a, and in the case of "1, 1", the start address is the pixel. RAS and CA
The most significant bit of S is arbitrarily set externally in the R preset register and the C preset register. DRAM1
Receives a 9-bit RAS signal, and then receives a 9-bit CAS signal to select an address from which data is read or written.

When reading from the DRAM 1 is started, R
The reset signal RST is supplied to the address counter 21 and the C address counter 22. By the reset signal RST, the count value of the C address counter 22 becomes 1
Bit is set to the value of the C preset register 24,
The lower 8 bits are set to 0. As for the count value of the R address counter 21, the most significant 1 bit is set to the value of the R preset register 23 and the lower 8 bits are set to 0.

The C address counter 22 counts in synchronization with the clock timing. The C (column) address indicates a pixel position (horizontal direction in the figure) in one line. When the count value of the C address counter 22 reaches the maximum value, it returns to 0, and the count value circulates. When the count value of the C address counter 22 reaches the maximum value, the R address counter 21 increments the R (row) address by one. When the R address reaches the maximum value, it returns to 0 and goes round. Thereafter, the same operation is performed to sequentially access and read 512 lines. If the start address is a pixel, the screen display of FIG. 1C is obtained. If the start address is a pixel, the screen display of FIG. 2C is obtained. 3 (c) is obtained.

In the above embodiment, the access control when data is read from the DRAM 1 is performed. However, when the image data from the image source (for example, the display device 3) is written into the DRAM 1, the above access control can be performed. , D
The data arrangement shown in FIG. 2C is obtained in the RAM 1. If this is read out from normal pixels, the original image arrangement will change.

The number of divided images arranged in the memory is not limited to four in the above embodiment. For example, as shown in FIG. 7A, if the most significant two bits of the RAS and CAS signals are used to specify the access start position, as shown in FIG. Scanning can be started from any arbitrary point of the 16 points of pixels 1 to 16, and the same effect can be obtained. In that case, the R preset register and the C preset register have a 2-bit configuration.

Such a change in the position of the divided screen can be used not only for image editing and the like but also for video games and the like.
For example, when a certain condition is satisfied, the scanning start address may be changed by a random number, or in a game played by a plurality of players, a player who obtains a certain condition may change the scanning start address. In this case, the image memory is not a DRAM but may be another random accessible memory or a ROM.

The present invention is not limited to the embodiments described above, and it is needless to say that various improvements and modifications can be made by those skilled in the art based on the above disclosure.

[0022]

According to the image data processing apparatus of the present invention,
The arrangement relationship of a plurality of divided images can be arbitrarily changed and displayed, or can be written to a memory, and a change can be given to the use form of the image data, which is convenient.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a display mode in which the arrangement of divided images that can be performed using an image data processing apparatus according to an embodiment of the present invention is changed.

FIG. 2 is a diagram showing an example of another display mode in which the arrangement of possible divided images is changed using the image data processing device according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a display mode in which the arrangement of possible divided images is changed using the image data processing device according to the embodiment of the present invention.

FIG. 4 is a block diagram of an image data processing device according to an embodiment of the present invention.

FIG. 5 is a diagram showing an example of an arrangement configuration of image data in a DRAM.

FIG. 6 is a diagram illustrating a configuration of a RAS signal and a CAS signal according to the embodiment of the present invention.

FIG. 7 shows the RAS signal and CA in another embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an S signal and an example of arrangement of divided image data.

[Explanation of symbols]

 Reference Signs List 1 DRAM 2 Address designating circuit 3 Display device 11 Address bus 12 Data bus 21 R address counter 22 C address counter 23 R preset register 24 C preset register

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 5/243 G06F 15/66 B

Claims (6)

[Claims] 1. An image data processing apparatus comprising: a memory device for storing digital image data of a predetermined number of pixels; and an address designating device for accessing an image data storage area of the memory device. An address generation unit for sequentially generating an address designating signal for designating an address to be accessed in the data storage area of the image memory device according to a clock signal, and arbitrarily designating a start address of an access start in a part of the address designating signal Means for adding information to the image data processing apparatus. 2. The memory device according to claim 1, wherein the memory device is a random accessible memory device, and the address designating signal includes a RAS signal designating a row address of a pixel arranged on an image plane and a CAS signal designating a column address. And information specifying the start address of the access start is the RA
2. The image data processing device according to claim 1, wherein the image data processing device is added to at least one of the S signal and the CAS signal. 3. The method according to claim 2, wherein the address generation unit has a clock counter unit for generating an address specification signal, and starts counting from the head address specified by information specifying a head address of the access start. The image data processing device according to claim 2, wherein 4. The information for designating the start address of the access start comprises a predetermined number of bits, and the start address of the access start is the address of the start pixel of each divided image when the image plane is divided into a plurality of areas. 4. The image data processing device according to claim 3, wherein the image data processing device specifies the image data. 5. The DRAM according to claim 5, wherein said address designating means comprises:
5. The image data processing apparatus according to claim 4, wherein when reading image data from the external device and outputting the image data to an external display device, a read address from the DRAM is designated. 6. The DRAM according to claim 6, wherein said address designating means comprises:
5. The image data processing apparatus according to claim 4, wherein when writing digital image data supplied from the outside to the memory, a write address to the DRAM is specified.