JPH10190375A - Operationnal amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a through rate while phase allowance is kept to be constant with a small circuit scale by providing first and second diodes between the emitters of first and third transistors and between the emitters of second and fourth transistors with prescribed polarity. SOLUTION: The diode D1 inserted between the emitters of the transistors Q1 and Q3 so that an anode is connected to the transistor Q1 and the diode D2 inserted between the emitters of the transistors Q2 and Q4 so that the anode is connected to the transistor Q2 are provided. Since the transistors Q1 and Q2 are emitter follower-connected to the input transistors Q3 and Q4 of a differential amplifier circuit 1A in an initial stage, large current is supplied to the initial stage differential amplifier circuit 1A only when the input voltage difference of a positive phase input signal S and an opposite phase input signal SB is larger than threshold voltage. Thus, the through rate can considerably be increased while stability is kept to be constant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier, and more particularly to an operational amplifier having a high gain and a high slew rate.

[0002]

2. Description of the Related Art In recent years, demands for high-speed and high-stability operating characteristics have been increasing as market requirements along with the expansion of application fields of operational amplifier circuits. As is well known, a conventional general operational amplifier circuit composed of bipolar transistors includes a capacitor for phase compensation in a feedback circuit for setting a gain. Needs to be reduced or the operating current must be increased. However, any of these methods causes the above-mentioned feedback circuit to be unstable, and therefore, it has been difficult to realize a stable operational amplifier circuit having a high slew rate.

Referring to FIG. 5 which shows a circuit diagram of a general conventional first operational amplifier circuit shown in the prior art described in Japanese Patent Application Laid-Open No. Hei 6-112737, this conventional operational amplifier circuit has a positive phase and an inverted phase. A first-stage differential amplifier circuit 1 for amplifying a differential input signal composed of the signals S and SB, converting the signal into a single-phase signal VS, and outputting the signal;
A second-stage amplifier circuit 2 that amplifies the single-phase signal VS and outputs an amplified signal VA, and an output buffer 3 that receives the supply of the amplified signal VA, operates as a current buffer of the amplifier circuit 2, and outputs the output signal VO. Prepare.

The differential amplifier 1 has a constant current I.sub.1 from a constant current source CS1 whose emitter is commonly connected and connected to a power supply VCC.
0 is supplied to each base and the positive and negative phase input terminals T
P, PNP type transistors Q3 and S3 connected to S and TSB to receive input signals S and SB, respectively.
Q4, an NPN transistor Q5 whose emitter is grounded and the base and collector are connected in common and the common connection point is connected to the collector of transistor Q3; and the emitter is grounded, the base is connected to the base of transistor Q6 and the collector is connected to transistor Q4. NPN connected to each collector
Transistor Q6.

The amplifier circuit 2 includes a phase compensation capacitor C inserted between an input terminal and an output terminal for stable operation by applying feedback.
P is provided.

Next, the operation of the conventional operational amplifier circuit will be described with reference to FIG.
Constitutes a differential amplifier circuit, and the transistors Q5 and Q6 are known current mirror circuits, and constitute active loads of the differential amplifier transistors Q3 and Q4. First, in a general operation, the transistors Q3 and Q4 differentially amplify in response to the supply of the input signals S and SB, and output a single-phase signal VS to the common connection point of the collectors of the transistors Q4 and Q6.

Next, the inverting input terminal T of this operational amplifier circuit
The slew rate of the output signal VO when the SB is connected to the output terminal TO and used as a voltage follower will be considered. The rate of change of the output signal VO, that is, the slew rate dVO / dt when a large amplitude step signal is supplied as the input signal S to the positive-phase input terminal TS is determined by the phase compensation of the current of the output signal VS of the first-stage differential amplifier circuit Capacity C
It is determined by the time for charging P, and is expressed by the following equation.

DvO / dt = I0 / cP where I0 is the current value of the constant current source CS1 and cP is the capacitance C
The capacitance value of P, vO, is the voltage of the output signal VO.

Conventionally, in order to increase the slew rate, a method has been adopted in which the constant current I0 is increased or the capacitance value cP of the compensation capacitance CP is set small.

[0010] However, this conventional operational amplifying circuit has I0
It is impossible to independently set the value of / cP and the phase margin representing the stability. That is, as described above, when the slew rate is set to be large, cP becomes small or I0 becomes large, and in any case, it becomes a factor of reducing the phase margin.

Referring to FIG. 3, which is a graph showing an example of the step response of the operational amplifier circuit, as shown in graph A, when the constant current I0 = 10 μA of the conventional operational amplifier circuit, the phase margin is sufficiently ensured but the through-hole is secured. The rate will be smaller. On the other hand, when the constant current I0 = 100 μA, the slew rate increases, but the phase margin decreases, so that the stability is lost and oscillation occurs as shown in graph B.

This problem has been improved by increasing the slew rate and maintaining the stability.
The conventional second operational amplifier circuit described in -112737,
A slew rate increasing circuit including two differential pairs each having a diode inserted into the emitter of one transistor and a current mirror circuit is inserted between the input terminal and the common emitter connection point of the first-stage differential amplifier circuit. is there. As a result, only when the differential input voltage exceeds a certain threshold,
A slew rate is increased by supplying a current to the first-stage differential amplifier circuit and charging a capacitor for phase compensation.

However, since two extra pairs of differential pairs and a current mirror circuit are required as described above, the circuit scale becomes large, and the current consumption also increases.

[0014]

In the above-mentioned first operational amplifier circuit, it is impossible to independently set the constant current value / capacitance value for phase compensation and the phase margin. If it is set to be large, there is a disadvantage that the phase margin becomes small, the stability is lost, and finally oscillation occurs.

The conventional second operational amplifier circuit with this improvement requires two extra pairs of differential pairs and a current mirror circuit in addition to the original amplifier circuit. There was a drawback that the current also increased.

It is an object of the present invention to provide an operational amplifier circuit having a small circuit scale and an increased slew rate while maintaining a constant phase margin.

[0017]

SUMMARY OF THE INVENTION An operational amplifier circuit according to the present invention has a differential circuit having first and second transistors each having an emitter connected in common and having the emitter common connection point connected to a first constant current source. An operational amplifier circuit comprising: an amplifier circuit; and an amplifier circuit having an input terminal connected to the collector of the second transistor and a capacitor for phase compensation connected between the input terminal and the output terminal. Has an emitter connected to the base of each of the first and second transistors, respectively connected to the second and third constant current sources, and a collector connected to the first power supply and connected to each base. Third and fourth transistors that operate as emitter followers upon receiving a complementary input signal;
A first diode inserted between the emitters of each of the third and third transistors with a polarity that conducts when the first transistor turns off, and the second diode between the emitters of each of the second and fourth transistors. And a second diode inserted with a polarity that conducts when the two transistors are turned off.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, referring to FIG. 1 which shows a first embodiment of the present invention in the same manner as FIG. The operational amplifier circuit of the present embodiment shown in FIG.
In place of the operational amplifier circuit 1 in addition to the output buffer 3 and the output buffer 3, each base has a positive phase and an inverted phase input terminals TS and TSB.
, And the emitters are supplied with constant currents I1 and I2 from constant current sources CS2 and CS3 connected to the power supply VCC, respectively. , SFB, PNP transistors Q1 and Q2 forming an emitter follower, a diode D1 inserted between the emitters of transistors Q1 and Q3 such that the anode is connected to transistor Q1, and transistors Q2 and Q4
And a diode D2 inserted between the respective emitters so that the anode is connected to the transistor Q2.

Next, the operation of the present embodiment will be described with reference to FIG. 1. Transistors Q1 and Q2 are respectively input transistors Q3 and Q3 of first stage differential amplifier circuit 1A.
Since Q4 is emitter-follower connected, the voltage difference SD between the positive-phase input signal S and the inverted-phase input signal SB is equal to the input transistors Q3, Q of the differential amplifier circuit 1A.
4 will be equal to the voltage difference between each base.

Next-stage amplifier circuit 2 for input voltage difference SD
2, which is a graph showing the relationship between the inflow current ID for operation of the differential amplifier circuit 1A corresponding to the single-phase signal VS supplied to the first and second phase signals VS. When the addition voltage is smaller than 1.2 V obtained by adding 0.6 V and the base-emitter voltage of each of the transistors Q3 and Q4 to about 0.6 V, the inflow current ID becomes the constant current I0. When the voltage difference SD between the signals S and SB exceeds 1.2 V, one of the diodes D1 and D2 conducts, and the inflow current ID becomes I0 + I1 or I0 + I depending on the conduction diode.
It becomes 2.

As in the conventional case, the slew rate of the output signal VO when the inverted input terminal TSB and the output terminal TO of the operational amplifier circuit of this embodiment are connected and used as a voltage follower will be considered. When a large-amplitude step signal is supplied as the input signal S to the positive-phase input terminal TS, the inflow current ID of the differential amplifier circuit 1A is large only during a large period in which the voltage difference between the input and output exceeds 1.2 V in the response waveform. When the output voltage VO reaches the target value and the voltage difference becomes I0 + I1 or I0 + I2 and the voltage difference becomes 1.2 V or less, the inflow current I
D returns to I0.

Referring to FIG. 3, which is a graph showing an example of the step response of the operational amplifier circuit. In the case of the conventional operational amplifier circuit, when I0 is 10 μA, as shown in graph A, the slew rate is low and I0 is 10 μA. When the frequency doubled to 100 μA, the phase margin was lost as shown in the graph B, and oscillation was not stabilized. In this embodiment, I0 is 10
When μA, I1 = I2 is set to 10I0, that is, 100 μA, as shown in the graph C, the slew rate is increased by a factor of 10 and the stability is such that the inflow current is 10 μA.
, Which is equivalent to the conventional low slew rate.

Next, a second embodiment of the present invention will be described with reference to FIG. 4, which is also shown in a circuit diagram with common reference characters / numerals added to components common to FIG. The difference from the above-described first embodiment lies in that instead of the differential amplifier circuit 1A, NPN transistors Q1A to Q4A and PNP transistors Q5A and Q6A are provided, and a diode D
1, a differential amplifier circuit 1B in which the polarity of the power supply of each transistor is inverted. The operation is the same as in the first embodiment.

[0024]

As described above, the operational amplifier circuit according to the present invention receives the supply of the complementary input signal to each base and operates as an emitter follower to constitute the first and second differential amplifier circuits. Third and fourth transistors to be supplied to the bases of the transistors, and the first and second transistors between the emitters of the first and third transistors and between the emitters of the third and fourth transistors. The first stage and the second stage of the operational amplifier are provided only when the input voltage difference between the positive-phase input signal and the inverted-phase input signal is larger than a certain threshold voltage because the first and second diodes are inserted with a polarity that conducts when shutting off. Since a large current is supplied to the differential amplifier circuit, there is an effect that the slew rate can be greatly increased while keeping the stability constant.

In addition, the addition of only two sets of emitter followers and two diodes has the effect of suppressing an increase in circuit scale current consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an operational amplifier circuit according to the present invention.

FIG. 2 is a characteristic diagram illustrating an example of an input voltage difference versus output current characteristic in the operational amplifier circuit according to the present embodiment.

FIG. 3 is a characteristic diagram showing an example of a slew rate characteristic in the operational amplifier circuit of the present embodiment in comparison with a conventional example.

FIG. 4 is a circuit diagram showing a second embodiment of the operational amplifier circuit according to the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional operational amplifier circuit.

[Explanation of symbols]

 1, 1A, 1B Differential amplifier circuit 2 Amplifier circuit 3 Output buffer Q1 to Q6, Q1A to Q6A Transistor D1, D2 Diode CS1, CS1, CS2 Constant current source CP Capacitance

Claims (3)

[Claims] 1. A differential amplifier circuit having first and second transistors having respective emitters connected in common and having a common emitter connection point connected to a first constant current source, and an input terminal connected to the second transistor. An operational amplifier connected to a collector of the differential amplifier and having an input terminal and an output terminal connected with a capacitor for phase compensation between the input terminal and the output terminal. And connected to the second and third constant current sources, respectively, and the respective collectors are connected to the first power supply. Each base receives a complementary input signal and is supplied as an emitter follower. A third and a fourth transistor operating and a third transistor inserted between the respective emitters of the first and third transistors with a polarity that conducts when the first transistor shuts off; Diode and said second and fourth transistors operational amplifier circuit each said second transistor between the emitter mutual is characterized in that it comprises a second diode which is inserted in polarity to conduct when the blocking. 2. The transistor of claim 1, wherein the first, second, third and fourth transistors are transistors of a first conductivity type, and a collector and a base are connected in common and an emitter is connected to a collector of the first transistor. The second connected respectively to the power supply of the first
A sixth transistor of a second conductivity type, a collector connected to the collector of the second transistor, a base connected to the base of the fifth transistor, and an emitter connected to the first power supply, respectively. The operational amplifier circuit according to claim 1, further comprising: 3. The transistor according to claim 1, wherein the first, second, third and fourth transistors are transistors of a second conductivity type.
2. The operational amplifier circuit according to claim 1, wherein said sixth transistor and said sixth transistor are first conductivity type transistors each having an emitter connected to said second power supply.