JPH1019984A - Semiconductor device test method and test apparatus - Google Patents

Abstract

(57) [Summary] A semiconductor device operating at a high speed operates at a low speed.
Provided are a test method and a test apparatus that can be reliably tested by an SI tester. A test signal is transferred to a device under test based on a first clock signal generated by an LSI tester. The processing operation of the test signal TD by the device under test 12 is performed by a multiplied clock signal HC obtained by multiplying the frequency of the clock signal CLK by the frequency multiplier 13.
This is performed based on LK. The signal processing result OUT is transferred to the LSI tester 11 based on the clock signal CLK. By comparing the test signal TD with the signal processing result OUT by the LSI tester 11, the device under test 12
Is operating normally.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor integrated circuit device. 2. Description of the Related Art In recent years, semiconductor integrated circuit devices have been increasingly scaled up and highly integrated, and the operating speed has been increased. The operation speed is increased by increasing the frequency of the clock signal. In such a semiconductor integrated circuit device, an operation test is performed using a test device before shipment, and it is necessary to surely and easily perform the operation test.

[0002]

2. Description of the Related Art FIG. 4 shows a test configuration for performing an operation test of a semiconductor integrated circuit device. The LSI tester 1 supplies a clock signal CLK to the device under test 2 for performing an operation test,
And test data TD for performing an operation test.

The device under test 2 is, for example, 100 MH
Z operates on the internal clock signal HCLK, while L
The SI tester 1 receives a clock signal CLK of about 50 MHz.
Can only supply. Then, the clock signal CLK is multiplied by the PLL circuit 3, and an internal clock signal HCLK of 100 MHz is generated and supplied to the device under test 2. The device under test 2 receives the internal clock signal HC.
It operates based on LK.

The device under test 2 operates based on the internal clock signal HCLK and the test data TD,
An output signal OUT is output to the LSI tester 1. The LSI tester 1 determines whether the device under test 2 is operating normally based on the test data TD output to the device under test 1 and the output signal OUT output from the device under test 1. .

[0005]

However, in the above test configuration, the clock signal CLK output from the LSI tester 1 and the test data TD are output as synchronization signals. It is difficult to synchronize the internal clock signal HCLK input to the device 2 with the test data TD.

Therefore, since the device under test 2 may not operate normally based on the internal clock signal HCLK and the test data TD, an operation test cannot be performed reliably.

The internal clock signal HCLK is connected to an LSI
When an attempt is made to directly output from the tester 1 to the device under test 2, the LS operating at the same speed as the device under test 2
Although an I tester 1 is required, it is becoming difficult to realize such an LSI tester 1.

An LSI tester 1 capable of operating at high speed
Is realized, crosstalk is likely to occur due to the impedance of the pattern of the test board on which the device under test 2 is set. Then, there is a problem that the operation test cannot be performed reliably due to the crosstalk.

Further, even if the internal clock signal HCLK output from the PLL circuit 3 is synchronized with the test data TD, the test data TD must be output after the operation of the PLL circuit 3 is stabilized. Therefore, there is a problem that it takes time to start the operation test.

An object of the present invention is to provide a test method and a test apparatus capable of reliably testing a semiconductor device operating at a high speed with an LSI tester operating at a low speed.

[0011]

FIG. 1 is a diagram for explaining the principle of claim 1 of the present invention. That is, a test signal is transferred to a device under test based on a first clock signal generated by an LSI tester, and the processing operation of the test signal by the device under test causes the frequency of the first clock signal to be multiplied by a frequency multiplier. Is performed based on the second clock signal multiplied by, and the signal processing result is transferred to the LSI tester based on the first clock signal, and the test signal and the signal processing result are compared by the LSI tester. Thus, it is determined whether the device under test is operating normally.

According to a second aspect of the present invention, a test signal output from the LSI tester is stored in a first storage device in a device under test based on a first clock signal generated by the LSI tester. The processing operation of the test signal stored in the storage device is a second clock signal CL obtained by multiplying the frequency of the first clock signal by a frequency multiplier.
K, which is performed in the device under test, is stored in a second storage device in the device under test, and the signal processing result stored in the second storage device is based on the first clock signal. The test signal is transferred to a tester, and the LSI tester compares the test signal with the signal processing result to determine whether the device under test is operating normally.

In the third aspect, the LSI tester transfers the first clock signal and a test data signal synchronized with the clock signal, and based on the signal transferred from the device under test and the test data signal. Perform an operation test on the device under test. The frequency multiplier generates a second clock signal obtained by multiplying the frequency of the clock signal. The switch circuit selects the first clock signal and outputs the first clock signal to the device under test during the signal transfer between the LSI tester and the device under test based on a control signal output from the LSI tester. During the signal processing operation of the device under test, the second clock signal is selected and output to the device under test. The device under test includes a first storage device in which the test data signal is stored based on the first clock signal when the test data is transferred from the LSI tester; and A CPU core for performing a signal processing operation based on a test data signal stored in the first storage device; and a second storage device for storing a signal processing result by the CPU core.

According to a fourth aspect, the frequency multiplier is a PLL.
The PLL circuit and the switch circuit are built in the device under test. In claim 5, the frequency multiplier is constituted by a PLL circuit, and the PLL circuit and the switch circuit are interposed between the device under test and a test apparatus.

According to the first aspect, a test signal is transferred to the device under test based on the first clock signal generated by the LSI tester, and the signal processing operation of the device under test by the test signal is performed in the second mode. This is performed based on a clock signal. The signal processing result is transferred to an LSI tester based on the first clock signal, and it is determined based on the signal processing result and the test signal whether the device under test is operating normally.

According to the second and third aspects, the test signal output from the LSI tester is stored in the first storage device in the device under test based on the first clock signal generated by the LSI tester. The processing operation of the test signal stored in the first storage device is performed in the device under test based on the second clock signal, and is stored in the second storage device in the device under test. A signal processing result is transferred to the LSI tester based on the first clock signal,
The LSI tester compares the test signal with the signal processing result to determine whether the device under test is operating normally.

In the present invention, the first clock signal output from the LSI tester is multiplied by a PLL circuit built in the device under test to generate a second clock signal, and the second clock signal is generated. And the first clock signal are output to the CPU core via the switch circuit.

According to the fifth aspect, the first clock signal output from the LSI tester is multiplied by a PLL circuit interposed between the device under test and the LSI tester to generate a second clock signal. One of the second clock signal and the first clock signal is output to the CPU core via the switch circuit.

[0019]

FIG. 1 shows an embodiment of a semiconductor device test apparatus embodying the present invention. The LSI tester 11 supplies a clock signal CLK to the device under test 12 for performing an operation test, test data TD for performing an operation test, and a control signal C for controlling the switch circuit 14.
Output S.

The device under test 12 operates with an internal clock signal HCLK of 100 MHz, while an LSI
The tester 11 can supply only a clock signal CLK of about 50 MHz. Then, the clock signal CLK becomes P
The frequency is multiplied by the LL circuit 13 to generate a multiplied clock signal HCLK of 100 MHz.
LK is output to the switching terminal B of the switch circuit 14.

The clock signal CLK is input to a switching terminal A of the switch circuit 14. The switch circuit 14 selects one of the signals input to the terminals A and B based on the control signal CS and outputs the selected signal to the device under test 12. Therefore, the switching circuit 14
Are the internal clock signal HCLK and the clock signal CLK
And outputs it to the device under test 12.

The device under test 12 operates based on either the clock signal CLK or the multiplied clock signal HCLK. The device under test 12 operates based on the multiplied clock signal HCLK and the test data TD, and outputs an output signal OUT to the LSI tester 11. The LSI tester 11 compares the test data TD output to the device under test 12 with the device under test 1
2 to determine whether the device under test 12 is operating normally based on the output signal OUT output from the device 2.

FIG. 3 shows a specific configuration of the device under test 12. The device under test 12 has the PLL circuit 13 and the switch circuit 14 formed on the same chip. The device under test 12 shown in FIG. 1 has a configuration in which the PLL circuit 13 and the switch circuit 14 are omitted from this configuration. Becomes

The input / output unit 16 and the peripheral circuit 17 are connected to the LSI tester 11 via an external bus 15 and receive the test data TD and output the output signal OUT.

The input / output unit 16 and the peripheral circuit 17 are connected to a CPU core 19 via an internal bus 18. Also,
The CPU core 19 is connected to the data RAM 20 and the program RAM 21 via the internal bus 18.

The data RAM 20 and the program RAM 21 are controlled by the CPU core 19. The CPU core 19 includes the switch circuit 1.
4, either the clock signal CLK or the multiplied clock signal HCLK is input.

Next, the operation of the test apparatus configured as described above will be described with reference to FIG. When the operation test is started, the switch circuit 14 is switched to the terminal A based on the control signal CS output from the LSI tester 11. Then, the clock signal CLK output from the LSI tester 11 is input to the device under test 12.

Next, test data TD is input from the LSI tester 11 to the device under test 12. The test data TD is composed of a program for performing an operation test of the device under test 12 and command data composed of test data, and includes an input / output unit 16 and the clock signal CLK.
Is stored in the program RAM 21 by the CPU core 19 operating based on the program (step 1).

When the storage of the instruction data is completed, the LSI tester 11 outputs a control signal CS to the switch circuit 14, and the switch circuit 14 switches to the terminal B based on the control signal CS.

Then, the multiplied clock signal HCLK output from the PLL circuit 13 is supplied to the CPU core 19. At this time, the PLL circuit 13 already has the clock signal CL
Since the multiplied clock signal HCLK is stably output based on K, the multiplied clock signal HCLK is instantaneously supplied to the CPU core 19 based on the switching of the switch circuit 14.

Then, the CPU core 19 executes the instruction based on the stored instruction (step 2). At this time, the CPU core 19 operates at high speed based on the multiplied clock signal HCLK.

Next, the CPU core 19 stores the execution result of the instruction in the data RAM 20 (step 3). Also at this time, the CPU core 19 operates at high speed based on the multiplied clock signal HCLK.

When the execution of the instruction is completed in this way (step 4), the switch circuit 14 is switched to the terminal A by the LSI tester 11, and the clock signal CLK is supplied to the CPU core 19.

Next, the CPU core 19 stores the data RAM 2
The data stored in 0 is read out and output to the LSI tester 11 as an output signal OUT (step 5). LS
The I tester 11 compares the test data TD output to the device under test 12 with the output signal OUT output from the device under test 12 to determine whether the device under test 12 is operating normally. (Step 6).

With the test apparatus configured as described above, the following operational effects can be obtained. (A) When the test data TD is input from the LSI tester 11 to the device under test 12, the clock signal CLK
, It is easy to synchronize the test data TD with the clock signal CLK. (B) When the device under test 12 performs an instruction execution operation based on the instruction stored in the program RAM 21, the multiplied clock signal HCLK generated by the PLL circuit is used.
, The device under test 12 can be operated at high speed. (C) Output signal O which is the operation result of device under test 12
The UT is reliably input to the LSI tester 11 based on the clock signal CLK. (D) By comparing the test data TD with the output signal OUT output from the device under test 12, LS
Device under test 12 that operates faster than I tester 11
Can be reliably tested. (E) When the internal clock signal HCLK is supplied from the PLL circuit 13 to the device under test 12, since the multiplied clock signal HCLK is already stable, the operation test time is long due to the time required for stabilizing the operation of the PLL circuit 13. It will not be.

[0036]

As described above in detail, the present invention can provide a test method and a test apparatus which can reliably test a semiconductor device operating at a high speed with an LSI tester operating at a low speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment.

FIG. 2 is a flowchart illustrating an operation of the embodiment.

FIG. 3 is a block diagram showing a device under test incorporating a PLL circuit.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 11 LSI tester 12 Device under test 13 Frequency multiplier (PLL circuit) CLK First clock signal HCLK Second clock signal TD Test signal (test data) OUT Signal processing result (output signal)

Claims (5)

[Claims] 1. A test signal is transferred to a device under test based on a first clock signal generated by an LSI tester, and a signal processing operation based on the test signal by the device under test is performed by the first clock signal. Is performed based on a second clock signal obtained by multiplying the frequency by a frequency multiplier, a signal processing result is transferred to the LSI tester based on the first clock signal, and the test signal and the signal processing are performed by the LSI tester. A method for testing a semiconductor device, comprising: determining whether the device under test is operating normally by comparing the result with a result. 2. A test signal output from the LSI tester is stored in a first storage device in a device under test based on a first clock signal generated by the LSI tester, and the first storage device Performing a signal processing operation based on the test signal stored in the device under test based on a second clock signal obtained by multiplying the frequency of the first clock signal by a frequency multiplier. The signal processing result stored in the second storage device is transferred to the LSI tester based on the first clock signal, and the test signal and the signal processing result are stored in the LSI tester. By comparing
A method for testing a semiconductor device, comprising: determining whether the device under test is operating normally. 3. A first clock signal and a test signal synchronized with the clock signal are transferred, and an operation test of the device under test is performed based on an output signal transferred from the device under test and the test signal. An LSI tester; a frequency multiplier that generates a second clock signal obtained by multiplying the frequency of the first clock signal; and an LSI tester and the device under test based on a control signal output from the LSI tester. During the signal transfer during, the first clock signal is selected and output to the device under test, and during the signal processing operation on the device under test, the second clock signal is selected and the device under test is selected. A switch circuit for outputting to the device; and the device under test, when the test signal is transferred from the LSI tester, CP for performing signal processing operation by the first storage device and the second test signal stored in said first storage device based on the clock signal to which the test signals are stored on the basis of the clock signal
A test apparatus for a semiconductor device, comprising: a U core; and a second storage device for storing a signal processing result by the CPU core. 4. The test apparatus for a semiconductor device according to claim 3, wherein said frequency multiplier comprises a PLL circuit, and said PLL circuit and said switch circuit are built in said device under test. 5. The semiconductor device according to claim 3, wherein said frequency multiplier comprises a PLL circuit, and said PLL circuit and said switch circuit are interposed between said device under test and a test apparatus. Testing equipment.