JPH10199994A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a method of manufacturing a semiconductor device in which the number of masks is reduced, the number of times of resist patterning is reduced, and the throughput is improved. In a step of forming a power supply voltage driving transistor on a semiconductor substrate, a first resist film having an opening in an N-channel Vcc transistor forming region is formed using a first mask, and an N-channel Vcc transistor is formed. Pw for ion-implanting a P-type impurity into region 9
cell 11, a second gate oxide film 8 removing step on the N-channel Vcc transistor formation region 9, a second resist film 13 having an opening in the P-channel Vcc transistor formation region 12 using a second mask, N-well 14 for ion-implanting N-type impurities into Vcc transistor formation region 12, P-channel Vcc
And a step of removing the second gate oxide film 8 on the transistor formation region 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a step of forming N and P channel transistors for driving a power supply voltage by ion implantation.

[0002]

2. Description of the Related Art Conventionally, in a process of forming N- and P-channel transistors for driving a power supply voltage in an EPROM or an EEPROM which is an example of a nonvolatile memory device in a semiconductor device, a P-type impurity such as boron is ion-implanted into
-well forming step and N such as phosphorus or arsenic
There are a step of forming an N-well by ion-implanting a type impurity, and a step of removing a gate oxide film by opening an N and P channel transistor formation region for driving a power supply voltage. In each of these steps, a dedicated mask is prepared, and at least three masks are required. Hereinafter, the manufacturing process of the EEPROM will be described with reference to FIGS.
This will be described with reference to FIGS.

First, as shown in FIG. 3A, a plurality of LOCOSs 2 for element isolation are formed on a semiconductor substrate 1 by a thermal oxidation method.

[0004] Next, as shown in FIG. 3B, a first gate oxide film 3 for a memory is formed on the semiconductor substrate 1 by a pyrogenic method.

Next, although not shown, a polysilicon film is formed on the entire surface of the LOCOS 2 and the first gate oxide film 3 and then resist patterning is performed, and as shown in FIG. Then, a polysilicon film 5 serving as a floating gate is formed. An intermediate insulating film is formed on the polysilicon film 5 and is formed of SiO ₂ / Si ₃ N ₄ / Si
An ONO film 6 made of O ₂ is formed.

Next, as shown in FIG. 3D, a resist film 7 for protecting the memory formation region is formed in the memory formation region 4, and the first resist film 7 outside the formation of the resist film 7 for protecting the memory formation region is formed. The gate oxide film 3 is removed.

[0007] Next, as shown in FIG.
After forming the second gate oxide film 8 by the organic oxidation method, the resist film 7 for protecting the memory formation region is removed.

Next, as shown in FIG. 4A, a first resist film 10 having an opening in an N-channel Vcc transistor forming region 9 of a power supply voltage driving transistor is formed. It is referred to as one mask. Then, the opening N of the first resist film 10 is
In the channel Vcc transistor formation region 9, boron as a P-type impurity is ion-implanted from the direction of the arrow in the figure to form a P-well 11, and then the first resist film 1 is formed.
Remove 0.

Next, as shown in FIG. 4B, a second resist film 13 having an opening in the P-channel Vcc transistor forming region 12 of the power supply voltage driving transistor is formed. It is referred to as a second mask. Then, ions of phosphorus or arsenic, which are N-type impurities, are implanted into the opened P-channel Vcc transistor forming region 12 of the second resist film 13 from the direction of the arrow in FIG. The resist film 13 is removed.

Next, as shown in FIG. 4C, a third resist film 15 having an opening in the N-channel Vcc transistor formation region 9 and the P-channel Vcc transistor formation region 12 is formed. Is referred to as a third mask. The N-channel Vcc transistor forming region 9 and the P-channel Vc
After removing the second gate oxide film 8 on the c-transistor formation region 12, the third resist film 15 is removed.

Next, as shown in FIG.
The third gate oxide film 16 is formed by an organic oxidation method.
The N-channel Vcc transistor forming region 9 and the P-channel Vcc transistor forming region 12 and the N-channel Vpp transistor forming region 17 and the P-channel Vpp transistor forming region 18 of the high voltage driving transistor are formed.

Next, as shown in FIG. 4E, a memory formation region 4, an N-channel Vcc transistor formation region 9, a P-channel Vcc transistor formation region 12, and N
By forming a polycide film 19 serving as a gate electrode in each of the channel Vpp transistor forming region 17 and the P channel Vpp transistor forming region 18, the P channel Vcc of the memory and power supply voltage driving transistors is formed.
Transistors and N-channel Vcc transistors,
The formation of the N-channel Vpp transistor and the P-channel Vpp transistor of the high voltage driving transistor is completed. Although not shown below, a desired semiconductor device is completed through the steps of forming an interlayer insulating film, forming a contact hole, forming an aluminum electrode in the contact hole, forming an overcoat film, and opening a pad. I do.

In the above steps, the first mask is used in the formation of the first resist film 10 and the formation of the P-well 11 in the N-channel Vcc transistor formation region 9, and the formation of the second resist film 13 and the formation of the P-well 11 are performed. N-well in channel Vcc transistor formation region 12
In the step of forming 114, the second resist is used and the second gate oxide film 8 on the N-channel Vcc transistor formation region 9 and the P-channel Vcc transistor formation region 12 is removed using the second mask. In the process, a third mask is used. That is, at least three masks are required in these manufacturing steps, and in order to improve the throughput in the manufacturing steps of the semiconductor device, it is necessary to reduce the number of masks and reduce the number of times of resist patterning. I have.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device in which the number of masks is reduced and the number of times of resist patterning is reduced in the process of manufacturing the semiconductor device, thereby improving the throughput.

[0015]

In order to solve the above-mentioned problems, in a method of manufacturing a semiconductor device according to the present invention, in a step of forming a power supply voltage driving transistor on a semiconductor substrate, a first mask is used by using a first mask. A first resist film having an opening in a channel transistor formation region is formed, and a P-type impurity such as boron is ion-implanted into an N-channel transistor formation region in which the first resist film has an opening to form a P-weld.
forming a gate oxide film on the N-channel transistor formation region, forming a second resist film having an opening in the P-channel transistor formation region by using a second mask; Forming an N-well by ion-implanting an N-type impurity such as phosphorus or arsenic into the P-channel transistor formation region where the resist film is opened, and then removing the gate oxide film on the P-channel transistor formation region. It is characterized by the following.

An effect of the above-described means is that the step of forming the N- and P-channel transistors of the power supply voltage driving transistor which conventionally required three masks can be performed with two masks. By reducing the number of resist patterns and the number of times of resist patterning, the throughput in the semiconductor device manufacturing process can be improved.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION E in the embodiment of the present invention
In the manufacturing process of the EPROM, a conventional technique is used as shown in FIG.
The description is omitted because it is the same as the case described with reference to (a) to (e), and the subsequent steps are schematic cross sections shown in FIGS. 1 (a) to 1 (d) and 2 (a) to 2 (c). This will be described with reference to the drawings. Note that components having the same structure as that of the conventional technology in the drawings are denoted by the same reference numerals.

Formation of LOCOS 2 for element isolation, formation of first gate oxide film 3, polysilicon film 5 and ONO film 6 in memory formation region 4, and second gate oxidation in other portions than memory formation region 4 After forming the film 8, FIG.
As shown in FIG. 4A, a first resist film 10 having an opening formed in an N-channel Vcc transistor forming region 9 of a power supply voltage driving transistor is formed. ) Will be referred to as a first mask similarly to the case described with reference to FIG. Then, P-well 11 is formed by ion-implanting boron, which is a P-type impurity, into the N-channel Vcc transistor forming region 9 in the opening of the first resist film 10 from the direction of the arrow in FIG. Further, as shown in FIG. 1B, after removing the second gate oxide film 8 on the N-channel Vcc transistor formation region 9, the first resist film 10 is removed.

Next, a second resist film 13 having an opening in the P-channel Vcc transistor forming region 12 of the power supply voltage driving transistor is formed. The mask used at this time is shown in FIG. The second mask will be referred to as in the case described above. Then, phosphorus or arsenic, which is an N-type impurity, is ion-implanted into the opened P-channel Vcc transistor forming region 12 of the second resist film 13 from the direction of the arrow in FIG.
Form 114. Further, as shown in FIG. 1D, after the second gate oxide film 8 on the P-channel Vcc transistor forming region 12 is removed, as shown in FIG. The film 13 is removed.

Next, as shown in FIG.
The third gate oxide film 16 is formed by an organic oxidation method.
It is formed on the N-channel Vcc transistor formation region 9 and the P-channel Vcc transistor formation region 12, and on the N-channel Vpp transistor formation region 17 and the P-channel Vpp transistor formation region 18 of the high voltage driving transistor.

Next, as shown in FIG. 2C, a memory formation region 4, an N-channel Vcc transistor formation region 9, a P-channel Vcc transistor formation region 12, and N
By forming a polycide film 19 serving as a gate electrode in each of the channel Vpp transistor forming region 17 and the P channel Vpp transistor forming region 18, the P channel Vcc of the memory and power supply voltage driving transistors is formed.
Transistors and N-channel Vcc transistors,
The formation of the N-channel Vpp transistor and the P-channel Vpp transistor of the high voltage driving transistor is completed. Although not shown below, a desired semiconductor device is completed through the steps of forming an interlayer insulating film, forming a contact hole, forming an aluminum electrode in the contact hole, forming an overcoat film, and opening a pad. I do. That is, according to the present invention, the N-channel Vcc transistor forming region 9 and the P-channel V
The third mask used in the step of forming the third resist film 15 in which the cc transistor formation region 12 is opened can be omitted.

[0022]

According to the method of manufacturing a semiconductor device of the present invention, the number of masks in the step of forming the P and N channel transistors of the power supply voltage driving transistor can be reduced to two, one less than the conventional one, and the resist patterning can be performed. The number of times can be reduced. Therefore, it is possible to improve the throughput in the manufacturing process of the semiconductor device.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, and FIGS.
(D) is a schematic sectional view explaining a manufacturing process of an EEPROM which is an example of a semiconductor device.

FIG. 2 shows an embodiment of the present invention, and (a) to (b) of FIG.
FIG. 2C is a schematic sectional view for explaining the manufacturing process of the EEPROM, following FIG. 1;

FIGS. 3A to 3E are schematic cross-sectional views illustrating a conventional example and explaining a manufacturing process of an EEPROM as an example of a semiconductor device.

4 (a) to 4 (e) are schematic cross-sectional views illustrating a conventional example and explaining the manufacturing process of the EEPROM following FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... LOCOS, 3 ... First gate oxide, 4 ... Memory formation area, 5 ... Polysilicon film, 6 ...
ONO film, 7 ... resist film for protecting memory formation region, 8 ...
2nd gate oxide film, 9 ... N channel Vcc transistor formation region, 10 ... first resist film, 11 ... Pw
well, 12 ... P-channel Vcc transistor forming region, 13 ... second resist film, 14 ... N-well, 1
5 ... third resist film, 16 ... third gate oxide film, 1
7 ... N-channel Vpp transistor formation region, 18 ...
P-channel Vpp transistor formation region, 19: polycide film

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 29/792

Claims (2)

[Claims] In the step of forming a power supply voltage driving transistor on a semiconductor substrate, a first resist film having an opening in an N-channel transistor formation region of the power supply voltage driving transistor is formed using a first mask. Ion-implanting a P-type impurity into the N-channel transistor forming region where the first resist film is opened to form P-w
removing the gate oxide film on the N-channel transistor formation region after forming the cell, and using the second mask to open the P-channel transistor formation region of the power supply voltage driving transistor in the second resist. A film is formed, and an N-type impurity is ion-implanted into the P-channel transistor forming region where the second resist film is opened, and N-w
removing the gate oxide film on the P-channel transistor formation region after forming the cell. 2. The method according to claim 1, wherein the P-type impurity is boron, and the N-type impurity is one of phosphorus and arsenic.