JPH10200068A - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: Provided are a stacked capacitor using a high dielectric film or a ferroelectric film, a semiconductor memory device having a highly reliable low resistance wiring, and a method of manufacturing the same. A copper wiring having excellent heat resistance is formed above a word line and a bit line and below a multilayer capacitor, and the capacitor is arranged at the uppermost part. This makes it possible to perform annealing at 450 ° C. or higher after forming the wiring,
As the dielectric constant of the capacitor insulating film is increased, no step is generated and the reliability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a stacked capacitance type semiconductor memory device which is advantageous for high integration and to form such a semiconductor memory device easily and with high precision. The present invention relates to a method of manufacturing a semiconductor memory device that can be used.

[0002]

2. Description of the Related Art In recent years, in order to realize a higher density of a semiconductor memory device, a capacitor storage section is formed above a switching transistor to reduce a plane area of a memory cell and to increase an element density. Have been done. However, as the area of the memory cell is reduced, the plane area of the capacitor is also significantly reduced, so that even with the use of these three-dimensional cells, it is difficult to secure the storage capacity required for memory operation. It has become to.

FIG. 6 shows a cross-sectional structure of a conventional stacked capacitance type memory cell called a crown type. A memory cell having this structure is described in, for example, JP-A-62-48062 and JP-A-62-128168. The feature of this structure is that the storage electrode 14 is formed above the word line 4 and the bit line 9, and the storage electrode 14 is formed in a cylindrical shape, and a capacitor is formed using not only the inner wall but also the outer wall. As a result, the area of the capacitor is significantly increased as compared with the memory cell having the conventional structure.

Although the storage capacity has been increased by using the stacked capacitor cell having such a structure, the increase is still insufficient, and it is becoming difficult to secure the required storage capacity as described above. Moreover, the formation of the crown type cell shown in FIG. 6 requires extremely complicated steps as described below. That is, a thick insulating film 18 is formed on the substrate surface on which the word lines 4 and the bit lines 9 are formed, a hole is formed in the thick insulating film 18, and then the storage electrode 14 is formed in the hole. The insulating film 18 must be removed to expose the inner and outer walls of the storage electrode 18, and the capacitor insulating film 15 and the plate electrode 16 must be formed thereon. In FIG. 6, reference numeral 20 denotes a silicon substrate, 1 denotes a field oxide film, 2 denotes a gate oxide film,
Is a polycrystalline silicon film, 4 is a tungsten film, 5 is a silicon nitride film, 6 is a BPSG film, 7 is a tungsten plug,
Reference numeral 9 denotes a bit line, 10 denotes a titanium nitride film, and 11 denotes a Cu wiring. 1 to 4 and 6,
In order to simplify the drawing and facilitate understanding, parts not directly related to the present invention, such as the source and drain of a MOS transistor, are omitted from the drawing.

In order to avoid such a complicated process, the shape of the memory cell is simplified by changing the shape of the electrode from a crown type to a simple stacked type, and a high dielectric constant film such as Ta ₂ O ₅ , BST, PZT or the like is used. It is actively being studied to secure the required capacity by using a computer.

[0006]

However, when a simplified stacked capacitor cell is formed by using the high dielectric constant film, a wiring forming step performed after the cell is formed,
The annealing process performed at a temperature of about 400 to 450 ° C. in an H ₂ atmosphere causes a problem that the leak current characteristic of the high dielectric constant film is deteriorated. This can be caused by
This is considered to be because the amount of oxygen and the state of chemical bonding in the high-dielectric-constant film are changed by the above-described wiring formation and the annealing process in the H ₂ atmosphere.

Therefore, when a high dielectric constant film is used as a capacitor insulating film, it is desirable to form a stacked capacitor cell after a wiring step, an annealing step, or the like. However, when these high dielectric constant films are used, it is necessary to perform annealing at 450 ° C. or more in an oxidizing atmosphere in order to sufficiently increase the dielectric constant. In this case, if a commonly used Al wiring is used as the wiring, a failure such as stress migration occurs due to annealing at 450 ° C. or more and disconnection occurs. Therefore, it is difficult to form a high dielectric constant film after forming the Al wiring. Not preferred.

As described above, conventionally, it has been extremely difficult to form a highly reliable stacked capacitor cell using a high dielectric constant film after forming an Al wiring.

In a conventional semiconductor memory device,
There is a large step at the boundary between the memory cell area and the peripheral circuit area. Therefore, the wiring for connecting the memory cell area and the peripheral circuit area to each other may be broken due to the step, and high reliability is obtained. There was a problem that can not be. In addition, there is a problem that a sufficient resolution cannot be obtained because the depth of focus of lithography becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a highly reliable semiconductor memory having a capacitor insulating film made of a high dielectric film, having a sufficiently large capacity, and no risk of disconnection of wiring. It is an object of the present invention to provide an apparatus and a method for manufacturing the same.

Another object of the present invention is to provide a semiconductor memory device having high reliability without a large step at the boundary between the memory cell region and the peripheral circuit region, and a method of manufacturing the same.

[0012]

According to another aspect of the present invention, there is provided a semiconductor memory device having a memory cell region and a peripheral circuit region, wherein a switching MOS transistor formed in the memory cell region is provided. A capacitor for storing information formed above the switching MOS transistor via a plurality of insulating films laminated on the main surface of the semiconductor substrate; and a capacitor for selecting the switching MOS transistor. A word line, a bit line for supplying electric charge to the capacitor, and at least one layer of copper wiring formed below the capacitor and above the word line and the bit line.

That is, according to the present invention, since copper is used as the wiring, reliability against stress migration is improved, and a wiring with low resistance is realized. Moreover, since the capacitor is formed above the copper wiring and the capacitor insulating film made of a high dielectric constant film or a ferroelectric film can be heat-treated at a sufficiently high temperature, a stacked capacitance cell having a sufficiently large capacitance is formed. You.

Further, since the capacitor is formed on the plurality of wiring layers, a step caused by the capacitor does not occur at the boundary between the memory cell region and the peripheral circuit region. A highly reliable semiconductor memory device in which wiring connecting circuit regions to each other is not broken can be obtained.

Since the adhesion improving films are formed on the upper surface and the lower surface of the copper wiring, the risk of peeling of the copper wiring is significantly reduced, and the reliability is improved. As the adhesion improving film, a film selected from the group consisting of a titanium nitride film, a titanium film, a metal film containing titanium, and a nitride film of a transition metal can be used.

The lower electrode of the capacitor can be easily electrically connected to the high-concentration impurity diffusion region of the MOS transistor via a conductive plug formed through the copper wiring and the insulating film. .

As the capacitor insulating film of the capacitor, a dielectric film or a ferroelectric film can be used, and as the high dielectric constant film, a Ta ₂ O ₅ film or a BST
A PZT film can be used as the film and the ferroelectric film, respectively.

As the lower electrode and the upper electrode of the capacitor, a Pt film, a Ru film or a RuO ₂ film can be used, and the copper wiring mainly contains copper.
An alloy to which at least one of Ti, Ni, Co and Al is added can be used.

A plurality of layers of wiring can be formed between the lower electrode of the capacitor and the switching MOS transistor. Of the plurality of layers of wiring, at least the lowermost wiring is an aluminum wiring, and the upper wiring is Can be a copper wiring. In this case, aluminum can be finely processed more easily than copper, so that an aluminum wiring having an extremely small line width can be formed under a copper wiring having a slightly larger line width.

In the present invention, since the capacitor is formed on the plurality of insulating films, no step is caused by the capacitor, and the plurality of insulating films extending from the memory cell region to the peripheral circuit region are not formed. Has been substantially flattened, and there is almost no risk of disconnection of the wiring formed thereon, so that the reliability has been significantly improved.

According to the semiconductor memory device of the present invention, a step of forming a plurality of MOS transistors in a predetermined region of a semiconductor substrate, a step of forming a first insulating film covering at least the MOS transistors, and a step of forming the first insulating film Forming a first conductive plug that penetrates through the gate electrode and is electrically connected to the high-concentration impurity diffusion region of the MOS transistor; and forming a copper wiring in contact with the upper end of the first conductive connection plug. Forming a second insulating film on the first insulating film to cover the copper wiring; and forming a second conductive plug penetrating through the second insulating film and in contact with the upper surface of the copper wiring. Forming, sequentially stacking a lower electrode of the capacitor electrically connected to the second conductive plug, a capacitor insulating film made of a ferroelectric film or a high dielectric film, and an upper electrode of the capacitor. A step of forming, 450 ° C. or higher, 6
It is formed by a method for manufacturing a semiconductor memory device, which comprises at least a step of heat treatment in an oxidizing atmosphere at a temperature of 00 ° C. or lower.

The above heat treatment can be performed by an electric furnace, laser annealing or lamp annealing. In particular, if laser annealing or lamp annealing is used, the required heat treatment can be performed in a very short time.

The first connection plug is formed after the upper surface of the first insulating film is flattened. The same applies to the second connection plug.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS On a switching MOS transistor formed in a memory cell region, a plurality of insulating films are formed by lamination, and a capacitor for storing information is formed thereon. A word line for selecting the switching MOS transistor and a bit line for supplying a charge to the capacitor are formed below the capacitor, and at least one layer is provided above the word line and the bit line and below the capacitor. Copper wiring is formed.

[0025] Therefore, high reliability for stress migration and low-resistance wiring are realized, and a capacitor insulating film made of a high dielectric constant film or a ferroelectric film can be heat-treated at a sufficiently high temperature. A stacked capacity cell having a sufficiently large capacity is formed.

Further, since the capacitor is not formed above the semiconductor substrate, below the wiring layer or the insulating film, there is no step caused by the capacitor, and there is no risk of disconnection of the wiring formed above the capacitor. .

If a titanium nitride film, a titanium film, a metal film containing titanium or a nitride film of a transition metal is formed on the upper and lower surfaces of the copper wiring as an adhesion improving film, respectively, the copper wiring may peel off. Is reduced and reliability is improved.

A plurality of the wiring layers are formed, and the capacitor insulating film is annealed by using laser annealing or lamp annealing. When annealing is performed using these means, since the annealing time is extremely short, the capacitor insulating film can be set to a predetermined temperature without excessively increasing the temperature of the underlying wiring. Therefore, only the lower wiring can be formed by the aluminum film, and the other wirings can be formed by the copper film. Since the aluminum film is easier to be finely processed by photoetching than the copper film, an aluminum wiring having a line width smaller than the copper wiring can be formed below the copper wiring.

The capacitor insulating film is made of Ta ₂ O ₅
A high dielectric constant film such as a film, a BST film or a PZT film, or a ferroelectric film can be used, and favorable characteristics can be obtained by annealing.

The lower electrode and the upper electrode of the capacitor may be a Pt film, a Ru film or a RuO ₂ film,
The copper wiring is mainly composed of copper, Ti, Ni, C
An alloy to which at least one of o and Al is added can be used, and sufficiently favorable results can be obtained.

[0031]

【Example】

<Embodiment 1> First, as shown in FIG.
A field oxide film 1 was formed on the substrate 0 by using a known selective thermal oxidation method. A gate oxide film 2, a P-doped polycrystalline silicon film 3, a tungsten film 4, and a silicon nitride film 5 are sequentially laminated and formed, and then processed into a predetermined shape using a well-known photolithography technique. An electrode was formed.

Next, ion implantation was performed using the gate electrode as a mask to form a diffusion layer. After forming the second silicon nitride film 5 ′ on the entire surface, a well-known etchback is performed to form a side spacer while leaving the silicon nitride film 5 ′ only on the side wall of the gate electrode, and the other portions are formed. Removed.

As shown in FIG. 2, BPSG (Boron Pho
After a sphor silicate glass) film 6 was formed and reflowed at 700 ° C., the surface of the BPSG film 6 was flattened by well-known chemical mechanical polishing (CMP). Next, a predetermined portion of the BPSG film 6 is selectively removed using well-known reactive ion etching to form a contact hole, and a well-known C
After forming a tungsten film on the entire surface using VD technology,
A well-known etch-back process was performed to leave the tungsten film only in the opening and remove the other portions to form a tungsten plug 7. In this example, a TiN / Ti laminated film formed by a sputtering method was interposed between the tungsten film and the BPSG film 6 as an adhesive layer.

After a BPSG film is further formed on the BPSG film 6 to increase the film thickness, a silicon nitride film 8 is formed, and a bit line contact hole reaching the surface of the semiconductor substrate 20 is formed. A bit line composed of a laminated film of the film 3 and the tungsten film 9 was formed.

As shown in FIG. 3, a first SiO 2 film is formed using a well-known plasma CVD method using TEOS as a raw material.
_After forming a _second film 6 ′ and forming a connection hole using the silicon nitride film 8 as an etching stopper, a second tungsten plug 7 ′ was formed in the same manner as the tungsten plug 7.

The second titanium nitride film 10, the Cu film 11, and the third titanium nitride film 10 'are sequentially laminated and formed into a predetermined shape by using a known photo-etching technique to form a first wiring. Was formed. Further, the second SiO ₂ is formed using a known plasma CVD method using TEOS as a raw material.
After forming the film 6 ″ and covering the first wiring, a connection hole and a third tungsten plug 7 ″ are similarly formed,
Further, the fourth titanium nitride film 10 ″ and the second Cu film 1
A second wiring composed of a laminated film of the 1 ′ and the fifth titanium nitride films 10 ′ ″ was formed on the second SiO ₂ film 6 ″.

Next, as shown in FIG.
_{The second} film 6 ′ ″ is formed by using a well-known plasma CVD method using TEOS as a raw material to cover the second wiring, and then processed in the same manner as described above to form a fourth tungsten plug 7 ′ ″. Was formed.

After a lower electrode 12 made of a Pt film is formed in a memory cell portion by using a well-known sputtering method, a BST film 13 is formed on the lower electrode 12 as a capacitor insulating film, and is heated at 450 ° C. in an oxidizing atmosphere. The dielectric constant of the BST film 13 was increased by annealing at 600 ° C. BS
In order to increase the dielectric constant of the T film or the PZT film, it is necessary to perform oxidation annealing at a temperature of 450 ° C. or higher. As the annealing temperature increases, the dielectric constant also increases.

FIG. 5 shows the dependence of the relative dielectric constant on the oxidation annealing temperature after annealing the BST film formed on the Pt electrode by sputtering in an oxygen atmosphere.
As is clear from FIG. 5, it was recognized that when the annealing temperature was 400 ° C. or higher, the relative dielectric constant sharply increased.

After the annealing, an upper electrode 19 made of a Pt film is formed by a known sputtering method, and a passivation film 20 made of a silicon nitride film is formed by a plasma CVD method. A semiconductor memory device is formed.

In the semiconductor memory device manufactured as described above, since the capacitor for storing electric charges is formed in the uppermost layer, process damage in the wiring step or the annealing step is not easily applied to the capacitor, and thus stable capacitor characteristics are obtained. I was able to. In addition, since the first and second wirings are formed from the Cu film, the above-described annealing does not cause disconnection or the like, and a highly reliable wiring was obtained.

In this embodiment, the annealing is performed using a normal electric furnace. However, the temperature may be effectively increased by short-time annealing using lamp annealing, laser annealing, or the like. Even if the oxidation annealing is performed at such a high temperature, as the wiring formed under the lower electrode 12 of the capacitor,
Since the Cu wirings 11 and 11 'are used, the wiring is not disconnected due to stress migration or the like, and the reliability of the wiring does not decrease.

If the annealing is performed at a temperature higher than 600 ° C., Cu may diffuse into the SiO ₂ films 6 ′ and 6 ″ and the dielectric strength may be deteriorated. However, in this embodiment, Ti
The N films 10 and 10 ′ are placed above and below the Cu film 11,
0 ″, 10 ′ ″ are formed above and below the Cu film 11 ′, respectively, and the SiO ₂ films 6 ′, 6 ″ and the Cu films 11, 11 ′ are formed.
Did not come into direct contact with each other, so that the dielectric breakdown voltage did not decrease due to the diffusion of Cu.

Further, a titanium nitride film may be interposed between the lower electrode 12 made of a Pt film and the SiO ₂ film 6 ″ ′ under the Pt film in order to improve the adhesiveness.

Instead of the titanium nitride film, a titanium-containing metal film such as a titanium film or a titanium tungsten film, or a transition metal nitride film such as a tungsten nitride film may be used.

Further, in addition to Cu, Ti, Ni,
Cu containing Co, Al or the like can also be used,
Thereby, the oxidation resistance of the Cu wiring can be improved. Further, as the lower electrode 12 and the upper electrode 19, Ru, Ir, an oxide thereof, or the like may be used instead of Pt.

In this embodiment, BST is used as the dielectric film.
Although a film is used, a ferroelectric film such as a PZT film or a high dielectric constant film such as Ta ₂ O ₅ can be used. The electrode shape is not limited to a flat plate shape, but it is also possible to use an electrode shape such as a fin or a crown.
The charge storage amount may be further increased.

In this embodiment, Cu wiring is used for all the wiring below the capacitor. However, if annealing is performed for a very short time by lamp annealing or laser annealing, the temperature of the wiring in the lower layer can be increased without excessively increasing the temperature. The capacitor insulating film can be annealed at a predetermined temperature. Therefore, heat treatment at an oxidation annealing temperature of about 450 ° C. to 600 ° C. for the capacitor insulating film was performed by extremely short-time annealing by lamp annealing or laser annealing, and the underlying wiring could be replaced with a normal Al wiring.

Although it is most preferable that the capacitor portion is formed in the uppermost layer as in the present embodiment, the capacitor is placed above the bit line and the word line even if it is not the uppermost layer, and the Cu wiring is arranged thereunder. Is useful in terms of reliability and low resistance.

Further, in this embodiment, the Cu wiring is formed by using normal dry etching. However, after forming a groove in the P-TEOS film and forming an adhesive layer such as a titanium nitride film in the groove, copper is formed. A copper wiring may be formed by a so-called damascene method in which copper is formed on the entire surface and copper outside the groove is removed by CMP to form a copper wiring.

[0051]

As is apparent from the above description, according to the present invention, stress migration resistance is improved, and
Annealing can be performed at a temperature of 0 ° C. or higher. In addition, Cu has a resistance about 1/2 that of Al, and W and T
Since the resistance is much lower than that of a high melting point metal such as iN, excellent heat resistance and low resistance are simultaneously realized. In addition, since a stacked capacitor using a high-dielectric-constant film or a ferroelectric-constant film is formed above the Cu wiring, it is possible to anneal at a temperature of 450 ° C. or more, and to obtain a capacitor insulating film having a high dielectric constant. Is obtained. In addition, since the wiring step and the annealing step can be reduced after the cell is formed, a highly reliable stacked capacitor cell can be easily formed. Further, since there is no step between the memory cell region and the peripheral circuit region, there is almost no possibility that the wiring connecting between the two regions will be disconnected, and the reliability is remarkably improved.

[Brief description of the drawings]

FIG. 1 is a process diagram showing a first embodiment of the present invention,

FIG. 2 is a process diagram showing a first embodiment of the present invention,

FIG. 3 is a process diagram showing a first embodiment of the present invention,

FIG. 4 is a process chart showing a first embodiment of the present invention,

FIG. 5 is a curve diagram showing a relationship between a dielectric constant of a BST film and an oxidation annealing temperature;

FIG. 6 is a cross-sectional view showing a conventional semiconductor memory device.

[Explanation of symbols]

1 ... field oxide film, 2 ... gate oxide film, 3 ...
Polycrystalline silicon film, 4 ...... tungsten film, 5 ...... silicon nitride film, 6 ...... BPSG film, 6 '...... SiO ₂ film,
7: tungsten plug, 8: silicon nitride film, 9
...... Tungsten bit line, 10 ... Titanium nitride film, 1
1 ... Cu wiring, 12 ... Pt electrode, 13 ... BST
Film 14 storage electrode 15 capacitor insulating film 1
6 ... upper electrode, 18 ... insulating film, 19 ... upper electrode,
20 silicon substrate.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masayoshi Saito 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd. Address: Central Research Laboratory, Hitachi, Ltd.

Claims (14)

[Claims] A switching MOS transistor having a memory cell region and a peripheral circuit region, the switching MOS transistor being formed in the memory cell region, and a plurality of insulating films formed by being stacked on a main surface of the semiconductor substrate. MO for switching
A capacitor formed above the S transistor for storing information, a word line for selecting the switching MOS transistor, a bit line for supplying a charge to the capacitor, and a bit line below the capacitor; And at least one layer of copper wiring formed above the word line and the bit line. 2. The semiconductor memory device according to claim 1, wherein an adhesion improving film is formed on each of an upper surface and a lower surface of said copper wiring. 3. The semiconductor memory device according to claim 2, wherein the adhesion improving film is selected from the group consisting of a titanium nitride film, a titanium film, a metal film containing titanium, and a nitride film of a transition metal. . 4. A lower electrode of the capacitor is electrically connected to a high-concentration impurity diffusion region of the MOS transistor via a conductive plug formed through the copper wiring and the insulating film. 2. The method according to claim 1, wherein
4. The semiconductor memory device according to any one of items 1 to 3. 5. The capacitor insulating film of the electric capacitor,
5. The semiconductor memory device according to claim 1, comprising a dielectric film or a ferroelectric film. 6. The high dielectric constant film is a Ta ₂ O ₅ film or BS.
6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is a T film, and the ferroelectric film is a PZT film. 7. The semiconductor memory device according to claim 1, wherein the lower electrode and the upper electrode of the capacitor are made of a Pt film, a Ru film, or a RuO ₂ film. 8. The copper wiring comprises copper as a main component, Ti, N
8. The semiconductor memory device according to claim 1, comprising an alloy to which at least one of i, Co, and Al is added. 9. The semiconductor memory device according to claim 1, wherein a plurality of wiring layers are formed between the lower electrode of the capacitor and the switching MOS transistor. 10. The semiconductor memory device according to claim 9, wherein at least the lowermost wiring of the plurality of wirings is an aluminum wiring and the upper wiring is a copper wiring. 11. The semiconductor device according to claim 1, wherein said plurality of insulating films extend from said memory cell region to said peripheral circuit region, and upper surfaces of said plurality of insulating films are substantially flat. The semiconductor memory device according to any one of the above. 12. A step of forming a plurality of MOS transistors in a predetermined region of a semiconductor substrate, a step of forming a first insulating film covering at least the MOS transistor, and a step of penetrating the first insulating film to form the MOS transistor. Forming a first conductive plug electrically connected to the high-concentration impurity diffusion region, forming a copper wiring in contact with an upper end of the first conductive connection plug, and forming a second insulating plug. Forming a film on the first insulating film to cover the copper wiring, forming a second conductive plug penetrating through the second insulating film and contacting the upper surface of the copper wiring; Forming a lower electrode of the capacitor electrically connected to the second conductive plug, a capacitor insulating film made of a ferroelectric film or a high-dielectric film, and an upper electrode of the capacitor in this order; Furthermore, a method of manufacturing a semiconductor memory device which comprises at least a step of heat treatment in an oxidizing atmosphere of 600 ° C. or less. 13. The method according to claim 12, wherein the heat treatment is performed by an electric furnace, laser annealing, or lamp annealing. 14. The method according to claim 12, wherein the first connection plug is formed after planarizing an upper surface of the first insulating film.