JPH10207434A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of reducing the generation of EMI without increasing the number of wires. SOLUTION: A controller IC8 is arranged in a source bus substrate 3, source bus drivers IC9 and 10 for driving a source bus are divided into two left and right groups, a line memory incorporated in the controller IC8 is divided into two corresponding to the two source bus drivers IC9 and 10, one line memory stores the former half data of a horizontal cycle, that is, left half data on a screen, the other line memory stores latter half data of the horizontal cycle, that is, right half data on the screen, and the controller IC8 outputs the data of the two line memories in parallel with each other to the source drivers 9 and 10 by a frequency 1/2 of an input frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for an active matrix type liquid crystal display device using thin film transistors (hereinafter, referred to as TFTs).

[0002]

2. Description of the Related Art FIG. 4 is a schematic diagram showing a conventional liquid crystal display device. In the figure, 1 is a liquid crystal display panel, 2 is a source driver IC for driving source wiring, and 3 is a source bus board on which a source driver IC 2 is mounted, and is arranged on one side of the outer peripheral portion of the liquid crystal display panel 1. Reference numeral 4 denotes a gate driver IC for driving the gate wiring, and reference numeral 5 denotes a gate bus substrate on which the gate driver IC 4 is mounted, which is arranged on one side of the outer peripheral portion of the liquid crystal display panel 1. Reference numeral 6 denotes a controller IC that receives an input signal and outputs a signal to the source driver IC 2 and the gate driver IC 4. Reference numeral 7 denotes a control board on which the controller IC 6 is mounted.

In a conventional liquid crystal display device having such a configuration, a clock input in parallel and n-bit data of each color of RGB (18 data in the case of 6 bits) are adjusted in timing by a controller IC6. Is performed to the source driver IC2,
When the frequency of the input signal increases, EMI (Elect
The problem of ro Magnetic Interference) was significant.

[0004]

The conventional active matrix type liquid crystal display device is configured as described above.
Since the source driver IC2 is driven without changing the input frequency, the EMI noise level is high and the FCC (Feed
ral Communications Commis
sion) or CISPR (Commit Inte)
rational Special des Per
turbines Radioelectric
It took a lot of time and effort to clear such standards as es.

[0005] The present invention has been made to solve the above-described problems, and has as its primary object to obtain a liquid crystal display device capable of reducing the occurrence of EMI. A second object of the present invention is to provide a liquid crystal display device that does not increase the number of wirings in reducing the occurrence of EMI.

[0006]

In the liquid crystal display device according to the present invention, a pixel portion having switching elements arranged in a matrix and an outer peripheral portion of the pixel portion are arranged on one side, and N groups (N is A plurality of drive circuits which are divided into two or more integers and respectively drive the corresponding first signal lines, and which are connected to each of the divided groups of the drive circuits and receive signals inputted from outside. A control circuit that divides the frequency by 1 / N and outputs the frequency to the drive circuit, wherein the control circuit is arranged on the same side of the outer periphery of the pixel portion on which the drive circuit is arranged, and connects the control circuit and the drive circuit. And the rest of the wiring are arranged on opposite sides of the control circuit. The control circuit has a memory for temporarily storing a signal input from the outside.

The memory of the control circuit is divided into N corresponding to the N groups of drive circuits, and a signal of one horizontal cycle is divided into N and stored. Further, for each divided drive circuit group, the control circuit converts the signal stored in the corresponding divided memory into 1 / N of the input frequency.
Output at the frequency of Further, the control circuit
The signals of one horizontal period are divided into N signals and sequentially written into the first to Nth memories divided according to the driving circuits of the group, and after the Nth writing, the divided driving circuit groups are , And the signals stored in the corresponding divided memories are read out in parallel at a frequency of 1 / N of the input frequency. N is 2. In addition, the control circuit is arranged at the center of the side where the driving circuit is arranged on the outer peripheral portion of the pixel portion.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a diagram showing an active matrix type liquid crystal display device according to an embodiment of the present invention. In the figure, 1, 3 to 5 are the same as those of the above-mentioned conventional device, and the description thereof is omitted. Reference numeral 8 denotes a controller IC similar to the above-described conventional device, but is arranged on the source bus board 3. Reference numerals 9 and 10 denote source driver ICs.
Divided into two groups.

FIG. 2 is a schematic configuration diagram showing a controller IC according to an embodiment of the present invention. In the figure, 1
Reference numerals 2 and 13 denote line memories built in the controller IC 8, and the line memory 12 stores data in the first half of the horizontal cycle, that is, data in the left half on the screen.
Reference numeral 3 stores data in the latter half of the horizontal cycle, that is, data in the right half on the screen. Reference numeral 14 denotes a timing controller that controls the timing of outputting the data stored in the line memories 12 and 13 to the source driver ICs 9 and 10, respectively.

FIG. 3 is a diagram showing input and output signal timings according to the embodiment of the present invention. In the liquid crystal display device configured as described above, an external signal is first input to the controller IC 8 as shown in FIG. 1, but here, first, as shown in FIG. Is separately written into a line memory 12 for storing the second half and a line memory 13 for storing the second half, and each is input to the timing controller 14 to adjust the timing. Signals read from the timing controller 14 are supplied to a source driver IC 9 for driving the first half of the horizontal line and a source driver IC 10 for driving the rear half of the horizontal line, respectively.
Then, the frequency is divided into に and distributed. Here, the signal is written to the line memory in the order of the line memory 12 and the line memory 13, and the signal is read in parallel from the line memory 12 and the line memory 13 after the writing to the line memory 13 is completed. I have. That is, 1
The screen is divided into left and right halves, and each is scanned independently. Therefore, as shown in FIG. 3, the frequency can be controlled at １ ／ of the originally required frequency. At this time, the number of output signals is twice as large as that of the conventional one, but by arranging the controller IC 8 at the center of the source bus board 3 as shown in FIG. Therefore, only the data frequency can be reduced to half.

[0011]

Since the present invention is configured as described above, it has the following effects. A pixel portion having switching elements arranged in a matrix and a first signal line arranged on one side of an outer peripheral portion of the pixel portion and divided into N groups (N is an integer of 2 or more) and A plurality of drive circuits that are individually driven; and a control circuit that is connected to each of the divided groups of the drive circuits and that divides an input frequency of an externally input signal by 1 / N and outputs the resultant to the drive circuit. The control circuit is disposed on the same side of the outer peripheral portion of the pixel portion where the drive circuit is disposed, and a part of a plurality of wirings connecting the control circuit and the drive circuit and a remaining part are opposite to each other across the control circuit. Side, so the output frequency from the control circuit to the drive circuit can be reduced to 1 / N of the input frequency while minimizing the increase in the number of wires connecting the control circuit and the drive circuit, thereby reducing electromagnetic interference. Let it be Can.

Further, since the control circuit has a memory for temporarily storing a signal input from the outside, the output frequency from the control circuit to the drive circuit can be easily reduced to one of the input frequencies.
/ N. The memory of the control circuit is
The signal is divided into N corresponding to the N groups of drive circuits, and a signal of one horizontal cycle is divided into N and stored, so that it is possible to output each divided memory. Further, the control circuit divides the signal of one horizontal cycle into N pieces and sequentially writes the divided signals into the N-th to N-th memories corresponding to the N groups of drive circuits, and simultaneously writes the N-th write signal. Since the signals stored in the corresponding divided memories are read out in parallel at a frequency of 1 / N of the input frequency for each of the divided drive circuit groups after the end, control is performed without reducing the processing speed of the control circuit. The output frequency from the circuit to the drive circuit can be reduced to 1 / N of the input frequency, and the electromagnetic interference can be reduced.

Since N is 2, there is no increase in the number of wires connecting the control circuit and the drive circuit. In addition, since the control circuit is arranged at the center of the side where the driving circuit on the outer periphery of the pixel portion is arranged, it is possible to minimize an increase in the number of wirings connecting the control circuit and the driving circuit.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 shows a controller I according to an embodiment of the present invention.
It is a schematic block diagram which shows C.

FIG. 3 is a diagram showing input and output signal timings according to the embodiment of the present invention.

FIG. 4 is a schematic configuration diagram showing a conventional liquid crystal display device.

[Explanation of symbols]

8 Controller IC, 9, 10 Source driver I
C, 12, 13 line memory.

Claims (7)

[Claims] 1. A pixel portion having switching elements arranged in a matrix at intersections of a plurality of first signal lines and a plurality of second signal lines, and N groups arranged on one side of an outer peripheral portion of the pixel portion (N is an integer of 2 or more) divided into a plurality of driving circuits for individually driving the corresponding first signal lines, and a signal which is connected to each divided group of the driving circuits and which is externally input. A control circuit that divides the input frequency of 1 / N into 1 / N and outputs the divided frequency to the drive circuit. The control circuit is disposed on the same side of the outer periphery of the pixel portion where the drive circuit is disposed. A liquid crystal display device, wherein a part of a plurality of wirings connecting a driving circuit and a remaining part are arranged on opposite sides of a control circuit. 2. The liquid crystal display device according to claim 1, wherein the control circuit has a memory for temporarily storing a signal input from the outside. 3. The memory of the control circuit is divided into N pieces corresponding to N groups of drive circuits, and a signal of one horizontal cycle is divided into N pieces.
3. The liquid crystal display device according to claim 2, wherein the liquid crystal display device is divided and stored. 4. The control circuit according to claim 3, wherein the control circuit outputs a signal stored in the corresponding divided memory at a frequency of 1 / N of the input frequency for each divided drive circuit group. Liquid crystal display. 5. The control circuit divides a signal of one horizontal cycle into N pieces and sequentially writes the divided signals into N pieces into first to Nth memories divided into N pieces corresponding to N groups of drive circuits. 3. The liquid crystal display device according to claim 2, wherein the signals stored in the corresponding divided memories are read out in parallel at a frequency of 1 / N of the input frequency for each divided drive circuit group after the completion of the first writing. . 6. The liquid crystal display device according to claim 1, wherein N is 2. 7. The liquid crystal according to claim 1, wherein the control circuit is disposed at a central portion of a side of the peripheral portion of the pixel portion where the driving circuit is disposed. Display device.