JPH1021280A - Integrated circuit device design method and integrated circuit device - Google Patents

Abstract

(57) [Summary] [Problem] To determine a pin position, based on a toggle rate of an integrated circuit device.
Set the wiring arrangement order, block boundaries, and wiring cross-sectional shapes to reduce power consumption. SOLUTION: When determining the layout of an integrated circuit device, first, a toggle rate calculation means 11 calculates a toggle rate of a pin of each block. The pin processing order determining means 12 rearranges the pin information in descending order of the toggle rate from the calculated toggle rate. The block position extracting means 13 extracts the position of each block. The pin position determining means 14 determines the positions of the pins in each block according to the processing order of the pins. In this way, the wiring having a high toggle rate is preferentially shortened, and the power consumption of the wiring portion due to a change in the signal level is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for designing an integrated circuit device for designing a mask layout of a semiconductor integrated circuit,
And an integrated circuit device.

[0002]

2. Description of the Related Art Conventionally, when a block layout of a semiconductor integrated circuit (hereinafter, referred to as an integrated circuit device) is performed, a pin position of a circuit block and an arrangement order of wirings are determined with particular emphasis on a final chip area and an operation speed. It is common to decide. As a result, the wiring length is shortened as a whole, and the power consumption due to the wiring capacitance is reduced by reducing the capacitance.

In a process of manufacturing an integrated circuit device such as an IC, LSI, or VLSI, a circuit that is incorporated in a chip and has one function by itself is called a block. For example, built-in ROM, RAM, ALU, CPU, DAC,
ADC and the like. A basic logic circuit forming each block is called a cell. For example, OR, AND, NAND,
It is a gate of NOR or the like, or an inverter (INV). The input port and output port of each cell or each block are called pins. Signals are input or output to other blocks via these pins. The signal referred to here is H / L
Refers to the logic signal of the level. The integrated circuit device is, for example, a DSP
In the case of a microcomputer or a one-chip microcomputer, in particular, the level of the clock signal changes at high speed to H or L level.
The level of each bit of the data or address signal changes to H or L level every time data is accessed. The speed at which the signal level changes in each signal line or pin in this manner is called a toggle rate.

In particular, LSI or VLS using CMOS or the like
In the case of realizing I, no problem occurs with a static signal having a low toggle rate, but the signal line of the clock signal or the LSB of the data bus or the address bus has a high toggle rate,
The power consumption due to the wiring capacity in this part cannot be ignored.

[0005]

In the above-mentioned prior art, it is not possible to expect an effect greater than the reduction in power consumption obtained by the reduced area. This technology alone is not sufficient for realizing a low power consumption semiconductor integrated circuit that has become important in recent years.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and has been made in order to further reduce power consumption due to wiring capacitance in an integrated circuit device and to reduce power consumption. And a method for designing an integrated circuit device that efficiently determines the positions of the signal lines and the arrangement order of the signal lines, and an integrated circuit device designed using this method.

[0007]

According to a first aspect of the present invention, there is provided an integrated circuit for designing an integrated circuit device by connecting a plurality of blocks including logic cells via pins serving as connection ports and wiring lines. A method for designing an apparatus, comprising: a toggle rate calculating step of calculating a toggle rate of a pin of each block in an integrated circuit device; and a toggle rate based on the toggle rate of the pin of the block calculated by the toggle rate calculating step. Pin processing order determining step of determining the processing order of the pins so as to be processed sequentially from the pin having the highest number of pins, a block position extracting step of extracting the position of the block on the floor plan, and the pin processing order determining step. Based on the pin processing order and the block position extracted in the block position extraction step, wiring is started from the pin with the highest toggle rate. And pin position determination step of sequentially determining the pin position of Kunar block, is characterized in that it comprises a.

According to a second aspect of the present invention, there is provided an integrated circuit device designing method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via pins serving as connection ports and wiring lines. A toggle rate calculating step of calculating a toggle rate of a pin of the block in the integrated circuit device; and sequentially processing the pin having a higher toggle rate based on the toggle rate of the pin of the block calculated by the toggle rate calculating step. A pin processing order determining step of determining a processing order of pins so as to perform the processing, and an inter-block wiring step of performing wiring between blocks from a pin having a high toggle rate based on the pin processing order determined by the pin processing order determining step. And characterized in that:

According to a third aspect of the present invention, there is provided an integrated circuit device designing method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via pins serving as connection ports and wiring lines. A toggle rate calculating step of calculating a toggle rate of a pin of each block in the integrated circuit device, and a pin having a higher toggle rate based on the toggle rate of the pin of the block calculated by the toggle rate calculating step. A pin processing order determining step of determining a processing order of pins to be processed; a block position extracting step of extracting a position of the block on a floor plan; and a pin processing order determined by the pin processing order determining step. On the basis of the block position extracted in the block position extracting step, wiring is shortened from a pin having a high toggle rate A pin position determining step of sequentially determining a pin position of the lock; and an inter-block wiring step of performing wiring between blocks from a pin having a high toggle rate based on the pin processing order determined by the pin processing order determining step. It is characterized by having.

According to a fourth aspect of the present invention, there is provided an integrated circuit device designing method for designing an integrated circuit device by connecting a plurality of blocks including a logic cell via pins serving as connection ports and wiring lines. A toggle rate calculating step of calculating a toggle rate of each wiring line; a cell extracting step of extracting a cell to which the wiring line is connected; and a toggle rate of the wiring line calculated by the toggle rate calculating step is discriminated. Then, based on the cells extracted in the cell extraction step, the cells to which the wiring lines with a high toggle rate are connected are arranged in the same block, and the cells to which the wiring lines with a low toggle rate are connected are And a block arranging step of arranging the blocks in another block.

According to the invention described in claim 5 of the present application,
An integrated circuit device design method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via a pin serving as a connection port and a wiring line, the toggle ratio for calculating a toggle ratio of each wiring line A calculating step, a cell extracting step of extracting a cell to which the wiring line is connected, and a toggle rate of the wiring line calculated in the toggle rate calculating step are discriminated, and based on the cell extracted in the cell extracting step. When the cells connected by the wiring line having a high toggle ratio belong to different blocks, an inter-block moving step of moving the cells to the same block;
It is characterized by having.

According to a sixth aspect of the present invention, there is provided an integrated circuit device designing method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via pins serving as connection ports and wiring lines. A toggle rate calculating step of calculating a toggle rate of each wiring line, and discriminating based on the toggle rate calculated in the toggle rate calculating step, and a low toggle adjacent to at least one of the high toggle rate wiring lines. And a wiring arrangement order determining step of determining the wiring arrangement order between the blocks so as to arrange the wiring lines of the ratio.

According to a seventh aspect of the present invention, there is provided an integrated circuit device designing method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via pins serving as connection ports and wiring lines. There is a toggle rate calculation step of calculating a toggle rate of each wiring line, a reverse phase wiring extraction step of extracting a wiring line in which the logic level of the wiring line is in a reverse phase relationship, and the toggle rate calculation step. Discriminate based on toggle rate, high toggle rate,
And a wiring arrangement order for arranging at least one low toggle rate wiring line between the wiring lines so as not to be adjacent to each other with respect to the two wiring lines having opposite phases extracted in the negative phase wiring extracting step. And a determining step.

The invention according to claim 8 of the present application is directed to an integrated circuit device designing method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via pins serving as connection ports and wiring lines. A bus wiring extracting step of extracting a wiring line constituting a bus among a plurality of wiring lines between blocks; and a bus wiring line extracted in the bus wiring extracting step, wherein And a wiring arrangement order determining step of sequentially and alternately arranging a plurality of wiring lines and a plurality of wiring lines directed higher than the least significant bit.

According to a ninth aspect of the present invention, there is provided an integrated circuit device in which a plurality of circuit blocks each including a logic cell are connected via a pin serving as a connection port and a wiring line. When the lines are arranged in parallel, when the cross section of the wiring line is rectangular, the long side of each cross section is arranged so as to be substantially orthogonal.

According to each of the above design methods, the arrangement positions of the pins of the block, the arrangement order of the wiring lines between the blocks,
Allocation of blocks followed by each cell can be automatically determined with priority given to signals having a higher toggle rate. Therefore, crosstalk components at wiring lines or pins (ports of each cell) through which high-frequency signals flow are reduced, and power consumption due to crosstalk can be suppressed. Therefore, the power consumption of the integrated circuit device can be reduced.

Also, since the cells connected by the high toggle rate wiring lines are rearranged in the same block, even when a part of the function of the integrated circuit device is changed, a mask is formed for each block already formed. Redesigning the layout will not increase power consumption due to crosstalk.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) A design method of an integrated circuit device according to a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is an explanatory diagram showing an outline of an integrated circuit device designing apparatus according to the first embodiment. This design device is configured to include a toggle rate calculating unit 11, a pin processing order determining unit 12, a block position extracting unit 13, and a pin position determining unit 14.

The toggle rate calculating means 11 is a means for calculating a toggle rate of a pin of a block to be laid out. Then, the calculated toggle rate is passed to the pin processing order determining means 12. The pin processing order determining means 12 is a means for rearranging the pin information from the toggle rate of each pin of the layout block in descending order of the toggle rate. The result is output to the pin position determining means 14.

On the other hand, the block position extracting means 13 is means for extracting the position of the layout block on the floor plan. The result is output to the pin position determining means 14.
The pin position determining unit 14 receives the pin processing order input from the pin processing order determining unit 12 and the layout block position information input from the block position extracting unit 13, and determines the pin position of each layout block. Is a means for determining in accordance with the processing order.

FIG. 2 is a flowchart showing a procedure of a method for designing an integrated circuit device according to the first embodiment. Step A
In (2), the toggle ratio of each pin of the layout block is calculated by the toggle ratio calculation means 11. In step B, the pin information is rearranged so that the pin processing order determining means 12 performs the processing in ascending order of the toggle rate from the pin toggle rate of the layout block passed from step A.

In step C, the block position extracting means 1
3, the position of the layout block on the floor plan is extracted. Based on the pin processing information extracted in step B in step D and the position information on the floor plan of the layout block extracted in step C,
The pin position of each layout block is determined by the pin position determining means 14. The details of each step will be described below.

FIG. 3 is a flowchart showing the procedure for calculating the toggle rate in step A. In step a1, only the pins of the layout block are extracted from the hardware description language. In step a2, a description for detecting the toggle ratio of the pin at the time of simulation is created from the pin extracted in step a1, and added to the simulation file. In step a3, a simulation is executed, and in step a4, a result of the toggle ratio of the pin of each layout block is obtained.

FIG. 4 is a flowchart for determining the processing order of the pins in step B. Step a in step b1
The toggle rate generated in step 4 is read, and in step b2, the pin information of the layout blocks is rearranged in descending order of the toggle rate based on the toggle rate read in step b1.

FIG. 5 is a flowchart showing a procedure for extracting the position of a block in step C. Step c1
In step c2, information on the floor plan is read.
Extract the position information of the unprocessed layout block on the floor plan. In step c3, it is determined whether the reading of the position information of all the layout blocks has been completed, and if not, the process returns to step c2.

FIG. 6 is a flowchart showing a procedure for determining the positions of the pins of the layout block in step D. In step d 1, the pin having the highest processing order in the processing order determined by the pin processing order determining means 12 is extracted from the pins for which the processing for determining the pin position has not been completed.
The pin is arranged at a position where the distance between the pins connected in step d2 is shortest. At step d3, it is determined whether or not all pins have been placed. If any pins have not been placed, the process returns to step d1.

FIG. 7 is a schematic plan view of a first example of an integrated circuit device on which the pin arrangement processing has been performed in step d2. When two pins are provided for wiring from the layout block 15a to the layout block 15b, the layout block 15a is viewed from the layout block 15b.
The pin 16a is arranged at the closest position where it can be arranged.
Further, a pin 16b is arranged on the layout block 15b at a position closest to the layout block 15a.

FIG. 8 is a schematic plan view showing, as a second example, the integrated circuit device that has performed the pin arrangement processing in step d2. In this example, there are a plurality of pin arrangement positions where the distance between the layout blocks is short. When arranging pins for wiring from the layout block 15c to the layout block 15d, the origin is at the lower left of the layout, and y
The pins 16c and 16d are arranged at positions closest to the direction.

FIG. 9 is a schematic plan view showing, as a third example, the integrated circuit device that has performed the pin arrangement processing in step d2. In this example, the layout block where the pins are arranged is 3
It is one. In this case, the layout block 15e
And layout block 15f and layout block 15
The pin 16 is arranged at a position where the sum of the distances between the pins 16e, 16f, and 16g is the shortest between the positions g.

As described above, according to the design method of the first embodiment, the pin arrangement can be determined so that the wiring line becomes shorter from the pin having the higher toggle rate.

(Embodiment 2) A design method of an integrated circuit device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 10 is an explanatory diagram showing an outline of an integrated circuit device designing apparatus according to the second embodiment. This design device includes a toggle rate calculating means 21 and a pin processing order determining means 2
2. It is configured to include the inter-block wiring means 23.

The toggle rate calculating means 21 calculates the toggle rate of the pins of the layout block. The calculation result is output to the pin processing order determining means 22. The pin processing order determination means 22 is means for rearranging the pin information in ascending order of the toggle rate from the toggle rate of the pins of the layout block passed from the toggle rate calculation means 21. This result is output to the inter-block wiring means 23. The inter-block wiring means 23 is means for receiving information on the pin processing order of the layout blocks from the pin processing order determining means 21 and performing wiring in accordance with the processing order.

FIG. 11 is a flowchart showing a procedure of a method for designing an integrated circuit device according to the present embodiment. Step E
, The toggle rate calculating means 21 calculates the toggle rate of the pins of the layout block. In step F, the pin processing order determining means 22 rearranges the pin information from the toggle ratio of the pins of the layout block passed from step E in order to perform the processing in descending order of the toggle ratio. In step G, wiring between the layout blocks is performed by the inter-block wiring means 23 based on the pin processing information extracted in step F. Note that the flow of calculating the toggle rate in step E is the same as the flow shown in FIG. Further, the flow of determining the pin processing order in step F is the same as the flow shown in FIG. Here, the details of step G will be described.

FIG. 12 is a flowchart showing a procedure for performing inter-block wiring in step G. Step g1
Then, wiring is performed between the pins having the highest processing order according to the processing order determined by the pin processing order determining means 22 for the pins for which wiring has not been completed. At step g2, it is determined whether or not the wiring processing has been completed for all the pins.

As described above, according to the design method of the second embodiment, by determining the wiring from the pin having the high toggle rate, the wiring line between the pins having the high toggle rate can be shortened.

(Embodiment 3) A design method of an integrated circuit device according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 13 is an explanatory diagram showing an outline of an integrated circuit device designing apparatus according to the third embodiment. This design device includes a toggle rate calculating means 31, a pin processing order determining means 3,
2. Block position extracting means 33, pin position determining means 3
4. It is configured to include the inter-block wiring means 35.

The toggle rate calculating means 31 is a means for calculating the toggle rate of the pins of the layout block. The pin processing order determining means 32 is a means for rearranging the pin information in ascending order of the toggle rates from the toggle rates of the pins of the layout blocks passed from the toggle rate calculation means 31. This result is output to the pin position determining means 34 and the inter-block wiring means 35.

The block position extracting means 33 is a means for extracting the position of the layout block on the floor plan.
The pin position determining means 34 inputs the information of the processing order of the pins of the layout block from the pin processing order determining means 31 and the position information of the layout block from the block position extracting means 33, and outputs the position of the pin of each layout block Is determined in accordance with the processing order of the pins.
The inter-block wiring means 35 is a means for inputting pin position information from the pin position determining means 34 and inputting information on the pin processing order of layout blocks from the pin processing order determining means 32 to perform wiring.

FIG. 14 is a flowchart showing a procedure of a method for designing an integrated circuit device according to the present embodiment. Step H
In, the toggle rate calculating means 31 calculates the toggle rate of the pins of the layout block. In step I, the pin processing order determining means 32 rearranges the pin information to be processed in descending order of the toggle rate from the toggle rate of the pins of the layout block passed from step H. In step J, the position of the layout block on the floor plan is extracted by the block position extracting means 33.

Based on the pin processing information extracted in step I in step K and the position information on the floor plan of the layout block extracted in step J, the pin position determining means 34 determines the pin position of each layout block. decide. In step L, wiring between the layout blocks is performed by the inter-block wiring means 35 based on the pin processing information extracted in step I.

The flow of calculating the toggle rate in step H is the same as the flow shown in FIG. Further, the flow of determining the pin processing order in step I is the same as the flow shown in FIG. Also, the flow of extracting the block position in step J is the same as the flow shown in FIG. Further, the flow of determining the pin position in step K is the same as the flow shown in FIG. The flow of the inter-block wiring in step L is the same as the flow shown in FIG.

(Embodiment 4) A design method of an integrated circuit device according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 15 is an explanatory diagram showing an outline of an integrated circuit device designing apparatus according to the fourth embodiment. This design device is configured to include a toggle rate calculating unit 41, a cell extracting unit 42, a cell selecting unit 43, a block dividing unit 44, and a block arranging unit 45.

The toggle rate calculation means 41 is means for calculating the toggle rate of the wiring. The cell extracting means 42 is a means for extracting a cell to which a wiring is connected. The cell extracting means 42 is a means for selecting a cell to which a wiring having a high toggle rate is connected and a cell to which a wiring having a low toggle rate is connected. The block division unit 44 is a unit for setting or changing the division of a block. The inter-block arrangement unit 45 is a unit for creating a new block.

FIG. 16 is an explanatory diagram showing an example of a cell selection technique in the integrated circuit device designing method of the present embodiment. As shown in the figure, a plurality of cells 46 are provided in the integrated circuit device.
a to 46f. For example, cells 46a, 46b, 46
d and 46e are connected by a high toggle net 47 indicated by thick lines, and cells 46b, 46c and 46f indicated by thin lines.
Are connected by a low toggle net 48.

FIG. 17 is an explanatory diagram showing a block dividing method of the integrated circuit device in the design method of the present embodiment. Here, the cells 46a connected by the high toggle net 47,
46b, 46d and 46e are treated as one block 49a, and cells 46c and 46f are treated as another block 49b.

The operation of the thus designed integrated circuit device designing apparatus will be described. First, the toggle rate of the wiring is calculated by the toggle rate calculation means 41, and the calculation result is provided to the cell selection means 43. The cell extracting unit 42 extracts a cell to which the wiring is connected, and supplies the extraction result to the cell selecting unit 43. The cell selecting means 43 selects the cells to be connected in the order of the wiring having the highest toggle rate, and delivers the result to the block dividing means 44. As a result, as shown in FIG. 16, cells are collected so that the cells 46 having a high toggle rate are close to each other.

For the cells selected by the block dividing means 44, as shown in FIG. 17, the cells connected to the high toggle net 47 are assigned to the same block 49a, and the cells connected to the low toggle net 48 are the same. Block 4 of
Assign to 9b. The wiring between the blocks should be a low toggle net. Finally, the block arrangement means 45
To rearrange the cells 46 in each block.

As described above, according to the present embodiment, by arranging the cells connected to the high toggle net in the same block, even if there is a rearrangement of the block, it is possible to perform the high toggle without changing within the block. The total wiring length of the net can be shortened.

(Embodiment 5) A method for designing an integrated circuit device according to a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 18 is an explanatory diagram showing an outline of an integrated circuit device designing apparatus according to the fifth embodiment. This design device is configured to include a toggle rate calculating unit 51, a cell extracting unit 52, a cell selecting unit 53, and an inter-block moving unit 54. It should be noted that the toggle rate calculating means 51, the cell extracting means 52,
The cell selection means 53 is the same as that of the fourth embodiment.
The inter-block moving means 54 is means for moving one cell group to another block when a cell group having a high toggle rate and a cell group having a low toggle rate are mixed in the same block.

FIG. 19 is a cell layout diagram showing a state before the arrangement of the integrated circuit device is improved. In the figure, a block 49c includes cells 46a, 46b, 46
c is arranged, and cells 46d, 46d are placed in block 49d.
e, 46f are arranged. And 46a, 46b,
46d and 46e are connected by a high toggle net 47,
b, 46c and 46f are connected by a low toggle net 48.

FIG. 20 is a layout diagram showing the result of moving cells of an integrated circuit device between blocks using the design apparatus of this embodiment. Here, block 46c includes cells 46a,
46b, 46d and 46e are arranged, and cells 46c and 46f are arranged in a block 49d. The cells in block 49c are connected by a high toggle net 47 and the cells in block 49d are connected by a low toggle net 48.

The operation of the integrated circuit device designing apparatus thus configured will be described. First, the toggle rate of the wiring is calculated by the toggle rate calculation means 51, and the calculation result is given to the cell selection means 53. The cell extracting means 52 extracts a cell to which the wiring is connected, and supplies the extraction result to the cell selecting means 53. The cell selecting means 53 selects the cells to be connected in the order of the wiring having the highest toggle rate, and delivers the result to the inter-block moving means 54. As a result, as shown in FIG. 16, cells are collected so that the cells 46 having a high toggle rate are close to each other.

In the inter-block moving means 54, as shown in FIG. 19, a cell group (cells 46a, 46b, 46d, 46e) connected to the high toggle net 47 for the cells already disposed in the blocks 49c, 49d. ) Are grouped in the same block 49c, and the cell group (cells 46c, 46f) connected to the low toggle net 48 is grouped in the same block 49d. The wiring between the blocks should be a low toggle net. This results in the rearrangement as shown in FIG.

As described above, according to the present embodiment, by moving the cell group connected to the high toggle net so as to be accommodated in the same block, the total wiring of the high toggle net can be performed even if the block is rearranged. The length can be shortened.

(Embodiment 6) A method of designing an integrated circuit device according to a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 21 is an explanatory diagram showing an outline of an integrated circuit device designing apparatus according to the sixth embodiment. This design device includes a toggle ratio calculating unit 61, a wiring arrangement order determining unit 6,
2 is included. Note that the toggle rate calculation means 61 is the same as that of the previous embodiments. The wiring arrangement order determining means 62 is a means for determining the arrangement of wiring lines to be wired between blocks or between cells based on the magnitude of the toggle rate.

The operation of the thus designed integrated circuit device designing apparatus will be described. FIG. 22 is an arrangement diagram when a plurality of wiring lines are provided between blocks. Here, a wiring 64a is provided between the block 63a and the block 63b.
６４64c is provided. First, the toggle rate calculating means 61 calculates the toggle rates of the wirings 64a to 64c between the blocks, and passes the result to the wiring arrangement order determining means 62.

In the conventional inter-block wiring method, power consumption is not considered when deciding the arrangement order of the wiring, and therefore, there is no guarantee that the wiring capacity is reduced as a result of wiring. In this embodiment, the toggle ratio of each wiring is obtained, and the wiring is determined based on the result, so that the wiring capacitance is reduced. In FIG. 22, for example, a wiring 64a
Has the maximum toggle rate, this wiring 64a is arranged so as to be sandwiched from both sides by using other wirings 64b and 64c having a low toggle rate. Thus, crosstalk between wirings and current consumption due to crosstalk can be reduced.

Embodiment 7 A method for designing an integrated circuit device according to Embodiment 7 of the present invention will be described with reference to the drawings. FIG. 23 is an explanatory diagram showing an outline of an integrated circuit device designing apparatus according to the seventh embodiment. This design device includes a toggle rate calculating means 71, an antiphase wiring extracting means 72,
The wiring arrangement order determining means 73 is included. The toggle ratio calculating means 71 and the wiring arrangement order determining means 73 are the same as those in the sixth embodiment. Antiphase wiring extraction means 72
Is means for extracting wiring lines having H / L levels opposite to each other at the same time among wiring lines wired between blocks or cells.

The operation of the integrated circuit device designing apparatus having such a configuration will be described. FIG. 24 is an arrangement diagram when a plurality of wiring lines are provided between blocks. Here, wirings 75a to 75b are provided between the block 74a and the block 74b.
5e. First, the toggle rate calculating means 71 calculates the toggle rate of the wirings 75a to 75e between the blocks. Then, the reversed-phase wiring extracting means 72 extracts wirings having phases opposite to each other, for example, a clock signal and its inverted clock signal, and delivers the results to the wiring arrangement order determining means 73.

In FIG. 24, for example, the wiring 75a and the wiring 7
5b is in the opposite phase, and these wirings have a high toggle rate. The antiphase wiring extracting means 72 extracts such wirings 75a and 75b and outputs the result to the wiring arrangement order determining means 73. The wiring arrangement order determining means 73 selects a wiring 75c having a low toggle rate from the remaining wirings,
Wirings 75a and 75b are arranged on both sides of the wiring 75c. In this case, a plurality of wirings may be arranged instead of one. Further, similarly to the sixth embodiment, low-toggle-rate wirings 75d and 75e are also provided outside the wirings 75a and 75b.
Are arranged respectively. Thus, crosstalk of wiring can be reduced, and current consumption due to crosstalk can be reduced.

(Embodiment 8) A method for designing an integrated circuit device according to an eighth embodiment of the present invention will be described with reference to the drawings. FIG. 25 is an explanatory diagram showing an outline of an integrated circuit device designing apparatus according to the eighth embodiment. This design device includes a bus wiring extracting means 81, a wiring arrangement order determining means 8
2 is included. The wiring arrangement order determining means 82
Are the same as those in the sixth and seventh embodiments. The bus wiring extraction means 81 is a part of the wiring group connected between the blocks.
This is a means for extracting a bus wiring such as a data bus and an address bus.

In the conventional inter-block wiring, since the wiring is usually a bus wiring, the wiring arrangement is not particularly considered. Therefore, even the bus wiring was normally treated in the same manner as other wirings. In the present embodiment, even if the toggle rate of each wiring is not known, the wiring capacity is stochastically reduced based on the information that the wiring is a bus wiring.

In the design of an integrated circuit device, bus wiring is often performed, and the toggle rate of each bit of this bus is such that, on average, the lower bit (LSB) is higher than the upper bit (MSB). large. This is because some buses, such as a data bus, have little difference in each bit stochastically, but there are many uses, such as an address bus, where 1 is added to the immediately preceding content.

The wires 83a to 83g shown in FIG. 26 are wires constituting one bus. 83a is the least significant bit, 83b is the second least significant bit, and so on.
Is the most significant bit. At this time, the wiring 83g
Can be estimated to have the lowest toggle rate, so it is placed at the end.
Next, the wiring 83a that can be estimated to have the highest toggle rate is arranged next to it. Hereinafter, the wiring 83f of the second bit from the most significant bit and the wiring 83 of the second bit from the least significant bit
They are arranged sequentially as in b. As a result, at the end opposite to the position where the wiring of the most significant bit is arranged, the wiring of the middle order bit which is estimated to have a not so high toggle ratio is arranged. Thus, crosstalk of wiring can be reduced, and power consumption due to crosstalk can be reduced.

(Embodiment 9) A method of designing an integrated circuit device according to a ninth embodiment of the present invention will be described with reference to the drawings. FIG. 27 is a cross-sectional view showing a wiring method of the integrated circuit device according to the ninth embodiment. FIG. 28 is a sectional view showing a wiring method of a conventional integrated circuit device. FIG.
In No. 8, the adjacent wirings 92a and 92b, or the wirings 92a and 92c, were formed such that the long sides of the rectangular cross sections were in the same direction. In this case, the adjacent wirings 92a and 92c form a parallel plate capacitor, and the wiring capacitance is increased.

In this embodiment shown in FIG. 27, adjacent wirings 91a and 91b or wirings 91a and 91a
c is formed such that the long sides of the rectangular cross section are orthogonal to each other. In this case, the wiring capacitance of the parallel plate capacitor is reduced, and the wiring has a small wiring capacitance as a whole.

[0067]

As described above, according to the method of designing an integrated circuit device of the present invention, in order to realize a desired circuit function, in the step of designing the layout of each block including a plurality of cells, first, each wiring line And the pin toggle rate is calculated. Here, by using the data of the toggle ratio discriminated, the position of the pin and the arrangement of the wiring line are determined in preference to the one with the high toggle ratio, and the assignment of the cells belonging to the same block is determined. Therefore, power consumption loss due to crosstalk between wiring lines can be minimized. Therefore, using a block with a given function,
A low power consumption semiconductor integrated circuit device can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an apparatus for designing an integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method for designing an integrated circuit device according to the first embodiment.

FIG. 3 is a flowchart showing an operation of a toggle rate calculating means in the design method of the first embodiment.

FIG. 4 is a flowchart showing an operation of a pin processing order determining unit in the design method of the first embodiment.

FIG. 5 is a flowchart showing an operation of a block position extracting means in the design method of the first embodiment.

FIG. 6 is a flowchart showing an operation of a pin position determining unit in the design method of the first embodiment.

FIG. 7 is an explanatory diagram showing a first example of a pin position determination method between two blocks in the design method of the first embodiment.

FIG. 8 is an explanatory diagram showing a second example of a pin position determination method between two blocks in the design method of the first embodiment.

FIG. 9 is an explanatory diagram showing an example of a pin position determination method between three blocks in the design method of the first embodiment.

FIG. 10 is a configuration diagram of an integrated circuit device designing apparatus according to a second embodiment of the present invention.

FIG. 11 is a flowchart illustrating a design method of an integrated circuit device according to a second embodiment.

FIG. 12 is a flowchart showing the operation of the inter-block wiring means in the design method of the second embodiment.

FIG. 13 is a configuration diagram of an integrated circuit device designing apparatus according to a third embodiment of the present invention.

FIG. 14 is a flowchart showing a method for designing an integrated circuit device according to the third embodiment.

FIG. 15 is a configuration diagram of an integrated circuit device designing apparatus according to a fourth embodiment of the present invention.

FIG. 16 is an explanatory diagram showing an operation of a cell selection unit in the design method of the fourth embodiment.

FIG. 17 is an explanatory diagram showing an operation of a block dividing unit in the design method of the fourth embodiment.

FIG. 18 is a configuration diagram of an integrated circuit device designing apparatus according to a fifth embodiment of the present invention.

FIG. 19 is an explanatory diagram (part 1) illustrating the operation of the method for designing an integrated circuit device in the fifth embodiment.

FIG. 20 is an explanatory diagram (part 2) illustrating the operation of the method for designing an integrated circuit device in the fifth embodiment.

FIG. 21 is a configuration diagram of an integrated circuit device designing apparatus according to a sixth embodiment of the present invention.

FIG. 22 is a plan view showing a wiring state in which a wiring having a high toggle rate is interposed between wirings having a low toggle rate in the sixth embodiment;

FIG. 23 is a configuration diagram of an integrated circuit device designing apparatus according to a seventh embodiment of the present invention.

FIG. 24 is a plan view showing a wiring state of a high toggle rate and a negative-phase signal in the seventh embodiment.

FIG. 25 is a configuration diagram of an integrated circuit device designing apparatus according to an eighth embodiment of the present invention.

FIG. 26 is a plan view showing an arrangement state of bus wirings in an eighth embodiment.

FIG. 27 is a cross-sectional view of a wiring using the design method according to the ninth embodiment of the present invention.

FIG. 28 is a cross-sectional view of two parallel wirings when a general design method is used.

[Explanation of symbols]

11, 21, 31, 41, 49a to 49d, 51, 6
1,71 Toggle rate calculating means 12,22,32 Pin processing order determining means 13 Block position extracting means 14,34 Pin position determining means 15,15a to 15g, 63a, 63b, 74a, 74
b block 16, 16a to 16g pin 23, 35 inter-block wiring means 33 block position extracting means 42, 52 cell extracting means 43, 53 cell selecting means 44 block dividing means 45 block arranging means 46, 46a to 46f cell 47 high toggle net 48 low toggle net 54 inter-block moving means 62, 73, 82 placement and wiring order determining means 64a to 64c, 75a to 75e, 91a to 91c, 9
2a-92c Wiring 72 Negative-phase Wiring Extraction Means 81 Bus Wiring Extraction Means 83a-83e Bus Wiring

Continuing from the front page (72) Inventor Kenji Yokoyama 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Katsuhiko Hirose 1006 Okadoma Kadoma, Kadoma City Osaka Pref.

Claims (9)

[Claims] An integrated circuit device design method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via pins serving as connection ports and wiring lines, wherein each block in the integrated circuit device is provided. A toggle rate calculating step of calculating a toggle rate of the pin, and a processing order of the pins such that the pins are sequentially processed in descending order of the toggle rate based on the toggle rates of the pins of the block calculated in the toggle rate calculating step. A pin processing order determining step for determining; a block position extracting step for extracting a position of the block on a floor plan; a pin processing order determined by the pin processing order determining step; and a block position extracting step. Based on the block position, determine the pin position of the block sequentially so that the wiring becomes shorter from the pin with the higher toggle rate Method of designing an integrated circuit device characterized by comprising a lupine positioning step. 2. A method for designing an integrated circuit device, wherein a plurality of blocks including logic cells are connected via a pin serving as a connection port and a wiring line, the integrated circuit device being designed. A toggle rate calculation step of calculating a toggle rate of the pin, and a processing order of the pins is determined based on the toggle rate of the pin of the block calculated in the toggle rate calculation step so that the pins are sequentially processed from a pin having a higher toggle rate. A pin processing order determining step to perform, and an inter-block wiring step of performing wiring between blocks from a pin having a high toggle rate based on the pin processing order determined by the pin processing order determining step. Integrated circuit device design method. 3. An integrated circuit device designing method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via pins serving as connection ports and wiring lines, wherein each block in the integrated circuit device is provided. A toggle rate calculating step of calculating a toggle rate of the pin, and a processing order of the pins such that the pins are sequentially processed in descending order of the toggle rate based on the toggle rates of the pins of the block calculated in the toggle rate calculating step. A pin processing order determining step for determining; a block position extracting step for extracting a position of the block on a floor plan; a pin processing order determined by the pin processing order determining step; and a block position extracting step. Based on the block position, determine the pin position of the block sequentially so that the wiring becomes shorter from the pin with the higher toggle rate A pin position determining step, and an inter-block wiring step of performing wiring between blocks from a pin having a high toggle rate based on the pin processing order determined in the pin processing order determining step. A method for designing an integrated circuit device. 4. A method for designing an integrated circuit device, wherein a plurality of blocks including logic cells are connected via a pin serving as a connection port and a wiring line, and the toggle rate of each wiring line is determined. Calculating a toggle rate, calculating a cell, extracting a cell to which the wiring line is connected, and extracting the toggle rate of the wiring line calculated in the toggle rate calculation step, extracted in the cell extraction step Based on the selected cell, a block to be placed in the same block for a cell to which a wiring line with a high toggle rate is connected, and a block to be placed in another block for a cell to which a wiring line with a low toggle rate is connected. And a step of arranging the integrated circuit device. 5. An integrated circuit device designing method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via pins serving as connection ports and wiring lines, wherein a toggle rate of each wiring line is provided. Calculating a toggle rate, calculating a cell, extracting a cell to which the wiring line is connected, and extracting the toggle rate of the wiring line calculated in the toggle rate calculation step, extracted in the cell extraction step An inter-block movement step of, when cells connected by a wiring line with a high toggle rate belong to different blocks based on the selected cell, moving the cells to the same block, Method. 6. An integrated circuit device designing method for designing an integrated circuit device by coupling a plurality of blocks including logic cells via pins serving as connection ports and wiring lines, wherein the toggle rate of each wiring line is provided. A toggle rate calculating step of calculating, and discriminating based on the toggle rate calculated in the toggle rate calculating step, and arranging a low toggle rate wiring line adjacent to at least one of the high toggle rate wiring lines. A wiring layout order determining step of determining a wiring layout order between the wirings. 7. An integrated circuit device designing method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via a connection port pin and a wiring line, wherein the toggle rate of each wiring line is provided. Calculating a toggle rate, calculating the logic level of the wiring line, extracting a wiring line having a reverse phase relationship, extracting a wiring line, and discriminating based on the toggle rate calculated in the toggle rate calculation step, toggle At least one wiring line with a low toggle ratio is arranged between the wiring lines so as not to be adjacent to each other with respect to the two wiring lines having a high ratio and having the opposite phases extracted in the negative-phase wiring extracting step. And a wiring arrangement order determining step. 8. An integrated circuit device designing method for designing an integrated circuit device by connecting a plurality of blocks including logic cells via pins serving as connection ports and wiring lines, wherein a plurality of wirings between blocks are provided. A bus wiring extracting step of extracting a wiring line constituting a bus among the lines; and a plurality of wiring lines and lowermost bits directed to lower than the most significant bit with respect to the bus wiring line extracted in the bus wiring extracting step. A wiring arrangement order determining step of sequentially and alternately arranging a plurality of wiring lines toward a higher order,
A method for designing an integrated circuit device, comprising: 9. An integrated circuit device in which a plurality of circuit blocks each including a logic cell are connected via a pin serving as a connection port and a wiring line, when two wiring lines that interfere with each other are arranged in parallel. An integrated circuit device, wherein when a cross section of a wiring line is rectangular, the long sides of each cross section are arranged to be substantially orthogonal.