JPH1022284A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: Provided is a multilayer wiring interlayer insulating film having a base film structure that prevents deterioration of flatness of an upper layer reflow SiO ₂ film and blocks diffusion under water, and a method of manufacturing the same. A lower aluminum wiring is formed on an insulating film on a main surface of a semiconductor wafer. On the wafer, a P-SiO film (an SiO film formed by a plasma CVD method) 12 including the aluminum wiring 11 is laminated. P-
An amorphous Si film 13 is formed on the SiO film 12. These films 12 and 13 are directly above the reflow SiO2 film 15
Base film. That is, a reflow SiO2 film 14 is formed on the amorphous Si film 13, and a P-SiO film 15 for a cap is formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure and a method of forming an interlayer insulating film of a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor devices increases, so-called multilayer wiring, in which wiring materials are formed in multiple layers on a substrate, is in progress. The manufacturing process of a semiconductor device having a multilayer wiring structure has become complicated and longer, and is regarded as a major factor in lowering the product yield and increasing the manufacturing cost. In particular, the rate at which the multilayer wiring forming step occupies the manufacturing cost of the semiconductor device is large, and the demand for reducing the cost of the multilayer wiring step is increasing in order to reduce the cost of the semiconductor device.

In a conventional multi-layer wiring formation process, first, a first wiring material for a lower wiring is deposited, and then the lower wiring is patterned, and a first insulating film is formed on the lower wiring and a lower insulating film is formed. An insulating film is embedded between the wirings. At this point, there is a step on the surface of the first insulating film depending on the pattern of the lower wiring. In this state, there is an adverse effect on the subsequent deposition of the second wiring material for the upper layer wiring and on the patterning of the upper layer wiring, which may result in a disconnection failure due to disconnection of the upper layer wiring.

Therefore, usually, before depositing the second wiring material, the surface of the first insulating film, which is the base material, is formed by a resist etch back method or a CMP (Chemical Mechanical Polishing) method.
After the surface is flattened by a sing) method or the like to reduce the step, the second wiring material and the second insulating film are formed.

However, the conventional process of forming an interlayer insulating film in which the first insulating film and the second insulating film are laminated involves a large number of steps of first film formation → planarization → second film formation. This is a major obstacle to the demand for reduction in the number of multilayer wiring steps as described above.

On the other hand, instead of the method of flattening the surface of the first insulating film, SOG which is an insulating material is formed on the first insulating film.
There is also known a method of forming a (Spin on Glass) film to alleviate a step of an underlayer of an upper wiring material. However, this method requires a large number of heat treatment steps when forming (coating and baking) the SOG film, and in order to secure the reliability of the wiring, unnecessary portions of the SOG film are removed by a resist etch-back method or the like. Need to be removed. As a result, the number of steps increases, and it is still impossible to sufficiently meet the above-described demand for reduction in the number of multilayer wiring steps.

As one of the techniques for planarizing the surface of an interlayer insulating film, an APL (Advanced Planarization Layer) is used.
The process has been reported (Matsuura e
t.al., IEEE Tech.Dig.pp117, 1994). In this APL process, when an interlayer insulating film is formed, SiH ₄ gas and H ₂ O ₂ (hydrogen peroxide solution) as an oxidizing agent are reacted in a low temperature (for example, 0 ° C.) and in a vacuum to form a lower wiring. A self-flowing (reflow) SiO2 film (hereinafter referred to as a reflow SiO2 film) is formed thereon.

According to this method, the insulating film can be buried between the lower wiring layers and the surface of the insulating film can be flattened at the same time.
Since the process up to the planarization is completed by one film formation, it is possible to sufficiently meet the demand for reducing the number of multilayer wiring processes.

Before the reflow SiO ₂ film is formed, a first plasma CVD insulating film as a first interlayer insulating film (base insulating film) is formed on the lower wiring by a normal plasma CVD method. May be. After the reflow SiO ₂ film is formed, a _second plasma CVD as a second interlayer insulating film (cap film) is also formed on the reflow SiO ₂ film by the usual plasma CVD method.
There is a case where an insulating film is formed and then furnace annealing is performed.

In the above APL process, the reflow Si
The flattening is achieved by the reflow degree of the O2 film. Further, in the APL process technology, it is essential that the amount of water in the reflow SiO ₂ film be desorbed out of the film by the above-described furnace annealing. If water desorption is insufficient,
The residual moisture has the following adverse effects. For example, adverse effects such as corrosion and loss on aluminum wiring
In addition, it is known that the element itself has an adverse effect such as deterioration of hot carrier reliability resistance.

Therefore, it is not an exaggeration to say that the key to the success or failure of the process is how to remove the water in the reflow SiO ₂ film outside the film during the furnace annealing. When considering the direction of desorption outside the membrane, the reflow S
Naturally, the influence of the diffusion of water downward in the iO ₂ film on the aluminum wiring and the element becomes significant. On the other hand, since there is no structure above, it is natural that there is no need to consider any adverse effect on the device when all the moisture in the film diffuses upward.

Therefore, in view of the above-described APL process structure, the base film directly under the reflow SiO ₂ film plays a role of blocking the downward diffusion of moisture, and the quality of the blocking property is extremely important. It is a problem.
In consideration of such a water blocking property, conventionally, application of a P-SiO film or a P-SiN film formed by plasma CVD as a base film has been studied (P- means plasma). However, these conventional base films have the following problems.

First, it cannot be said that the essential water blocking property of the P-SiO film has reached a satisfactory level. Specifically, the adverse effects represented by the loss of the aluminum wiring and the deterioration of the hot carrier reliability of the device have become apparent. Originally, it is considered that the P-SiO film cannot have an excessive expectation for the water diffusion blocking ability in view of physical properties such as the film density.

On the other hand, in the case of a P-SiN film, on the contrary, considering the physical properties such as the film density, the moisture diffusion blocking ability is excellent among the insulating films, and is good even when actually used as a base film in the APL process. Results have been obtained. However, there are the following problems as side effects.

First, since the P-SiN film is formed using NH ₃ gas, [-NH] is formed in the film and on the film surface.
₂ ] There are many [-NH] groups. These [-NH
₂ ] The presence of [-NH] groups renders the film hydrophobic. This impairs the reflow properties of the reflow SiO2 film immediately above. When a P-SiN film is actually used as the base film, the flatness of the reflow SiO ₂ film is deteriorated, and it is almost necessary to add a flattening step.
This is fatal because the APL process finds its value at a point where a planarization step is unnecessary.

[0016]

As described above, conventionally,
When the APL process technology is applied to the interlayer insulating film forming process in the multilayer wiring process, the P film used as a base film is used.
-The SiO film or the P-SiN film itself does not have satisfactory characteristics. That is, the former has a problem such as a defect of the AL wiring and the deterioration of the hot carrier reliability of the element, and the latter has a problem that the flatness of the reflow SiO ₂ film is deteriorated.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to prevent the flatness of the reflow SiO ₂ film from deteriorating and to reduce the AL wiring and the hot carrier reliability of the element. It is an object of the present invention to provide a novel base film structure capable of avoiding the problem and a semiconductor device to which the method for forming the same is applied and a method for manufacturing the same.

[0018]

A typical structure of a semiconductor device according to the present invention has fluidity or self-flatness formed on an uneven shape reflected by an element or a wiring formed on a semiconductor substrate. An insulating film and a base film made of an amorphous Si film existing immediately below the insulating film are provided.

A typical method of manufacturing a semiconductor device according to the present invention is a process of forming an insulating film having fluidity or self-flatness on an uneven shape reflected by an element or a wiring formed on a semiconductor substrate. A step of forming a laminated structure of an amorphous Si film and a plasma SiO ₂ film as a base film of the insulating film before forming the insulating film;
The film and the plasma SiO ₂ film are continuously formed in a plasma CVD chamber kept in a vacuum at a temperature of 200 ° C. to 450 ° C.

[0020]

FIG. 1 is a sectional view showing a structure of an interlayer insulating film between multilayer wirings of a semiconductor device as a main part according to the present invention. The APL process is applied to a wafer which needs to cover an element or a wiring formed on a semiconductor substrate and form an interlayer insulating film having good flatness. For example, a lower aluminum wiring 11 is formed on an insulating film 10 on a main surface of a semiconductor wafer on which elements and the like are formed. On the wafer, the P-
An SiO film (SiO film by a plasma CVD method) 12 is laminated. Amorphous Si film 13 on P-SiO film 12
Are formed. A reflow SiO2 film 14 is formed on the amorphous Si film 13, and a capping P-
An SiO film 15 is formed.

A material newly introduced in the present invention is an amorphous Si film (13). Amorphous Si
The characteristics of the film will be discussed by comparing it with a conventional P-SiN film used as a base film.

(1) The amorphous Si film is different from the P-SiN film due to the necessity in the film forming process.
[-NH _2] in the film and the film surface [- NH] no group is present. [-NH _2] [- NH] groups are hydrophobic groups, so hinder the flatness of the reflow SiO2 film immediately above as described above (14), an amorphous Si film not containing these (1
3) P-Si for ensuring the flatness of the reflow SiO2 film.
It is more advantageous than the N film.

(2) With respect to the property of blocking the downward diffusion of water in the reflow SiO ₂ film (14), the amorphous Si film has the same excellent characteristics as the P-SiN film. That is, it is much better than the P-SiO film.

It is understood that the P-SiN film has a high film density and therefore has a property of blocking moisture permeation through the film. On the other hand, an amorphous Si film is hydrophilic because it contains a large number of [-H] groups and [Si-.] Groups (Si dangling groups). Therefore, it is considered that high blockability is secured and the downward diffusion of water is suppressed. That is, P
It can be said that the effect of controlling the moisture blocking property is different between the -SiN film and the amorphous Si film.

In other words, in the case of the P-SiN film, in exchange for the high blocking property of water, there is a side effect that the flatness of the reflow SiO ₂ film is degraded. There is the advantage that high blocking properties against moisture can be provided without side effects.

In addition, the amorphous Si used in the present invention
Since the film is a material that can be easily formed only by changing the supply type of the reaction gas in the same film forming chamber as the P-SiN film and the P-SiO film conventionally used as the base film,
The L process can be taken into the APL process without changing the whole image and without introducing a new film forming apparatus. That is, the structure of the present invention can be achieved by a method having good compatibility with the conventional process.

Next, an example of a method of manufacturing the structure shown in FIG. 1 will be described with reference to FIG. The APL process is performed in an APL device system as shown in FIG. First, a wafer, which needs to cover an element or a wiring formed on a semiconductor substrate and form an interlayer insulating film having good flatness, is introduced into the plasma reaction chamber 21 in the APL system.

The wafer is set on the susceptor of the plasma reaction chamber 21 evacuated to a vacuum set at 300 ° C., for example, by the transfer arm 23, and then a P-SiO film as a base film is formed by a plasma CVD method. . The conditions were as follows: gas flow rate: 150 cc for SiH4, 3500 cc for N2O,
N2 is discharged at 1500 cc, pressure of 1400 mm torr, and RF power of 100 W. Thus, a P-SiO film (12 in FIG. 1) having a thickness of 100 nm is formed as a base film. Here, the thickness of 100 nm is set in consideration of wiring density, wiring dimensions, and the like. As the miniaturization of semiconductor devices progresses, it is assumed that the setting will be about 150 nm or less.

Subsequently, the gas type is changed while the wafer is held at the same temperature on the same susceptor in the plasma reaction chamber 21. For example, 1500 cc for SiH _{4 and} 1 for N ₂
50 cc, H ₂ is 3000cc, pressure 1400 mm tor
r, RF power of 100 W, etc. The discharge is performed as it is to form an amorphous Si film (13 in FIG. 1) with a thickness of 100 nm. The thickness of 100 nm here is also set in consideration of the wiring density, the dimensions of the wiring, and the like as described above. As the miniaturization of semiconductor devices progresses, it is assumed that the setting will be about 150 nm or less.

Next, the wafer is once carried out of the plasma reaction chamber and transferred to the load lock chamber 25 while maintaining the back pressure at a vacuum degree (665 Pa or less). Subsequently, the wafer is carried into the APL chamber 27 and placed on a susceptor maintained at a temperature in the range of -10 ° C to + 10 ° C, preferably 0 ° C. Next, the wafer is appropriately held on the susceptor in an N ₂ atmosphere. During this holding time, the wafer is released from the residual heat from the previous 300 ° C. film formation to plasma processing. The wafer surface temperature drops stably to the reflow ensuring temperature region.

Next, SiH which is an actual APL film forming gas system is used.
_{4 + H 2 O 2 + N} 2 shifts gas is introduced into the flow stabilization phase. SiH4 is 10cc, H ₂ O ₂ is 0.65 / m
in, N ₂ is 500cc, pressure 850mm torr, a time of 10 seconds is typical conditions.

[0032] Then, film formation is started by increasing the 120cc only SiH4 (reflow SiO ₂ film 14 of FIG. 1).
After the completion of the film formation corresponding to 800 nm, all the introduced gases are exhausted and exhausted to the degree of vacuum of the back pressure. Next, the P-SiO film (15 in FIG. 1) serving as a cap film is again carried out of the APL chamber 27, again carried into the plasma reaction chamber 21 via the load lock chamber 25 via the load lock chamber 25, and subjected to the plasma CVD method. 30
0 nm is formed. Temperature and pressure are the same as that at the time of the base film, SiH ₄ is 100 cc, N2 O is 2000cc, N
2 is 1000 cc and RF power is 500 W. Thus, the film forming process in the APL device system is completed. Finally, the final heat treatment is performed at 450 ° C. for 30 minutes in another furnace annealing apparatus, and the process is completed.

According to the present invention, adverse effects such as corrosion and loss on aluminum wiring, which are remarkable when only the P-SiO film is used as the base film, and hot carrier reliability on the element itself are obtained. It is possible to avoid adverse effects such as deterioration of resistance.

As a conventional method of avoiding the above-mentioned adverse effects, when a base film of a P-SiN film is applied, there is a side effect that the flatness of a reflow SiO ₂ film is deteriorated. However, according to the present invention, such a side effect can be avoided, so that it is no longer necessary to add a flattening step.

FIG. 3 shows data relating to the former effect.
As an electrical characteristic evaluation in a test pattern of an aluminum wiring, an open failure rate and a wiring resistance distribution in a lower wiring in a two-layer aluminum wiring are shown. FIG. 4 shows a short-circuit failure rate distribution in the upper wiring pattern.

The verification samples shown in FIGS. 3 and 4 were prepared in the following procedure. After forming a base film on the lower aluminum wiring pattern, a reflow SiO ₂ film 800n
m, and a P-SiO film as a cap film of 300 n
m was formed. Thereafter, furnace annealing was performed at 450 ° C. for 30 minutes, and then through normal photolithography and etching steps, connection holes were formed in the lower aluminum wiring pattern, and an upper aluminum wiring pattern was formed thereon.

As the base film, a conventional P-SiO
The film and the P-SiN film were compared with each other by employing the laminated structure of the P-SiO film and the amorphous Si film having the structure of the present invention. The film thickness of the former is 200 nm and 500 n.
For m, the latter performed 100 nm each for a total of 200 nm.

The electrical characteristics of the lower aluminum wiring were measured before and after a furnace annealing at 450 ° C. for 30 minutes performed at the completion of the APL process. Since it is known in advance that the downward diffusion of moisture occurs during the funnel annealing, if there is a difference in the measurement results before and after annealing (if it deteriorates after annealing), it is considered to be the effect of downward diffusion of moisture.

On the other hand, the measurement of the electrical characteristics of the upper aluminum wiring pattern is necessarily limited after annealing from the above-described process order. The flatness of the reflow SiO ₂ film is reflected in the short-circuit failure rate in the upper wiring. That is, when the flatness of the reflow SiO ₂ film is good, the short-circuit failure rate shows an extremely low value. On the other hand, when the flatness of the reflow SiO ₂ film deteriorates, the short-circuit failure rate increases. Next, the obtained results will be described.

As is clear from FIG. 3, in the case of the P-SiO base film, which is one of the conventional structures, both the lower layer open defect rate and the wiring resistance are greatly increased after annealing at a film thickness of 200 nm. When the thickness is 500 nm, the degree is improved. Therefore, when a P-SiO film is used as the base film,
It can be determined that at least a film thickness of about 500 nm is necessary from the viewpoint of ensuring the diffusion blocking property under water. However, when a base film having a thickness of 500 nm is formed on the aluminum wiring, 500 nm is formed on both side walls of the aluminum pattern.
It becomes impossible for the _two films to fill the space between the aluminum patterns. That is, voids (voids) are generated between the aluminum patterns. Therefore, the process is outside the allowable range.

From the above, it can be seen that P-S
It can be concluded that there is no solution for the iO base film having an appropriate thickness. On the other hand, since the upper-layer wiring short-circuit failure rate in FIG. 4 is low,
It can be seen that the flatness of the reflow SiO ₂ film is good. In summary, in the configuration using the P-SiO film as the base film, the flatness of the reflow SiO ₂ film is good, but the diffusion blocking property under water is insufficient.

Next, P-Si, which is another of the conventional structures, is used.
In the case of the N base film, the open defect rate of the lower layer wiring is very low before and after annealing for both the film thicknesses of 200 nm and 500 nm, and no change is observed in the wiring resistance.
Can be seen from Therefore, in the P-SiN base film, the water downward diffusion blocking property is at a favorable level. However, as shown in FIG. 4, the short-circuit defect rate in the upper layer wiring is significantly increased. From this, reflow SiO ₂
It is presumed that the flatness of the film has deteriorated. Therefore P
In a configuration using a SiN film as a base film, it is essential to add a planarization step. This deviates from the purpose of the invention and is therefore still outside the permissible range of application.

Next, in the P-SiO film and the amorphous Si film laminated structure sample having the structure of the present invention, as can be seen from FIG. 3, the lower-layer wiring open defect rate before and after annealing is extremely low. Since no change is observed, the blockability of water downward diffusion is at a favorable level.

Further, from the low short-circuit defect rate of the upper wiring in FIG. 4, it is supposed that the flatness of the reflow SiO ₂ film is also good. Therefore, in the base film having the structure according to the proposed method, it is possible to achieve both good electrical characteristics for both the lower wiring and the upper wiring.

Next, FIG. 5 shows the result of performing hot carrier reliability in a MOS transistor in order to evaluate the influence of the downward diffusion of moisture on the element itself. Similar to the structure shown in FIGS. 3 and 4, three types of base films in the APL process were compared. As the base film, P-SiO is used as a conventional structure.
Each of the film and the P-SiN film was compared with each other by adopting a laminated structure of a P-SiO film and an amorphous Si film as a configuration of the present invention. The film thickness of the former two types is 200 n
m, the latter was performed at a total of 200 nm, each of 100 nm. The vertical axis shows the gain margin (in%), and the horizontal axis shows the stress time.

From FIG. 5, it can be seen that the hot carrier reliability is good when the P-SiN base film is used and when the P-SiO film is used as the base film. It is obvious that the degree of property deterioration is large. The advantage of the structure of the present invention is apparent from this evaluation.

In addition to the above-described embodiment, there is the following method for forming an insulating film having fluidity or self-flatness.
TEOS and O ₃ are reacted with each other at normal pressure to form a film. At this time, they are reacted with each other in a vacuum within a range of 200 torr to 700 torr. It is also conceivable to apply, dry and bake a coating material containing siloxane, which is a so-called SOG coating method.

In other words, in the case where the object of the present invention is to enhance the moisture blocking property to the lower side (wiring) by the amorphous Si film immediately below, the insulating film having the fluidity or the self-flatness on the amorphous Si film. This means that they do not care about the type and method of film formation.

Also, from the verification samples shown in FIGS. 3 and 4, even if the order of laminating the P-SiO film 12 and the amorphous Si film 13 in FIG. It is considered that this will not happen (see FIG. 6).

As shown in FIG. 7, a configuration in which only the amorphous Si film 17 is used as the base film can be considered. The thickness of the amorphous Si film 17 was 200 nm, for example, with the thickness of the P-SiO film 12 shown in FIG. By doing so, the number of steps for forming the P-SiO film is reduced, and the time is also reduced.

[0051]

As described above, according to the present invention,
An amorphous Si film that can enhance the downward diffusion blocking property of water without deteriorating the flatness of an insulating film having self-flatness (reflow insulating film) is used as a base film in forming the reflow insulating film. With this, AL
An interlayer insulating film structure that can avoid problems such as loss of wiring and deterioration of hot carrier reliability of an element is realized, and a highly reliable semiconductor device and a method of manufacturing the same can be provided even when miniaturization proceeds.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of an interlayer insulating film between multilayer wirings of a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an APL device system used in the present invention.

FIG. 3 is a characteristic diagram showing an open defect rate and a wiring resistance value in a lower aluminum wiring for evaluating the present invention.

FIG. 4 is a characteristic diagram showing a short-circuit defect rate in an upper aluminum wiring for evaluating the present invention.

FIG. 5 is a hot carrier reliability characteristic diagram of a MOS transistor for evaluating the present invention.

FIG. 6 is a sectional view showing the structure of a first modification of FIG. 1 according to another embodiment of the present invention.

FIG. 7 is a sectional view showing the structure of a second modification of FIG. 1 according to another embodiment of the present invention.

[Explanation of symbols]

10 ... Insulating film 11 ... Aluminum wiring 12,15 ... P-SiO film (SiO by plasma CVD method)
13, 17… Amorphous Si film 14… Reflow SiO2 film

Claims (12)

[Claims] An insulating film having fluidity or self-flatness formed on an uneven shape reflected by an element or a wiring formed on a semiconductor substrate; and an amorphous Si film existing immediately below the insulating film. A semiconductor device, comprising: a base film configured. 2. An insulating film having fluidity or self-flatness formed on an uneven shape reflected by an element or a wiring formed on a semiconductor substrate; and an amorphous Si film existing immediately below the insulating film. And a base film having a laminated structure of a plasma SiO ₂ film. 3. The semiconductor device according to claim 2, wherein the base film has a stacking order such that the amorphous Si film exists between the insulating film and the plasma SiO ₂ film, It is characterized by having a laminated structure in any of the lamination order such that the plasma SiO ₂ film exists between the Si films. 4. The semiconductor device according to claim 2, wherein the thickness of each of the amorphous Si film and the plasma SiO ₂ film is 150 nm or less. 5. A semiconductor device including a step of forming an insulating film having fluidity or self-flatness on an uneven shape reflected by an element or a wiring formed on a semiconductor substrate, wherein the insulating film is formed before the insulating film is formed. A step of forming a laminated structure of an amorphous Si film and a plasma SiO ₂ film as a base film of the insulating film, wherein the amorphous Si film and the plasma SiO ₂ film are evacuated at a temperature of 200 ° C. or more and 450 ° C. or less. A method for manufacturing a semiconductor device, wherein a film is continuously formed in a plasma CVD chamber held in a chamber. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the base film is formed in a stacking order of forming the amorphous Si film on the plasma SiO ₂ film, and the plasma is formed on the amorphous Si film. It is characterized by adopting one of the lamination structures in the lamination order of forming the SiO ₂ film. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the film formation in the plasma CVD chamber is performed using a single gas of SiH ₄ or S
iH ₄ + H ₂ gas is performed in a plasma atmosphere supplied as a main reactive gas, and for a plasma SiO 2 film, SiH ₄ + N ₂ O is performed in a plasma atmosphere supplied as a main reactive gas. Features. 8. The method for manufacturing a semiconductor device according to claim 5, wherein the step of depositing the insulating film having fluidity or self-flatness includes the step of depositing SiH ₄ gas and H ₂ O _2.
It is characterized in that they react with each other in a vacuum of 65 Pa or less within a temperature range of -10 ° C or more and + 10 ° C or less. 9. The method for manufacturing a semiconductor device according to claim 5, wherein the step of depositing the insulating film having fluidity or self-flatness includes reacting TEOS and O ₃ with each other at normal pressure. Semiconductor device manufacturing method. 10. The method for manufacturing a semiconductor device according to claim 5, wherein the step of depositing the insulating film having fluidity or self-flatness is performed by adding TEOS and O ₃ to 700 t.
It is characterized by reacting with each other in a vacuum of 200 torr or less. 11. The method for manufacturing a semiconductor device according to claim 5, wherein the step of depositing the fluid or self-flattening insulating film comprises applying, drying and baking a coating material containing siloxane. And 12. A semiconductor device including a step of forming an insulating film having fluidity or self-flatness on an uneven shape reflected by an element or a wiring formed on a semiconductor substrate, before forming the insulating film. A step of forming an amorphous Si film as a base film of the insulating film, wherein the amorphous Si film is formed in a plasma CVD chamber held in a vacuum at a temperature of 200 ° C. to 450 ° C. A method for manufacturing a semiconductor device, comprising: