JPH10232830A - 分散型タグ・キャッシュメモリシステムおよびそこにデータを格納する方法 - Google Patents

分散型タグ・キャッシュメモリシステムおよびそこにデータを格納する方法

Info

Publication number
JPH10232830A
JPH10232830A JP9325228A JP32522897A JPH10232830A JP H10232830 A JPH10232830 A JP H10232830A JP 9325228 A JP9325228 A JP 9325228A JP 32522897 A JP32522897 A JP 32522897A JP H10232830 A JPH10232830 A JP H10232830A
Authority
JP
Japan
Prior art keywords
cache
instruction address
instruction
tag
tag portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9325228A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10232830A5 (2
Inventor
William C Moyer
ウィリアム・シー・モイヤー
Wan Lee Lee
リー・ワン・リー
Arens John
ジョン・アレンズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPH10232830A publication Critical patent/JPH10232830A/ja
Publication of JPH10232830A5 publication Critical patent/JPH10232830A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
JP9325228A 1996-11-14 1997-11-11 分散型タグ・キャッシュメモリシステムおよびそこにデータを格納する方法 Pending JPH10232830A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US748856 1996-11-14
US08/748,856 US5920890A (en) 1996-11-14 1996-11-14 Distributed tag cache memory system and method for storing data in the same

Publications (2)

Publication Number Publication Date
JPH10232830A true JPH10232830A (ja) 1998-09-02
JPH10232830A5 JPH10232830A5 (2) 2005-07-07

Family

ID=25011225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9325228A Pending JPH10232830A (ja) 1996-11-14 1997-11-11 分散型タグ・キャッシュメモリシステムおよびそこにデータを格納する方法

Country Status (3)

Country Link
US (1) US5920890A (2)
JP (1) JPH10232830A (2)
KR (1) KR100470516B1 (2)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010066892A (ja) * 2008-09-09 2010-03-25 Renesas Technology Corp データプロセッサ及びデータ処理システム
JP2012221086A (ja) * 2011-04-06 2012-11-12 Fujitsu Semiconductor Ltd 情報処理装置
JP2015069649A (ja) * 2013-09-26 2015-04-13 晶心科技股▲ふん▼有限公司Ａｎｄｅｓ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏｒｐｏｒａｔｉｏｎ マイクロプロセッサ及びその命令ループキャッシュの使用方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
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US5983310A (en) * 1997-02-13 1999-11-09 Novell, Inc. Pin management of accelerator for interpretive environments
US6662216B1 (en) * 1997-04-14 2003-12-09 International Business Machines Corporation Fixed bus tags for SMP buses
US6247098B1 (en) * 1998-02-17 2001-06-12 International Business Machines Corporation Cache coherency protocol with selectively implemented tagged state
US6519684B1 (en) * 1999-11-23 2003-02-11 Motorola, Inc. Low overhead method for selecting and updating an entry in a cache memory
JP2001195302A (ja) * 1999-11-30 2001-07-19 Texas Instr Inc <Ti> 命令ループ・バッファ
US6963965B1 (en) 1999-11-30 2005-11-08 Texas Instruments Incorporated Instruction-programmable processor with instruction loop cache
US6950929B2 (en) * 2001-05-24 2005-09-27 Samsung Electronics Co., Ltd. Loop instruction processing using loop buffer in a data processing device having a coprocessor
US20040088682A1 (en) * 2002-11-05 2004-05-06 Thompson Ryan C. Method, program product, and apparatus for cache entry tracking, collision detection, and address reasignment in processor testcases
US8386712B2 (en) * 2006-10-04 2013-02-26 International Business Machines Corporation Structure for supporting simultaneous storage of trace and standard cache lines
US7934081B2 (en) * 2006-10-05 2011-04-26 International Business Machines Corporation Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
US20080250206A1 (en) * 2006-10-05 2008-10-09 Davis Gordon T Structure for using branch prediction heuristics for determination of trace formation readiness
KR101645003B1 (ko) * 2010-02-12 2016-08-03 삼성전자주식회사 메모리 제어기 및 그 메모리 제어기가 탑재된 컴퓨팅 장치
US10423423B2 (en) 2015-09-29 2019-09-24 International Business Machines Corporation Efficiently managing speculative finish tracking and error handling for load instructions
US10180839B2 (en) * 2016-03-04 2019-01-15 Silicon Laboratories Inc. Apparatus for information processing with loop cache and associated methods
US20240385944A1 (en) * 2023-05-19 2024-11-21 Zoho Corporation Private Limited Concurrency-enabled loop constructs using state variable mutation principle

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0614324B2 (ja) * 1986-05-02 1994-02-23 エムアイピ−エス コンピユ−タ− システムズ、インコ−ポレイテイド コンピユ−タシステム
US4763253A (en) * 1986-09-26 1988-08-09 Motorola, Inc. Microcomputer with change of flow
US5222224A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
JPH04127339A (ja) * 1990-09-19 1992-04-28 Hitachi Ltd キヤツシユメモリシステム
JPH0512119A (ja) * 1991-07-04 1993-01-22 Nec Corp キヤツシユメモリ回路
JPH06243036A (ja) * 1993-02-12 1994-09-02 Hitachi Ltd キャッシュ制御システム
JPH07160577A (ja) * 1993-12-10 1995-06-23 Matsushita Electric Ind Co Ltd キャッシュメモリ制御装置
US5510934A (en) * 1993-12-15 1996-04-23 Silicon Graphics, Inc. Memory system including local and global caches for storing floating point and integer data
US5749090A (en) * 1994-08-22 1998-05-05 Motorola, Inc. Cache tag RAM having separate valid bit array with multiple step invalidation and method therefor
JP3348367B2 (ja) * 1995-12-06 2002-11-20 富士通株式会社 多重アクセス方法および多重アクセスキャッシュメモリ装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010066892A (ja) * 2008-09-09 2010-03-25 Renesas Technology Corp データプロセッサ及びデータ処理システム
JP2012221086A (ja) * 2011-04-06 2012-11-12 Fujitsu Semiconductor Ltd 情報処理装置
JP2015069649A (ja) * 2013-09-26 2015-04-13 晶心科技股▲ふん▼有限公司Ａｎｄｅｓ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏｒｐｏｒａｔｉｏｎ マイクロプロセッサ及びその命令ループキャッシュの使用方法

Also Published As

Publication number Publication date
US5920890A (en) 1999-07-06
KR100470516B1 (ko) 2005-05-19
KR19980042269A (ko) 1998-08-17

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