JPH1023358A - Display device drive circuit - Google Patents

Abstract

(57) [Problem] To correct distortion of a display screen in a predetermined area of a display screen when an analog video signal source and a display screen have different aspect ratios. A sampling pulse generating circuit for generating sampling pulses P1, P2,... Pi,... Pm for sampling an analog video signal VS, and a clock having a plurality of frequencies within one horizontal period of the analog video signal VS. A clock control circuit 4 for generating the clock and supplying the clock to the sampling pulse generating circuit is provided. The analog video signal is directly sampled by the sampling pulse, and supplied to the signal electrode of the display panel 1 for input. A display distortion caused by a difference in aspect ratio between the VS and the display screen can be corrected in a desired area of the display screen.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device driving circuit in which source lines and gate lines are arranged in a matrix, and more particularly, to a display screen having a different aspect ratio between a video signal source and a display device. The present invention relates to a drive circuit of a display device which makes it easy to see a display screen when a ratio is converted.

[0002]

2. Description of the Related Art Conventionally, as a display device in which source lines and gate lines are arranged in a matrix, for example, there is a TFT liquid crystal display device. This TFT liquid crystal display device has a plurality of source lines B1, B2,... Bi,.
And a plurality of gate lines A1, A2,
.. Aj,... An, and at the intersection, via a TFT,
A liquid crystal station is provided, and picture elements are formed at each intersection. And
The driving circuit of this TFT liquid crystal display device is provided with the source line B
Source line drive circuit 2 for driving 1, B2,... Bi,.
, Aj,... An for driving the gate lines A1, A2,.

The source line driving circuit 2 shifts a start pulse by a clock signal to generate a sampling pulse, samples a video signal by the sampling pulse, holds the sampled video signal, and
... Bm are supplied to the source lines B1, B2,.

The gate line driving circuit 3 sequentially selects the gate lines A1, A2,... Aj,... An in synchronization with the horizontal synchronizing signal of the video signal. The source lines B1, B2,... Bi,... Bm are connected to the sources of the TFTs arranged close to the respective source lines, and the gate lines A1, A2,.
.. An,... An are TFs arranged close to each gate line.
The drain of each TFT is connected to a picture element electrode, and a liquid crystal layer is provided between each picture element electrode and the common electrode.

When the input video signal is a standard NTSC signal having an aspect ratio of 4: 3, the aspect ratio of the TFT liquid crystal display device is also set to 4: 3. If the number of horizontal lines is 320 pixels (1 pixel = 3 dots), the horizontal effective display time T _{H is set} to T _H = 52.75 μs.
When the symbol is displayed, a perfect circle can be displayed for a perfect circle of the input video signal.

Therefore, the input clock frequency of the source line drive circuit 2 is set to (320 × 3) / T _H = 18.2 MHz. However, when the source line drive circuit 2 performs the sampling operation at the rising and falling edges of the input clock, the input clock frequency is 18.2 / 2 = 9.1 M
Hz.

[0007]

The prior art described above is intended for a case where only a standard NTSC signal represented by a perfect circle having an aspect ratio of 4: 3 is input.
In addition, it is assumed that the display aspect ratio of the display device is 4: 3 in accordance with the NTSC signal. However, as an example, let us input and display the above-mentioned standard NTSC signal on a display device having a display section configured with a wide accept ratio (horizontal: vertical ratio = 16: 9), which is becoming mainstream in recent years. Then, the display is stretched in the horizontal direction.

FIG. 3 simulates the linearity when a video signal having an aspect ratio of 4: 3 is displayed on a display device having an aspect ratio of 4: 3. In the figure, a first quadrant is a display image of a display device,
The second quadrant is a display signal source (vertical), the third quadrant is a display signal source (horizontal), and the fourth quadrant is an aspect ratio conversion between a video signal and a display device determined by a sampling clock XSC of a source line driving circuit. Rate, where the slope is 1
The frequency of the sampling clock XSC is determined so that

In the first and second quadrants, X
The axis and the Y axis indicate the horizontal display position and the vertical display position, respectively, and the Y axis in the third and fourth quadrants indicates the number of horizontal lines (sampling count n). In this case, an image of a perfect circle is displayed as shown in the first quadrant for a video signal of a perfect circle as shown in the second and third quadrants.

On the other hand, FIG. 4 shows a simulation in which a perfect circular video signal having an aspect ratio of 4: 3 is displayed as an example on a display device having an aspect ratio of 16: 9. In this case, the frequency of the sampling clock XSC shown in the fourth quadrant has an aspect ratio of 4: 3.
Is determined so as to have a conversion rate necessary to display the video signal on a display screen having an aspect ratio of 16: 9. As is apparent from the figure, although the input video signal is a perfect circle, the displayed video becomes elliptical as shown in the first quadrant, and the display quality is impaired.

The present invention has been made in view of such circumstances, and it is an object of the present invention to perform signal processing of an NTSC signal on a transmission side in the conventional manner, and to adjust the display aspect ratio of a display device to a standard. Even if the aspect ratio of the NTSC signal is different (4: 3), the display quality is improved by approaching a perfect circle at the center of the screen and stretching it at both ends of the screen.

[0012]

A driving circuit for a display device according to the present invention is provided near a plurality of source lines, a plurality of gate lines crossing the source lines, and a crossing of the source lines and the gate lines. A plurality of picture element electrodes, and a driving circuit of a display device comprising a display body provided to face the picture element electrodes,
A source line driving circuit for supplying a display signal to the source line based on an input analog video signal, a gate line driving circuit for supplying a scanning signal to the gate line, and the analog video inputted to the source line driving circuit A sampling clock generating circuit for generating a sampling clock for sampling a signal, the sampling clock generating circuit including a sampling clock switching circuit capable of switching the frequency of the sampling clock within one horizontal time; It is characterized by having been provided.

Accordingly, the analog video signal supplied to the source line driving circuit is sampled n times for each horizontal line by the sampling clock supplied from the sampling clock generating circuit, and the n sampled video signals are sampled. Are supplied to the corresponding source lines of the n source lines. On the other hand, a scanning signal synchronized with the horizontal synchronizing signal of the video signal is output from the gate line driving circuit, and the scanning signal is sequentially supplied to the plurality of gate lines. As a result, a signal corresponding to the input video signal is supplied to each of the plurality of picture element electrodes, and the display device as a whole displays a display image corresponding to the input video signal.

When the aspect ratio of the video signal is equal to the aspect ratio of the display screen, the frequency of the sampling clock generated by the sampling clock generating circuit is set so that the perfect circle of the video signal is displayed on the screen of the display device as a perfect circle. Set to a constant value. If the aspect ratio of the video signal is different from the aspect ratio of the display screen, so that the perfect circle of the video signal can be displayed as a perfect circle at a desired position on the display screen,
The sampling clock switching circuit switches the frequency of the sampling clock within one horizontal period at an appropriate timing corresponding to the desired position.

For example, when a video signal having an aspect ratio of 4: 3 is displayed on the entire display screen having an aspect ratio of 16: 9, a sampling clock switching circuit is used to prevent image distortion at the center of the screen. The sampling clock at a position corresponding to the center of the screen is switched within one horizontal period.

In this area, the sampling clock frequency is set so that a perfect circle of the video signal can be displayed as a perfect circle on the display screen. In the other areas on both sides of the screen, the remaining part of the video signal is The sampling clock frequency is set so as to allow a screen distortion such that a perfect circle of the video signal is displayed as an ellipse on the display screen. As a result, the perfect circle of the video signal having the aspect ratio of 4: 3 is displayed as a perfect circle at the center on the display screen having the aspect ratio of 16: 9 and an ellipse at both sides, and the center is displayed at the center. The quality of the displayed image can be improved to make the screen easy to see.

According to a second aspect of the present invention, there is provided a driving circuit for a display device, wherein the sampling clock generating circuit of the driving circuit for the display device includes a voltage controlled oscillator for generating a sampling clock, and a component for dividing the output of the voltage controlled oscillator. A frequency divider, a control circuit for controlling the frequency division ratio of the frequency divider, an oscillator for generating a signal of the original oscillation frequency, and comparing the output of the frequency divider with the output of the oscillator according to the comparison value. A signal is formed by a feedback circuit that feeds back a signal to the voltage controlled oscillator, and the oscillation frequency of the voltage controlled oscillator can be changed within one horizontal period.

According to the present invention, the sampling clock output from the voltage controlled oscillator is divided by the frequency divider, compared with the original oscillation frequency from the oscillator, and a signal corresponding to the comparison value is output from the voltage controlled oscillator. When the frequency division ratio of the frequency divider is controlled by the control circuit, the frequency of the sampling clock output from the voltage controlled oscillator can be changed. Therefore, the frequency of the sampling clock at a desired position in one horizontal period of the video signal can be changed by the control circuit,
It is possible to correct display distortion at a desired position on the display screen due to a difference in aspect ratio between the video signal and the display screen.

Further, according to the drive circuit for a display device of the present invention, in the drive circuit for a display device described above, when the frequency of the sampling clock is switched within one horizontal period by the sampling clock switching circuit, the frequency is switched. Characterized in that a low-pass filter circuit for smoothing the changing point of the filter by the response characteristic of the filter is provided.

According to the present invention, when the frequency of the sampling clock is switched within one horizontal period by the sampling clock switching circuit, the low-pass filter circuit is provided, so that the filter response characteristic of the low-pass filter circuit is provided. Accordingly, a sharp change at the time of switching the sampling clock frequency is reduced, and the display distortion can be smoothly corrected in a desired area of the display screen.

According to a second aspect of the present invention, there is provided a driving circuit for a display device, wherein the aspect ratio of the display device is 16: 9.

According to the present invention, since the aspect ratio of the display device is 16: 9, even when a standard NTSC signal widely used as a video signal is input, the clock frequency of the sampling clock within one horizontal period is obtained. Is switched in a desired region, the display distortion of the screen in this region can be corrected.

According to a second aspect of the present invention, in the above-described display device driving circuit, an aspect ratio of the display device is different from an aspect ratio of a signal source of the analog video signal.

According to the present invention, since the aspect ratio of the display device is different from the aspect ratio of the signal source of the analog video signal, the frequency of the sampling clock within one horizontal period is appropriately switched to cause distortion on the display screen. The frequency of the sampling clock in the region not to be determined is set to a value such that the video signal of a perfect circle becomes a perfect circle on the display screen,
The frequency of the sampling clock in the other area within one horizontal period is set appropriately while allowing display distortion.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. The present invention is applied to a drive circuit of a display device in which a source line and a gate line are arranged in a matrix, and an intersection thereof is a picture element.
As an example, a case where the present invention is applied to a driving circuit of a TFT liquid crystal display device will be described. FIG. 1 is a block diagram in that case.

In FIG. 1, reference numeral 1 denotes m source lines B1,
.. Bm, and n gate lines A1, A2,... Aj,... An that are orthogonal to the source line. A liquid crystal station is provided at the intersection through a TFT. This is a TFT liquid crystal display panel in which elements are formed. 2 is a source line driving circuit for supplying a driving signal to each of the source lines B1, B2,... Bi,... Bm of the TFT liquid crystal display panel 1, and 3 is sequentially connected to the gate lines A1, A2,. This is a gate line driving circuit that supplies a gate line driving signal for scanning.

The source line driving circuit 2 includes a shift register 21, a sample and hold circuit 22, and a hold circuit 2.
3 is provided. The shift register 21 shifts the shift pulse XSP according to the clock XSC, and sequentially shifts the sampling pulses P to the lines L1, L2,.
1, P2,... Pi,.

The sampling pulses P1, P2,... P
, Pm are analog switches ASW11, ASW12,... ASW1i,.
, The analog switches are sequentially turned on, and the sampling capacitors C11, C12,.
.. Sequentially charge the instantaneous amplitude VS (i, j) of the analog video signal VS input to C1m.

Here, the instantaneous amplitude VS (i, j) of the analog video signal VS is applied to the pixel electrode corresponding to the intersection of the i-th source line Bi and the j-th gate line Aj of the TFT display panel 1. This is the instantaneous amplitude of the analog video signal VS to be written.

As described above, the video signal for one horizontal scanning period is sampled by the sampling pulses P1, P2,... Pi,... Pm, and the sampling capacitors C11, C12,.
When the charging is performed sequentially to 1 m, an output pulse OE is supplied to the hold circuit 23.

As a result, the analog switches ASW21, ASW22,... ASW2i,.
W2m is closed all at once, and the sampling capacitor C
, C1m,... C1m are charged to the hold capacitors C21, C22,.
Transferred to 2m and held. Hold capacitor C21,
The video signals held in C22,... C2i,... C2m are output to the corresponding source lines B1, B2,.

The outline of the input / output signal waveform in each section of the source line drive circuit 2 is as shown in FIG. In FIG. 2, V (C1i), V (C2i) and V (i) are connected to the source of the TFT via the voltage of the sampling capacitor C1i, the voltage of the hold capacitor C2i, and the output buffer for the i-th source line Bi, respectively. The applied voltage is shown. It is necessary to invert the polarity of the video signal VS every one horizontal cycle and to make it AC, and as shown in FIG. 2, the phase of the signal is inverted by 180 ° in the adjacent horizontal period.

The gate line driving circuit 3 synchronizes the shift pulse YSP with the clock YSC in synchronization with the horizontal synchronizing signal of the video signal.
, And a scanning signal synchronized with the horizontal synchronizing signal of the video signal is supplied to the gate lines A1, A2,.
The TFTs connected to the same gate line are turned on for each line.

Next, the clock control circuit 4 for switching the clock XSC used for the shift register 21 of the source line driving circuit 2 and switching the frequency of the sampling pulses P1, P2,... Pi,. Reference numeral 41 denotes a voltage controlled oscillator (VCO) that oscillates at a frequency corresponding to the DC voltage value applied to the input side, and the sampling pulses P 1, P 1 are supplied to the shift register 21 of the source line driving circuit 2.
2,... Pi,... Pm.

The voltage controlled oscillator 41 is required to have oscillation characteristics with good linearity between the control signal N and the oscillation frequency f ₀ as shown in FIG. Here, the control signal N is
This is the frequency division ratio of the frequency divider 42. The frequency divider 42 divides the output signal of the voltage controlled oscillator 41 by N times by the control signal N from the control circuit 43, and N = n
By changing the control signal N from the control circuit 43, such as 1, n2, n3,...

The output f ₁ of the frequency divider 42 is supplied to the next-stage frequency comparator 44 and compared with the oscillation frequency f ₀ from the oscillator 45. Since the oscillation frequency f ₀ is a reference for producing the sampling pulses P 1, P 2,... Pi,... Pm, the oscillator 45 must normally perform stable oscillation by a quartz oscillator or the like.

The frequency comparator 44 compares the output f ₁ of the frequency divider 42 with the oscillation frequency f ₀ of the oscillator 45, outputs an error signal including a high frequency corresponding to the frequency difference, and outputs a low-pass filter 46. To enter. The low-pass filter 46 is a DC voltage V from which high-frequency components contained in the error signal have been removed.
d is derived and supplied to the voltage controlled oscillator 41 as the control voltage Vd. The voltage control oscillator 41 derives an output of the frequency f _CLD according to the control voltage Vd, and supplies the output as the clock XSC to the shift register 21.

As an example of partially correcting a screen distortion due to a difference in an aspect ratio between an input video signal and a display screen, for example, a sampling clock of a sampling clock is provided at a central portion and a peripheral portion of one horizontal period of the display screen. The case of changing the frequency will be described. In each horizontal period of the input analog video signal VS, the frequency f _{CLD of the} clock XSC is shown in FIG.
And f ₁ in the right and left ends as shown in, to be a f ₂ at the center. For this purpose, first, the analog video signal VS
At t = t ₀ , the control signal N from the control circuit 43 is set to N = n 1, the dividing ratio N of the frequency divider 42 is set to N = n 1, and then at t = t ₁ The dividing ratio N is set to N = n2.

As a result, the frequency f of the clock XSC
_{CLD is, f CLD = N · f 0} N = n1, n2, ... f 0: Since the oscillation frequency of the oscillator 45, the elapsed time within one horizontal period corresponds to the screen end portion between t ₀ ~t ₁ the region, the frequency f _CLD clock XSC is, f _CLD = n1f _0, and the center of the screen between t ₂ ~t ₃ after a lapse of transient time of switching the frequency between t ₁ ~t ₂ In the corresponding area, the frequency f _{CLD of the} clock XSC is f _CLD = n2f _0, and the frequency f _CLD of the clock XSC is f ₂ = n 2f ₀ and f ₁ = at the center and at the end of the screen.
It can be switched to n1f _0.

In a transitional region where the frequency between the times t _{1 and} t ₂ in one horizontal period changes from f _{1 to} f ₂ , a discontinuous portion occurs at the switching point. By optimizing the response characteristics of the filter 46, the discontinuous portion at the boundary portion can be smoothly changed, and the screen display of this portion can be changed in a natural manner without discomfort.

[0041] 1 when the elapsed time t in the horizontal period is a control signal N of the control circuit 43 to return the frequency f _CLD again clock XSC at time t = t ₃ to f ₁ to N = n1, in the same manner as described above Te, after a lapse of t ₃ ~t transient time frequency is switched between _4, at time t = t _4, said frequency f _CLD returns to f _1, said transient time t ₃ ~t _Four
The frequency f _CLD of the clock XSC smoothly changes from f ₂ to f ₁ .

When the above control is repeated for each horizontal period of the input analog video signal VS, the sampling pulse P
As for i, the frequency f _CLD becomes f ₂ in the center area of the screen, and f _{1 in} the other end areas of the screen, and changes smoothly at the boundary. FIG. 6 is a timing chart showing the relationship between the signal waveforms in one horizontal period described above.

FIG. 7 shows an example of a specific structure of the low-pass filter 46. The active circuit controls the output of a frequency comparator 44 used as a phase comparator based on a signal from a control circuit 47. A low-pass filter is configured to optimize the switching of the frequency f _CLD of the clock XSC.

In FIG. 7, the output of the frequency comparator 44 is supplied to the input of an operational amplifier 48 via a resistor R 1, the difference from the reference voltage VS is amplified, and the output is supplied to the voltage controlled oscillator 41. A capacitor C1, a capacitor C2 and a resistor R1 are connected between the input and output of the operational amplifier 48.
And a series circuit of resistors R2 and R3 are provided. An FET controlled by the control circuit 47 is provided at a connection point between the resistors R2 and R3.

The active low-pass filter shown in FIG. 7 functions to remove a harmonic component contained in the output signal from the frequency comparator 44, and the gain A in the low band is represented by the following equation. A = − {(R2 + R3) + R2 × R3 / Rd} / R1 Here, the operational amplifier 48 functions as an inverting amplifier, VS is a reference voltage of the operational amplifier 48, and Rd is an equivalent resistance between the source and the drain of the FET. The equivalent resistance Rd of this FET changes according to the control voltage from the control circuit 47, and varies the gain of the active low-pass filter.

Therefore, the control circuit 47 changes the equivalent resistance Rd of the FET and changes the gain of the operational amplifier 48 in synchronization with the change of the frequency f _CLD of the clock XSC by the control circuit 43. The characteristics of the low-pass filter 46 composed of an active low-pass filter change, and the discontinuity of the change point when the frequency f _CLD of the clock XSC is switched can be eliminated.

FIG. 8 is a simulation for displaying a video signal having an aspect ratio of 4: 3 on a display device having an aspect ratio of 16: 9. In the case where the frequency f _CLD of the clock XSC is switched from f ₁ to f ₂ in the left and right end regions and the center region of the display screen described with reference to FIG. 6, and the switching is performed smoothly by the low-pass filter 46 at the time of switching. The display method is the same as in FIGS. 3 and 4. As is clear from FIG. 8, a perfect circle display is obtained at the center of the screen, and a perfect circle is not obtained and the displayed image is distorted toward the right and left sides.
_No discontinuity occurs at the time of switching the _CLD , so that the display does not give a sense of incongruity.

[0048]

As described above, according to the present invention,
Even when the aspect ratio is different between the signal source and the display device, by switching the video sampling clock of the source driver without digitally processing the video signal, the display distortion can be reduced in a desired area such as the center of a horizontal screen. It is possible to display a perfect circle without any color, and to improve the display quality. Further, the change point at which the frequency of the clock is changed can be smoothed by optimizing the response speed of the low-pass filter, and a display screen without a sense of incongruity can be provided.
As described above, it is not necessary to individually design the display device according to the aspect ratio of the signal source unlike the related art, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart used for explaining the operation of the present invention.

FIG. 3 is a simulation diagram of a display image used for explaining the operation of the present invention.

FIG. 4 is a simulation diagram of a display image used for explaining the operation of the present invention.

FIG. 5 is an output characteristic diagram of the voltage controlled oscillator used in the present invention.

FIG. 6 is a timing chart used to explain the operation of the present invention.

FIG. 7 is a circuit diagram of a main part of the present invention.

FIG. 8 is a simulation diagram of a display image used for explaining the operation of the present invention.

FIG. 9 is a conventional block diagram.

[Explanation of symbols]

 Reference Signs List 1 display panel 2 source line drive circuit 3 gate line drive circuit 4 clock control circuit 21 shift register 22 sample hold circuit 23 hold circuit 41 voltage controlled oscillator 42 frequency divider 43 control circuit 44 frequency comparator 45 oscillator 46 low-pass filter 47 Control circuit 48 Operational amplifier A1, A2,... Aj,... An Gate line B1, B2,... Bi,.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 3/223 H04N 3/223

Claims (5)

[Claims] A plurality of source lines; a plurality of gate lines intersecting the source lines; a plurality of pixel electrodes provided in the vicinity of intersections of the source lines and the gate lines; And a source line drive circuit for supplying a display signal to the source line based on an input analog video signal, and a scan signal for supplying a scan signal to the gate line. A gate line driving circuit; and a sampling clock generating circuit for generating a sampling clock for sampling the analog video signal input to the source line driving circuit, wherein the sampling clock generating circuit has a frequency of the sampling clock. Wherein the sampling clock switching circuit is provided so as to be able to switch within one horizontal time. Drive circuit. 2. The sampling clock generating circuit according to claim 1,
A voltage-controlled oscillator that generates a sampling clock, a frequency divider that divides the output of the voltage-controlled oscillator, a control circuit that controls a frequency division ratio of the frequency divider, and an oscillator that generates a signal of the original oscillation frequency. A feedback circuit that compares the output of the frequency divider with the output of the oscillator and feeds back a signal corresponding to the comparison value to the voltage controlled oscillator, and changes the oscillation frequency of the voltage controlled oscillator within one horizontal period. 2. The driving circuit for a display device according to claim 1, wherein the driving circuit is configured to be able to perform the driving. 3. A low-pass filter circuit for smoothing a change point of the frequency switching by a response characteristic of the filter when the frequency of the sampling clock is switched within one horizontal period by the sampling clock switching circuit. The driving circuit for a display device according to claim 1, wherein: 4. An aspect ratio of the display device is 16: 9.
4. The driving circuit for a display device according to claim 1, wherein: 5. The driving circuit for a display device according to claim 1, wherein an aspect ratio of the display device is different from an aspect ratio of a signal source of the analog video signal.