JPH10247717A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH10247717A
JPH10247717A JP9048664A JP4866497A JPH10247717A JP H10247717 A JPH10247717 A JP H10247717A JP 9048664 A JP9048664 A JP 9048664A JP 4866497 A JP4866497 A JP 4866497A JP H10247717 A JPH10247717 A JP H10247717A
Authority
JP
Japan
Prior art keywords
signal terminal
semiconductor device
lead frame
package
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9048664A
Other languages
Japanese (ja)
Inventor
Hidetoshi Ishida
秀俊 石田
Kazuo Miyatsuji
和郎 宮辻
Daisuke Ueda
大助 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP9048664A priority Critical patent/JPH10247717A/en
Priority to CNB981052975A priority patent/CN1154182C/en
Priority to US09/033,240 priority patent/US6166429A/en
Publication of JPH10247717A publication Critical patent/JPH10247717A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/261—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions
    • H10W42/265—Shielding wires, e.g. constant potential wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【課題】 半導体装置のパッケージを小型化し、かつ、
信号端子電極の電気的分離性を向上させる。 【解決手段】 半導体装置のパッケージ１の中央部にリ
ードフレーム２、周辺部に信号端子電極３ないし信号端
子電極７を配設し、リードフレーム２上に半導体チップ
８を搭載し、信号端子電極４および信号端子電極５の間
に接地電位を有する接地電極１６、信号端子電極５およ
び信号端子電極６の間に接地電位を有する接地電極１７
をそれぞれ配設する。 [PROBLEMS] To reduce the size of a semiconductor device package, and
Improve the electrical isolation of the signal terminal electrode. SOLUTION: A lead frame 2 is provided at a central portion of a package 1 of a semiconductor device, a signal terminal electrode 3 to a signal terminal electrode 7 are provided at a peripheral portion, a semiconductor chip 8 is mounted on the lead frame 2, and a signal terminal electrode 4 is provided. And a ground electrode 16 having a ground potential between the signal terminal electrodes 5, and a ground electrode 17 having a ground potential between the signal terminal electrodes 5 and 6.
Are arranged respectively.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、高周波デバイスを
格納したパッケージを有する半導体装置に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a package containing a high-frequency device.

【０００２】[0002]

【従来の技術】近年、携帯電話、ＰＨＳをはじめとする
移動体通信端末の小型化が要望されている。そのため、
移動体通信端末に使用される半導体装置のパッケージを
縮小化することが考えられる。2. Description of the Related Art In recent years, there has been a demand for miniaturization of mobile communication terminals such as portable telephones and PHSs. for that reason,
It is conceivable to reduce the size of a semiconductor device package used for a mobile communication terminal.

【０００３】まず、従来の半導体装置について説明す
る。図５は、高周波で動作する半導体チップを格納した
６ピンミニパッケージを有する従来の半導体装置の平面
図である。図５においてパッケージ１上の中央部には、
リードフレーム２、周辺部には信号端子電極３ないし信
号端子電極７が配設され、リードフレーム２上には半導
体チップ８が搭載されている。また、半導体チップ８上
に設けられたチップ電極９ないしチップ電極１３は、ワ
イヤー１５によって信号端子電極３ないし信号端子電極
７にそれぞれ接続され、半導体チップ８上に設けられた
チップ電極１４は、ワイヤー１５によってリードフレー
ム２に接続されている。隣接する信号端子電極４と信号
端子電極５との間隔および信号端子電極５と信号端子電
極６との間隔はそれぞれ０．５ｍｍである。First, a conventional semiconductor device will be described. FIG. 5 is a plan view of a conventional semiconductor device having a 6-pin mini-package storing a semiconductor chip operating at a high frequency. In FIG. 5, in the central part on the package 1,
A signal terminal electrode 3 to a signal terminal electrode 7 are arranged on the lead frame 2 and a peripheral portion, and a semiconductor chip 8 is mounted on the lead frame 2. The chip electrodes 9 to 13 provided on the semiconductor chip 8 are respectively connected to the signal terminal electrodes 3 to 7 by wires 15, and the chip electrodes 14 provided on the semiconductor chip 8 are connected to wires 15 is connected to the lead frame 2. The distance between the adjacent signal terminal electrodes 4 and 5 and the distance between the signal terminal electrodes 5 and 6 are each 0.5 mm.

【０００４】[0004]

【発明が解決しようとする課題】上記従来の半導体装置
において、パッケージの大きさを縮小化するためには、
信号端子電極４および信号端子電極５のように、隣接す
る２つの信号端子電極どうしの間隔を狭くすることが考
えられる。In the above-mentioned conventional semiconductor device, in order to reduce the size of the package,
As in the case of the signal terminal electrode 4 and the signal terminal electrode 5, it is conceivable to reduce the distance between two adjacent signal terminal electrodes.

【０００５】一方、半導体装置を高周波で動作させる場
合、信号端子電極どうしの電気的分離性、すなわちアイ
ソレーションを高く保つことが必要であるので、隣接す
る信号端子電極どうしの間隔を一定値以上としなければ
ならない。−３０ｄＢのアイソレーションを得るために
は、信号端子電極どうしの間隔を０．５ｍｍ以上とする
必要がある。On the other hand, when the semiconductor device is operated at a high frequency, it is necessary to maintain high electrical isolation between signal terminal electrodes, that is, high isolation. Therefore, the interval between adjacent signal terminal electrodes is set to a certain value or more. There must be. In order to obtain an isolation of −30 dB, the interval between the signal terminal electrodes needs to be 0.5 mm or more.

【０００６】したがって、上記半導体装置においては、
パッケージの小型化と信号端子電極のアイソレーション
の向上とを同時に満たすことができなかった。Therefore, in the above semiconductor device,
The miniaturization of the package and the improvement of the isolation of the signal terminal electrode cannot be satisfied at the same time.

【０００７】本発明は、パッケージのサイズが小さく、
かつ、信号端子電極のアイソレーションが高い半導体装
置を提供することを目的とする。According to the present invention, the package size is small,
It is another object of the present invention to provide a semiconductor device having high isolation of signal terminal electrodes.

【０００８】[0008]

【課題を解決するための手段】本発明の半導体装置は、
パッケージ上の中央部にリードフレーム、パッケージ上
の周辺部に複数の信号端子電極がそれぞれ配設され、リ
ードフレーム上に半導体チップが搭載され、隣り合う２
つの信号端子電極の間に、接地電位を有する接地電極が
配設されたもの、およびパッケージ上の中央部にリード
フレーム、パッケージ上の周辺部に複数の信号端子電極
がそれぞれ配設され、リードフレーム上に半導体チップ
が搭載され、リードフレーム上の中央部に、接地電位を
有する架橋状の導電線が、半導体チップ上を横切るよう
に配設されているものであり、これにより、信号端子電
極どうしが互いに電気的に遮蔽される。According to the present invention, there is provided a semiconductor device comprising:
A lead frame is provided at a central portion on the package, a plurality of signal terminal electrodes are provided at a peripheral portion on the package, and a semiconductor chip is mounted on the lead frame.
A ground electrode having a ground potential is provided between two signal terminal electrodes, and a lead frame is provided at a central portion on the package, and a plurality of signal terminal electrodes are provided at a peripheral portion on the package, respectively. A semiconductor chip is mounted on the semiconductor chip, and a bridge-shaped conductive line having a ground potential is disposed in a central portion on the lead frame so as to cross over the semiconductor chip. Are electrically shielded from each other.

【０００９】[0009]

【発明の実施の形態】以下、本発明の実施の形態につい
て説明する。Embodiments of the present invention will be described below.

【００１０】（実施の形態１）図１は、本発明の実施の
形態１における半導体装置の平面図である。(First Embodiment) FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

【００１１】図１において、パッケージ１上の中央部に
は、リードフレーム２、周辺部には、信号端子電極３な
いし信号端子電極７が配設され、リードフレーム２上に
は半導体チップ８が搭載されている。また、半導体チッ
プ８上にはチップ電極９ないしチップ電極１４が設けら
れており、チップ電極９ないしチップ電極１３は、ワイ
ヤー１５によって信号端子電極３ないし信号端子電極７
にそれぞれ接続され、チップ電極１４はワイヤー１５に
よってリードフレーム２に接続されている。信号端子電
極４と信号端子電極５との間には、接地電位を有し、リ
ードフレーム２と一体形成された接地電極１６が配設さ
れている。同様に、信号端子電極５と信号端子電極６と
の間には、接地電極１７が配設されている。In FIG. 1, a lead frame 2 is provided at a central portion on a package 1, a signal terminal electrode 3 to a signal terminal electrode 7 are provided at a peripheral portion, and a semiconductor chip 8 is mounted on the lead frame 2. Have been. Further, chip electrodes 9 to 14 are provided on the semiconductor chip 8, and the chip electrodes 9 to 13 are connected to the signal terminal electrodes 3 to 7 by wires 15.
, And the chip electrode 14 is connected to the lead frame 2 by a wire 15. A ground electrode 16 having a ground potential and formed integrally with the lead frame 2 is provided between the signal terminal electrode 4 and the signal terminal electrode 5. Similarly, a ground electrode 17 is provided between the signal terminal electrode 5 and the signal terminal electrode 6.

【００１２】次に、上記半導体装置の動作について説明
する。信号端子電極４から入力された信号はワイヤー１
５およびチップ電極１０を伝搬し、半導体チップ８内で
増幅、減衰などの処理を受け、チップ電極１１およびワ
イヤー１５を経由して信号端子電極５から出力される。
このとき、信号端子電極４と信号端子電極５との間に、
接地電位を有する接地電極１６が配設されているため
に、信号端子電極４から発生する電磁波が遮蔽され、信
号端子電極５は、信号端子電極４で発生する電磁波の影
響を受けにくい。同様に、信号端子電極５で発生する電
磁波も、接地電極１６によって遮蔽される。この結果、
信号端子電極４と信号端子電極５とのアイソレーション
が良好になる。Next, the operation of the semiconductor device will be described. The signal input from the signal terminal electrode 4 is the wire 1
5, undergoes processing such as amplification and attenuation in the semiconductor chip 8, and is output from the signal terminal electrode 5 via the chip electrode 11 and the wire 15.
At this time, between the signal terminal electrode 4 and the signal terminal electrode 5,
Since the ground electrode 16 having the ground potential is provided, the electromagnetic wave generated from the signal terminal electrode 4 is shielded, and the signal terminal electrode 5 is hardly affected by the electromagnetic wave generated at the signal terminal electrode 4. Similarly, the electromagnetic wave generated at the signal terminal electrode 5 is also shielded by the ground electrode 16. As a result,
The isolation between the signal terminal electrode 4 and the signal terminal electrode 5 is improved.

【００１３】図２は、従来の半導体装置（曲線ａ）およ
び実施の形態１における半導体装置（曲線ｂ）の周波数
とアイソレーションとの関係を示したものである。図２
から明らかなように、接地電極１６、１７を有する実施
の形態１における半導体装置は、従来の半導体装置より
も電気的分離性が向上していることがわかる。FIG. 2 shows the relationship between the frequency and the isolation of the conventional semiconductor device (curve a) and the semiconductor device (curve b) in the first embodiment. FIG.
As is clear from FIG. 5, the semiconductor device according to the first embodiment having the ground electrodes 16 and 17 has improved electrical isolation compared to the conventional semiconductor device.

【００１４】上記実施の形態１では、６端子のパッケー
ジの例について説明したが、さらに多端子化されたパッ
ケージについても同様の効果が得られる。In the first embodiment, an example of a package having six terminals has been described. However, a similar effect can be obtained with a package having more terminals.

【００１５】（実施の形態２）図３は、本発明の実施の
形態２における半導体装置の平面図である。(Embodiment 2) FIG. 3 is a plan view of a semiconductor device according to Embodiment 2 of the present invention.

【００１６】実施の形態２における半導体装置は、接地
電極１６、１７を有していない点およびリードフレーム
２上の中央部には、接地電位を有し、半導体チップ８の
上を横切るような架橋状の導電線である接地ワイヤー１
８が設けられている点で、実施の形態１における半導体
装置とは異なる。In the semiconductor device according to the second embodiment, a bridge having a ground potential and crossing over the semiconductor chip 8 is provided at a point where the ground electrodes 16 and 17 are not provided and at a central portion on the lead frame 2. Ground wire 1 that is a conductive wire
8 in that it is different from the semiconductor device in the first embodiment.

【００１７】この半導体装置においては、接地ワイヤー
１８が、信号端子電極３および信号端子電極７から発生
する電磁波を遮蔽するため、信号端子電極４ないし信号
端子電極６のアイソレーションが向上し、また逆に信号
端子電極３および信号端子電極７のアイソレーションも
向上する。In this semiconductor device, the ground wire 18 shields electromagnetic waves generated from the signal terminal electrode 3 and the signal terminal electrode 7, so that the isolation of the signal terminal electrodes 4 to 6 is improved and the reverse. In addition, the isolation between the signal terminal electrode 3 and the signal terminal electrode 7 is improved.

【００１８】図４は、従来の半導体装置（曲線ａ）およ
び実施の形態２における半導体装置（曲線ｂ）の周波数
とアイソレーションとの関係を示したものである。図４
から明らかなように、接地ワイヤー１８を有する実施の
形態２における半導体装置は、従来の半導体装置よりも
アイソレーションが向上していることがわかる。FIG. 4 shows the relationship between the frequency and the isolation of the conventional semiconductor device (curve a) and the semiconductor device (curve b) in the second embodiment. FIG.
As is clear from FIG. 7, the semiconductor device according to the second embodiment having the ground wire 18 has improved isolation as compared with the conventional semiconductor device.

【００１９】[0019]

【発明の効果】以上説明したように、本発明は、半導体
装置のパッケージ上の中央部にリードフレーム、周辺部
に複数の信号端子電極をそれぞれ配設し、リードフレー
ム上に半導体チップを搭載し、隣り合う２つの信号端子
電極の間に、接地電位を有する接地電極を配設すること
により、小型でかつ電気的干渉の少ない半導体装置を得
ることができる。As described above, according to the present invention, a lead frame is provided at a central portion on a package of a semiconductor device, a plurality of signal terminal electrodes are provided at a peripheral portion, and a semiconductor chip is mounted on the lead frame. By arranging a ground electrode having a ground potential between two adjacent signal terminal electrodes, it is possible to obtain a small-sized semiconductor device with little electrical interference.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態１における半導体装置の平
面図FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

【図２】同半導体装置および従来の半導体装置の周波数
特性を示す図FIG. 2 is a diagram showing frequency characteristics of the semiconductor device and a conventional semiconductor device.

【図３】本発明の実施の形態２における半導体装置の平
面図FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention;

【図４】同半導体装置および従来の半導体装置の周波数
特性を示す図FIG. 4 is a diagram showing frequency characteristics of the semiconductor device and a conventional semiconductor device.

【図５】従来の半導体装置の平面図FIG. 5 is a plan view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ パッケージ ２ リードフレーム ３、４、５、６、７ 信号端子電極 ８ 半導体チップ ９、１０、１１、１２、１３、１４ チップ電極 １５ ワイヤー １６、１７ 接地電極 １８ 接地ワイヤー DESCRIPTION OF SYMBOLS 1 Package 2 Lead frame 3, 4, 5, 6, 7 Signal terminal electrode 8 Semiconductor chip 9, 10, 11, 12, 13, 14 Chip electrode 15 Wire 16, 17 Ground electrode 18 Ground wire

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 パッケージ上の中央部にリードフレー
ム、前記パッケージ上の周辺部に複数の信号端子電極が
それぞれ配設され、前記リードフレーム上に半導体チッ
プが搭載され、隣り合う２つの前記信号端子電極の間
に、接地電位を有する接地電極が配設されていることを
特徴とする半導体装置。1. A lead frame is provided at a central portion on a package, a plurality of signal terminal electrodes are provided at a peripheral portion on the package, and a semiconductor chip is mounted on the lead frame, and two adjacent signal terminals are provided. A semiconductor device, wherein a ground electrode having a ground potential is provided between the electrodes. 【請求項２】 パッケージ上の中央部にリードフレー
ム、前記パッケージ上の周辺部に複数の信号端子電極が
それぞれ配設され、前記リードフレーム上に半導体チッ
プが搭載され、前記リードフレーム上の中央部に、接地
電位を有する架橋状の導電線が、前記半導体チップ上を
横切るように配設されていることを特徴とする半導体装
置。2. A lead frame is provided at a central portion on the package, a plurality of signal terminal electrodes are provided at a peripheral portion on the package, a semiconductor chip is mounted on the lead frame, and a central portion on the lead frame is provided. A cross-linked conductive line having a ground potential is provided so as to cross over the semiconductor chip.
JP9048664A 1997-03-04 1997-03-04 Semiconductor device Pending JPH10247717A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP9048664A JPH10247717A (en) 1997-03-04 1997-03-04 Semiconductor device
CNB981052975A CN1154182C (en) 1997-03-04 1998-02-27 Semiconductor device
US09/033,240 US6166429A (en) 1997-03-04 1998-03-03 Lead-frame package with shield means between signal terminal electrodes

Applications Claiming Priority (1)

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JP9048664A JPH10247717A (en) 1997-03-04 1997-03-04 Semiconductor device

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JPH10247717A true JPH10247717A (en) 1998-09-14

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US6166429A (en) 2000-12-26
CN1192582A (en) 1998-09-09
CN1154182C (en) 2004-06-16

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