JPH10256389A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: To manufacture a vertical bipolar transistor and a horizontal bipolar transistor of opposite conductivity type having good characteristics with a minimum number of steps. SOLUTION: The vertical Tr. Collector 14a and horizontal Tr. On the substrate 10 on which the base 14b of the vertical type is formed. Base electrode 22a and the horizontal Tr. Of the collector electrode 23b and the emitter electrode 24b. Cover the substrate 10 with an insulating film 25,
A contact hole 26 reaching the collector 14a is formed.
A resist pattern 27 having an opening above the contact hole 26 and above the base 14b between the collector electrode 23b and the emitter electrode 24b is formed on the insulating film 25. By ion implantation using the resist pattern 25 as a mask, the vertical Tr. An impurity for forming the intrinsic base 28a is introduced, a high concentration collector region 29a is formed immediately below the intrinsic base 28a, and the high concentration base region 30 is formed on the surface layer of the base 14b.
An impurity for forming b is introduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a vertical transistor and a vertical bipolar transistor and a lateral bipolar transistor of the opposite conductivity type are provided on the same substrate.

[0002]

2. Description of the Related Art In order to improve the AC characteristics of a vertical NPN bipolar transistor (hereinafter referred to as a vertical Tr.), It is necessary to suppress the parasitic capacitance between the base and the collector. Therefore, the N-type impurity concentration of the collector composed of the epitaxial layer grown on the semiconductor substrate,
That is, the N-type impurity concentration of the epitaxial layer is set to a low concentration. In addition, the vertical Tr. In order to suppress the Kirk effect in a high current region and improve the maximum cutoff frequency, a high-concentration collector region having a high N-type impurity concentration is provided in the collector in the epitaxial layer immediately below the intrinsic base. .

On the other hand, the vertical Tr. Since a lateral PNP bipolar transistor (hereinafter, referred to as a lateral Tr.) Formed on the same substrate as the base is based on the epitaxial layer in which the N-type impurity concentration is set to a low concentration as described above, it is relatively High hFE is obtained. However, since the surface state of the low-concentration epitaxial layer tends to vary due to the manufacturing process, the horizontal Tr. Is unstable in the surface condition of the base and the transistor characteristics are easy to fluctuate,
There is a problem that the base charge accumulation amount (Qb) is likely to be insufficient and the element withstand voltage is reduced, the current capacity is reduced, and the Early voltage is reduced.

Therefore, the horizontal Tr. In order to suppress the characteristic fluctuation and improve the characteristics, a configuration in which a high-concentration base region is provided in the surface layer of the base between the emitter and the collector has been considered.

[0005]

However, a lateral Tr. Having a structure in which a high-concentration base region is provided in the surface layer of the base is used.
When manufacturing a semiconductor device having the above, it is necessary to add a lithography step and an ion implantation step for forming the high concentration base region. Therefore, the vertical Tr. And horizontal Tr. Also in the manufacture of a semiconductor device provided with the above, there is a problem that the number of manufacturing steps is increased and the manufacturing steps are complicated.

Accordingly, the present invention relates to a vertical Tr.
And horizontal Tr. Are arranged on the same substrate, the vertical Tr. Although a low-concentration epitaxial layer is used to improve the characteristics of a horizontal Tr. It is an object of the present invention to provide a production method capable of obtaining the following.

[0007]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to a vertical Tr. And this vertical Tr. And a lateral Tr. Is a method of manufacturing a semiconductor device in which the steps are formed on the same substrate. That is, on the substrate on which the collector of the vertical bipolar transistor and the base of the horizontal bipolar transistor are formed, the vertical Tr. Base electrode and horizontal Tr. After the collector electrode and the emitter electrode are formed, the substrate is covered with an insulating film to form a contact hole reaching the collector. Next, on this insulating film,
A resist pattern having an opening above the contact hole and above the base between the collector electrode and the emitter electrode is formed. Thereafter, an impurity for forming a high-concentration collector region in the surface layer of the collector and an impurity for forming a high-concentration base region in the surface layer of the base are introduced by ion implantation using the resist pattern as a mask.

In the above manufacturing method, the vertical Tr. Is formed in a collector composed of an epitaxial layer grown on a semiconductor substrate, and a horizontal Tr. Is formed in the base made of the epitaxial layer. In addition, the vertical Tr. When the intrinsic base is formed, the intrinsic base is formed on the surface layer of the high concentration collector region by ion implantation using the resist pattern as a mask, or the intrinsic base is formed on the substrate at the bottom of the contact hole. Is formed. In this case, the epitaxial layer may be formed of silicon, and the semiconductor layer serving as the intrinsic base may be formed of silicon-germanium.

In the method of manufacturing a semiconductor device, the vertical T
r. Of impurities for forming a high concentration collector region of the vertical Tr. And a lateral Tr. Is simultaneously performed by ion implantation using the same resist pattern as a mask. Then, the vertical Tr. When forming the intrinsic base of the above, the substrate is exposed on the portion where the high concentration collector region is formed,
The upper portion of the high concentration base region is covered with an insulating film. For this reason, when the formation of the intrinsic base is performed by ion implantation, the impurity for forming the intrinsic base is not introduced into the surface layer of the high-concentration base region because of the inhibition of the insulating film. . Also, when the semiconductor layer serving as the intrinsic base is formed, the semiconductor layer is not formed on the surface of the high-concentration base region.

The high-concentration collector region is formed immediately below the intrinsic base and in a collector composed of an epitaxial layer grown on a semiconductor substrate. Therefore, by reducing the concentration of this epitaxial layer, the vertical Tr. Is designed to reduce the parasitic capacitance between the base and the collector and to reduce Kirk in a high current region.
The effect is suppressed. The high-concentration base region is formed in a surface layer of the base made of the epitaxial layer. For this reason, the lateral Tr. Has a good hFE, has a high impurity concentration on the base surface, and suppresses fluctuations in characteristics.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a semiconductor device manufacturing method according to an embodiment of the present invention;

(First Embodiment) FIGS. 1 and 2 are views showing one embodiment of a method of manufacturing a semiconductor device to which the present invention is applied. Here, a vertical NP having a double polysilicon structure is shown.
N bipolar transistor (hereinafter referred to as vertical Tr.)
And a horizontal PNP bipolar transistor (hereinafter referred to as a horizontal TNP).
r. Are described on the same substrate as an example.

First, as shown in FIG.
> Vertical Tr. On the semiconductor substrate 11 made of oriented P-type silicon. Region 11a and the horizontal Tr. On the surface layer with the region 11b, n + buried layers 12a and 12b are formed. Next, an n-type silicon epitaxial layer 14 is formed on the upper surface of the semiconductor substrate 11. This epitaxial layer 14
With a sheet resistance of about 0.3 Ωcm to 5.0 Ωcm and a film thickness of 0.1 Ωcm.
It is set to about 5 μm to 2.5 μm. As described above, the substrate 1 including the semiconductor substrate 11 and the epitaxial layer 14
0 is formed.

Next, as shown in FIG.
The element isolation region 15 is formed in the surface layer of the substrate 10 by the S method. Then, the vertical Tr. The epitaxial layer 14 in the region 11a has a vertical Tr. Of the horizontal type. Epitaxial layer 1 in Tr region 11b
The four parts are horizontal Tr. Base 14b. Next, after the surface of the substrate 10 is planarized, the element isolation region 15 is formed.
A channel stop layer 16 is formed below and a vertical T
r. An extraction collector 17a reaching the n + buried layer 12a is formed in the surface layer of the substrate 10 in the region 11a,
Horizontal Tr. N + is added to the surface layer of the substrate 10 in the region 11b.
An extraction base 18b reaching the buried layer 12b is formed. Next, CVD (Chemical Vapor Deposition)
The silicon oxide film 19 is deposited to a thickness of about 50 to 200 nm by a method.

Next, an opening 20 is formed in the silicon oxide film 19 as shown in FIG. This opening 20
Is a vertical Tr. Region 11a above the base forming portion and the horizontal Tr. It is provided above the emitter forming portion and the collector forming portion in the region 11b. Thereafter, a polysilicon film 21 having a thickness of about 80 nm to 250 nm is formed on the silicon oxide film 19 in a state of being connected to the bottom of the opening 20, and the polysilicon film 21 is ion-implanted.
A P-type polysilicon film 21 is formed by introducing boron ions (B ⁺ ) or boron difluoride ions (BF ₂ ⁺ ) serving as P-type impurities therein. Next, the P-type polysilicon film 21 is patterned by dry etching using a resist pattern (not shown) as a mask. Base electrode 22a, horizontal Tr. Emitter electrode 23b and the horizontal Tr. Is formed. After that, the resist pattern is removed.

Next, as shown in FIG. 1 (4), an insulating film 25 is formed so as to cover the electrodes 22a, 23b and 24b. This insulating film 25 is formed by, for example, CVD method.
It is made of silicon oxide deposited and formed to a thickness of about 00 nm to 500 nm. Next, a resist pattern (not shown)
Is used as a mask to etch the insulating film 25 and the base electrode 22a. A contact hole 26 is provided in the region where the intrinsic base is formed. After that, the resist pattern is removed.

The following step shown in FIG. 1 (5) is a characteristic step of the present invention. That is, the upper side of the contact hole 26 and the horizontal Tr. A resist pattern 27 opening above base 14b between emitter electrode 23b and collector electrode 24b in region 11b.
Is formed on the insulating film 25.

Thereafter, ion implantation is performed using this resist pattern 27 as a mask to form a vertical Tr. Area 11a
A P-type impurity for forming the intrinsic base 28a is introduced into the surface layer of the substrate 10 in FIG. Here, the vertical Tr. In order to make the base shallower,
It is assumed that ion implantation with low energy is performed. As an example, boron difluoride ion (BF ₂ ⁺ ) is 5 keV
With an implantation energy of about 50 keV, 10 ¹² / cm
^{About 2 to} 3 × 10 ¹⁴ particles / cm ² are introduced. For this reason, the horizontal Tr. In the region 11b, the P-type impurity is not introduced into the substrate 10 because it is blocked by the insulating film 25 and the silicon oxide film 19.

Further, the vertical Tr. Is formed by ion implantation using the resist pattern 27 as a mask. Area 1
1a, a high-concentration collector region 29a is formed.
An N-type impurity for forming the high concentration base region 30b is simultaneously introduced into the region 11b. The high-concentration collector region 29a has a vertical Tr. Is an impurity region for suppressing the Kirk effect. The high concentration base region 30b is
Horizontal Tr. Impurity region for stabilizing and improving the characteristics of the semiconductor device.

Here, the high-concentration collector region 29a is disposed immediately below the intrinsic base 28a,
It is assumed that ion implantation is performed at such an energy that Ob is disposed on the surface layer of the substrate 10. As an example, phosphorus ions (P ⁺ ) are implanted at a dose of about 200 keV to 400 keV, and 1 × 10 ¹² ions / cm ^{2 to} 5 × 10 ¹³ ions / cm ^2.
Introduce about ² cm ² .

Next, after removing the resist pattern 27, as shown in FIG. A sidewall 31 is formed in the contact hole 26 in the region 11a. The sidewalls 31 are formed by, for example, etching back a silicon oxide film formed to a thickness of about 0.4 μm to 1.0 μm by CVD using RIE (Reactive Ion Etching). afterwards,
An N-type polysilicon film 32 is formed above the substrate 10 so as to cover the inner wall of the contact hole 26. The N-type polysilicon film 32 is formed by forming a polysilicon film containing an N-type impurity such as arsenic or phosphorus, or forming a polysilicon film containing no impurity, and then forming an N-type polysilicon film on the polysilicon film. It may be formed by introducing impurities.

Next, a silicon oxide film (not shown) having a thickness of about 100 nm to 500 nm is formed on the N-type polysilicon film 32 by the CVD method.
A heat treatment at about 00 ° C. is performed for 5 seconds to 2 hours. As a result, the N-type polysilicon film 32
Type impurities are diffused to form a vertical Tr. An emitter 33a is formed on the surface layer of the intrinsic base 28a in the region 11a. Further, a base electrode 22 made of P-type polysilicon is formed.
a, a P-type impurity is diffused from the emitter electrode 23b and the collector electrode 24b to the surface layer of the substrate 10, and the vertical Tr. A braft base 34a is formed in the region 11a, and a horizontal Tr.
An emitter 35b and a collector 36b are formed in the region 11b. The silicon oxide film serves as a layer for preventing impurities in the N-type polysilicon film 32 from diffusing upward.

Next, as shown in FIG. 2B, after removing the silicon oxide film, the vertical Tr. Is removed by etching using a resist pattern as a mask. N in area 11a
An emitter electrode 37a made of the mold polysilicon film 32 is formed. Thereafter, a contact hole 38 is formed in the insulating film 25 and the silicon oxide film 19 by etching using a different resist pattern as a mask. This contact hole 38 has a vertical Tr. Region 11a, the base electrode 22a, the take-out collector 17a, and the horizontal Tr. It is provided so as to reach the extraction base 18b, the emitter electrode 23b, and the collector electrode 24b of the region 11b.

Next, as shown in FIG. 2C, the bottom of each contact hole 38 and the vertical Tr. A wiring 39 connected to the emitter electrode 37a in the region 11a is formed. The wiring 39 is formed by forming a barrier metal and an aluminum-based material by sputtering and etching the film. Although illustration is omitted here, the subsequent steps are multilayer wiring steps.

The semiconductor device 1 formed as described above
Is a vertical Tr. 1a and horizontal Tr. 1b is the same substrate 10
It will be provided in. Then, the vertical Tr. K of 1a
High concentration collector region 29a for suppressing irk effect
And a horizontal Tr. Impurities for forming the high-concentration base region 30b for stabilizing and improving the characteristics of 1b are introduced into the substrate 10 by the same ion implantation. Therefore, the semiconductor device 1 is manufactured without separately providing an impurity introduction step for forming the high concentration collector region 29a and the high concentration base region 30b.

(Second Embodiment) FIGS. 3 and 4 are views showing another embodiment of a method of manufacturing a semiconductor device to which the present invention is applied. In this embodiment, a vertical N-type semiconductor device having a double polysilicon structure is shown.
PN heterojunction bipolar transistor (hereinafter referred to as vertical T
r. And a lateral PNP bipolar transistor (hereinafter, referred to as a lateral Tr.) Formed on the same substrate.

First, the steps described in the first embodiment with reference to FIGS. 1A to 1D are performed in the same manner. However,
As the semiconductor substrate 11, a <100> -oriented P-type silicon substrate is used. Thereafter, the process shown in FIG. 3A is performed in the same manner as described in the first embodiment with reference to FIG. 1F, and ion implantation using the resist pattern 27 as a mask causes the vertical Tr. A high concentration collector region 29a is formed in the region 11a to form a horizontal Tr. An N-type impurity for forming the high concentration base region 30b is simultaneously introduced into the region 11b. The high concentration collector region 29a has a vertical T
r. Is an impurity region for suppressing the Kirk effect. The high-concentration base region 30b has a horizontal Tr. Impurity region for stabilizing and improving the characteristics of the semiconductor device.

Next, as shown in FIG. 3B, after the resist pattern (27) is removed, the damage caused on the surface of the substrate 10 at the bottom surface of the contact hole 26 by the ion implantation is recovered, and A heat treatment for activating the impurities introduced therein is performed. Next, the substrate 10 and P
After sufficiently exposing the exposed surface of the polysilicon film 21, the vertical Tr. Is formed on the exposed surface (that is, on the high concentration collector region 29 a) by selective epitaxial growth.
Of a silicon-germanium layer to be the intrinsic base 50a of FIG. Thereby, the vertical Tr. In the area 11a,
A heterojunction between silicon and silicon-germanium is formed. At this time, the silicon-germanium layer is
r. So that the intrinsic base 50a of the silicon
An impurity profile in the germanium layer is selected.

Next, the step shown in FIG.
In the same manner as described with reference to FIG. 2A in the embodiment, a sidewall 31 is formed on the side wall of the contact hole 26, and an N-type polysilicon film 32 is further formed to form a silicon-germanium layer. Intrinsic base 5
An emitter 33a is formed on the surface layer 0a. Further, the vertical Tr. A graft base 34a is formed in the region 11a, and the horizontal Tr. An emitter 35b and a collector 36b are formed in the region 11b.

Next, the step shown in FIG.
By performing the same operation as described with reference to FIG. 2B in the embodiment, the vertical Tr. An emitter electrode 37a made of an N-type polysilicon film 32 is formed in the region 11a, and a contact hole 38 is formed in the insulating film 25.

Thereafter, the wiring 39 is formed by performing the step shown in FIG. 4 in the same manner as described in the first embodiment with reference to FIG. The subsequent steps are multilayer wiring steps.

The semiconductor device 5 formed as described above
Is a heterojunction vertical Tr. 5a and horizontal Tr. 1b is provided on the same substrate 10. Then, similarly to the first embodiment, the vertical Tr. A high concentration collector region 29a for suppressing the Kirk effect of
r. Impurities for forming the high-concentration base region 30b for stabilizing and improving the characteristics of 1b are introduced into the substrate 10 by the same ion implantation. Therefore, the semiconductor device 5 is manufactured without separately providing an impurity introduction step for forming the high-concentration collector region 29a and the high-concentration base region 30b.

[0033]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the vertical Tr. Of impurities for forming a high-concentration collector region for suppressing the Kirk effect of the vertical Tr. And a lateral Tr. Impurity introduction for forming a high concentration base region for the purpose of stabilizing and improving the characteristics of the semiconductor device is performed in the same process, so that an increase in the number of processes can be suppressed and a semiconductor device having good characteristics can be manufactured. become.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram (part 1) for describing a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram (part 2) for explaining the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram (part 1) for describing a second embodiment of the present invention.

FIG. 4 is a manufacturing process diagram (part 2) for explaining the second embodiment of the present invention.

[Explanation of symbols]

1,5 Semiconductor device 1a, 5a Vertical Tr. (Vertical Bipolar Transistor) 1b Horizontal Tr. (Lateral bipolar transistor) 10 substrate 14 epitaxial layer 14a collector 14b base 22a base electrode 23b emitter electrode 24b collector electrode 25 insulating film 26 contact hole 27 resist pattern 28a, 50a intrinsic base 29a high concentration collector region 30b high concentration base region

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device in which a vertical bipolar transistor having a double polysilicon structure and a horizontal bipolar transistor having the opposite conductivity type to the vertical bipolar transistor are formed on the same substrate, wherein a collector of the vertical bipolar transistor is provided. After forming a base electrode of the vertical bipolar transistor and a collector electrode and an emitter electrode of the horizontal bipolar transistor on a substrate on which the base of the horizontal bipolar transistor is formed, the substrate is covered with an insulating film, and the base is covered. Forming a contact hole reaching the collector in the electrode and the insulating film; and forming a resist pattern having an opening above the base above the contact hole and between the collector electrode and the emitter electrode. Formed on insulating film Forming a high concentration collector region in the surface layer of the collector and introducing impurities for forming a high concentration base region in the surface layer of the base by ion implantation using the resist pattern as a mask. A method for manufacturing a semiconductor device, comprising: 2. The method for manufacturing a semiconductor device according to claim 1, wherein the high concentration collector region is formed in the collector formed of an epitaxial layer grown on a semiconductor substrate, and wherein the high concentration base region is A method for manufacturing a semiconductor device, wherein the semiconductor device is formed in the base made of an epitaxial layer. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the intrinsic base of the vertical bipolar transistor is formed in a surface layer of the high concentration collector region by ion implantation using the resist pattern as a mask. A method of manufacturing a semiconductor device, the method comprising the step of introducing impurities. 4. The method of manufacturing a semiconductor device according to claim 2, wherein a step of forming a semiconductor layer serving as an intrinsic base of the vertical bipolar transistor on a surface of the substrate at a bottom surface of the contact hole is performed. Manufacturing method of a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, wherein said epitaxial layer is made of silicon, and said semiconductor layer serving as an intrinsic base is made of silicon-germanium.