JPH10268002A - Noise filter relay circuit and noise filter relay board for semiconductor device measurement test - Google Patents

Abstract

(57) [Summary] (Modifications) [Problem] To have excellent noise filter capability and to increase the number of 32 parallel units without increasing the occupied area on the probe board, power consumption and maintenance cost. To provide a semiconductor device measurement and test technique which can sufficiently cope with a test method. A plurality of unit relay circuits are connected in parallel along a power supply side bus line and a ground side bus line connected to a tester, and each unit relay circuit is connected to a power supply side bus line. A power supply contact 111 connected to the ground bus line; a bypass capacitor 119 interposed between the power supply contact and the ground contact; A ground-side relay 117 was interposed between the ground-side bus line. Further, the noise filter relay circuit 101 is mounted on the probe board 133, and the power supply side and ground side contacts 111 and 113 are respectively brought into contact with the power supply side and ground side pads on the semiconductor element CP to be measured during the measurement test. Mounted as possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise filter relay circuit and a noise filter relay board for a semiconductor device measurement test, and more particularly to a noise test relay circuit for measuring the electrical performance of a semiconductor device on a wafer by a parallel test method. The present invention relates to improvement of noise reduction capability and various costs of a measurement test system.

Normally, a silicon wafer which has undergone a process of forming circuit elements and wirings is provided with a plurality of semiconductor integrated circuits having the same circuit configuration and arranged in a matrix on a silicon base layer (substrate) by scribe lines. Have been. Defective products of these semiconductor integrated circuits are marked in an electrical performance measurement test using an IC tester. Thereafter, the wafer is individually cut off from the wafer along the scribe line to become a semiconductor element (for example, an IC chip), and only non-defective products proceed to the next packaging step. In this specification, for convenience of expression,
The individual semiconductor integrated circuits formed on the wafer before separation as described above will be referred to as “semiconductor elements”. Such a semiconductor element is sometimes called a “semiconductor device”.

[Prior art]

The above-described electrical performance measurement test generally tests a semiconductor wafer set on a prober using an IC tester, and all pads and IC testers formed on each semiconductor element are probed. A predetermined level of power supply potential (power supply voltage Vcc and ground side voltage Vss) is supplied to a predetermined power supply pad on the semiconductor element, and a predetermined input signal is supplied to a predetermined power supply pad on the semiconductor element. , The output signal from the semiconductor element is sent to the IC tester, whereby the quality of the electrical performance of the semiconductor element is determined.

[0004] Incidentally, the above-described electrical performance measurement test of a semiconductor device includes a serial test system for sequentially measuring and testing a plurality of semiconductor devices on a wafer and a parallel test system for simultaneously measuring and testing a plurality of semiconductor devices on a wafer. There is a test method. Of these, the present invention is directed to a measurement test by the parallel test method, but currently, in this measurement test system, a so-called “16-cavity” for simultaneously measuring and testing 16 semiconductor elements is mainly used. . However, in the near future, there is a tendency for technology to shift to "32-cavity", in which 32 semiconductor elements are measured and tested at the same time, or to "multi-cavity", or more. The present invention has been proposed especially with a view to such a future technology flow.

The configuration of a conventional filter relay circuit and a conventional filter relay board in a measurement test system for performing such a parallel test type measurement test and the role of the relay used therein will be described in detail later. For better understanding, an outline of a conventionally known measurement test system will be described below.

[0006] In the measurement test by the above-described measurement test system, the signal transmission between the tester and the semiconductor element is performed by bringing a large number of contacts arranged on the probe board into contact with all the pads of the individual semiconductor elements. Is what you do. As for transmission (application) of the power supply voltage among those signal transmissions, the power supply side contact and the ground side contact are brought into contact with the pads on the individual semiconductor elements via the filter relay circuit arranged on the probe board. Communication is performed by causing Further, if noise occurs during the measurement test, the true electrical performance of the semiconductor element cannot be determined, so the noise is reduced by the noise filter function of the parallel capacitor interposed in the power supply line. Further, unless a defective semiconductor element is separated from the system, an adverse effect is exerted on a measurement test of a good semiconductor element. Therefore, a power supply side relay (VCC relay) is provided between the power supply side contact and the parallel capacitor, and a ground side relay (VSS relay) is provided between the ground side contact and the ground.
Each of these devices is interposed, and disconnecting the defective semiconductor element from the system is performed by opening these relays.

As described above, in the conventional measurement test system, it is necessary to provide two relays per semiconductor element, that is, a total of 32 relays in a "16-cavity" system. The use of such a large number of relays causes various problems in terms of noise reduction capability, manufacturing cost, space and maintenance costs, and the like. In particular, when the measurement test system shifts to “32 pieces” as described above, such a problem becomes more serious. The idea of the present invention is to basically reduce the number of relays used and to simplify the configuration of the filter relay circuit in order to deal with such a problem.

FIG. 30 shows an example of a conventional noise filter relay circuit, and FIGS. 31 and 32 show an example of a conventional noise filter relay board equipped with such a noise filter relay circuit. In the noise filter relay circuit 1 shown in FIG. 30, along the back bias line 12 connected to the back bias power supply 4 of the tester 9 and the ground line 14 also connected to the ground 16,
Two or more unit relay circuits 3 having the same circuit configuration are connected in parallel. Normally, the unit relay circuit 3 is provided with a number equal to the number of simultaneous measurement tests of the semiconductor elements, for example, 16 in the case of a "16-piece" parallel test system. A signal input line 6 and a signal output line 8 are connected between each semiconductor element CP and the tester 9, and a signal is transmitted through these lines. The number of these lines is appropriately increased or decreased according to the measurement test conditions.

Each unit relay circuit 3 has a power contact 11
And ground-side contacts 13. The number of these contacts is appropriately increased or decreased according to the measurement test conditions. The power supply side contact 11 is connected to the power supply 2 (for example, 5 V) via the tester relay 10 and has a bypass capacitor 19.
Is also connected. Here, the bypass capacitor 19 functions as a noise filter for reducing noise during a measurement test of the semiconductor device.

The bypass capacitor 19 is connected to the ground line 14 via the power supply side relay 15, and the ground contact 13 is also connected to the ground line 14 via the ground side relay 17. These relays 15 and 17 are used to separate defective semiconductor elements from the system, that is, the noise filter relay circuit 1 during a measurement test, as described later. A back bias contact 21 connected to the back bias line 12 separately from these.
Are provided, and the back bias contacts 21 of the respective semiconductor elements are connected to each other by a substrate (not shown). Here, the back bias voltage applied to the contact 21 stabilizes the operation of the semiconductor element.

In the noise filter relay board 31 shown in FIGS. 31 and 32, a probe board 33 on which the above-mentioned noise filter relay circuit 1 is mounted has a substantially central portion penetrated in the thickness direction. Have a viewing window 35 for checking the contact state of the contact 11 (13) with the semiconductor element. Further, a contact insertion hole 37 surrounds the viewing window 35 concentrically. The contact holes 37 are formed in a number equal to the maximum number of simultaneous measurement tests of the semiconductor device in the parallel test method. Each contact 11 (13) extends from the front side to the back side of the probe board 33 through the corresponding through hole 37. Arrangement boards 39 are attached to the back surface of the probe board 33 along both edges of the viewing window 35,
On the lower surface of each arrangement board 39, a groove for directing the contact is formed. That is, these grooves are engaged with the contacts 11 (13) protruding from the back side of the probe board 33, and correspond to the arrangement of the pads of the semiconductor elements on the wafer.
The tips of the contacts 11 (13) are aligned.

In each unit relay circuit 3 shown in FIG. 30, two relays 15, 17 are used. The reason will be described below. Two semiconductor elements CP1, CP
2, a parallel test is performed, and CP1 is a defective product in which the power supply contact 11 and the substrate contact 21 are short-circuited. Assuming that the power supply side relay 15 is not provided, in the measurement test of the output level at the substrate side contact 21 of the second semiconductor element CP2, the back bias voltage output from the back bias power supply 4 21 to charge the bypass capacitor 19 through a circuit from the substrate (not shown) to the power supply side contact 11 of the semiconductor element CP1. The flow through such a long circuit and the charging of the bypass capacitor 19 combine to delay the rise of the output. As a result, the timing of the measurement test is deviated, and the second semiconductor element CP2 is determined as a defective product although the second semiconductor device CP2 is a good product.

If the number of simultaneous measurement tests of the semiconductor device is two, such a malfunction can be avoided by adjusting the timing of the measurement test according to the delay of the rise of the voltage. However, the number of simultaneous measurement tests for semiconductor devices is 4
When the number of semiconductor elements increases to eight, or even sixteen, it becomes difficult to specify how many semiconductor elements having such an internal short-circuit exist in the number of simultaneous measurement tests. For this reason, it is not preferable in terms of work efficiency to estimate the delay largely and adjust the measurement test timing in accordance with the delay, that is, perform the measurement test after a waiting time. Therefore, as shown in the figure, a relay 15 is provided between the power supply side contact 11 of each semiconductor element CP and the bypass capacitor 19, and for a semiconductor element CP determined to be defective, the relay 15 is opened, and the bypass capacitor 19 Can be separated.

The above malfunction is caused by the ground contact 1
3 also occurs. That is, the first semiconductor element CP
1 is a ground contact 13 and a substrate contact 2
It is assumed that a defective product is short-circuited between them. Assuming that there is no ground side relay 17, the second semiconductor element CP2
In the test for measuring the output level at the substrate side contact 21 of FIG. 5, the output back bias voltage is changed to the contact 21 to the substrate of the semiconductor element CP1 (not shown).
It falls to the ground via the circuit of the ground contact 13.
That is, since the output becomes 0 V, it is determined that the second semiconductor element CP2 is defective, even though the second semiconductor element CP2 is good. Also in this case, when the number of simultaneous measurement tests of the semiconductor element increases, the same problem as described above appears. Therefore, as shown in the drawing, a relay 17 is provided between the ground contact 13 of each semiconductor element CP and the ground bus line 7, and for a semiconductor element CP determined to be defective, the relay 17 is opened to bring the system from ground. It is detachable.

As described above, for each semiconductor element CP, 2
By providing the relays 15 and 17, when a certain semiconductor element is determined to be defective, the semiconductor element is separated from the measurement test system, that is, the noise filter relay circuit by opening these relays, and is a non-defective product. This avoids adverse effects on semiconductor device measurement tests.

The opening / closing control of the relays 15 and 17 as described above may be performed by a worker when a defective product is determined, for example, by a manual switch, or automatically by an appropriate known control circuit.

[0017]

In the conventional noise filter relay circuit 1 shown in FIG. 30, the power supply side bus line 5 is connected to the bypass capacitor 19 via the power supply side relay 15. A relay is an element that constitutes impedance by itself. Therefore, the presence of the power supply side relay 15 increases the circuit impedance between the power supply and the ground, and the noise reduction effect of the bypass capacitor 19 is reduced.

Similarly, the ground contact 13 is connected to the ground bus line 7 via the ground relay 17. Also in this case, the ground-side relay 17 becomes an impedance element, and the circuit impedance between the contact 17 and the ground increases, thereby generating noise.

In order to solve such a problem, for example, as shown in FIG. 33, it is conceivable to make the ground side relay 17 a parallel structure to reduce the impedance by half. However, in this case, three relays are used for one unit relay circuit 3. As a result, (a) the space occupied by the relay on the probe board increases, (b)
There is a problem that the production cost increases and (c) the relay has a long service life and is frequently used, so that the maintenance cost increases.

That is, in the parallel test system, when the current "16 pieces" is shifted to the future "32 pieces", a total of 64 relays are used in the conventional noise filter relay circuit. However, the following problems arise.

(A) The use of a relay reduces the noise reduction effect of the bypass capacitor. (B) The relay has the same size (about 10 mm) as the semiconductor element in the longitudinal direction. Therefore, the area occupied by the relay on the probe board becomes considerably large. (C) Since a current of 200 mA flows per relay, the power consumption is also considerable. (D) The number of replacements increases due to the life of the relay, and the maintenance cost increases.

The power consumption of the semiconductor device is 600 mA at the maximum.
Rank. When 32 chips are taken, a current 32 times larger flows to the ground at the same time, and the ground level is raised as noise. To deal with this, a strong noise filter capability is required, but the configuration and capability of the conventional noise filter relay circuit cannot meet this requirement.

In view of the current state of the prior art, an object of the present invention is to provide an excellent noise filter capability and without increasing an occupied area on a probe board, power consumption and maintenance cost. It is an object of the present invention to provide a semiconductor device measurement test technique which can sufficiently cope with a 32-test parallel test method.

[0024]

SUMMARY OF THE INVENTION For this reason, the first of this application is described.
The present invention relates to a noise filter relay circuit for semiconductor device measurement test that transmits a predetermined signal between a plurality of semiconductor devices arranged in a matrix on a semiconductor wafer and a tester, wherein the relay circuit is A power supply side bus line to which a predetermined power supply potential is supplied from a tester, a ground side bus line to which a ground voltage is supplied, and a predetermined pad formed on the semiconductor element connected to the power supply side bus line. A power supply contact that can be contacted and a ground contact that is connected to the ground bus line via a relay and that can contact a predetermined pad formed on the semiconductor element. And a plurality of unit relay circuits each having a bypass capacitor.

According to a second invention of this application, a predetermined signal is transmitted between a contactor capable of contacting pads formed on a plurality of semiconductor elements arranged in a matrix on a semiconductor wafer and a tester. A noise filter relay board for a semiconductor device measurement test, wherein the relay board includes a power supply side bus line to which a predetermined power supply voltage is supplied from a tester, a ground side bus line to which a ground voltage is supplied, A plurality of unit relays including a power supply contact connected to a power supply bus line, a ground contact connected to the ground bus line via a relay, and a bypass capacitor interposed between the two contacts. And a circuit.

The contact may project obliquely below the probe board, or may project vertically.
The components of the noise filter relay circuit may be arranged on the upper surface of the probe board, or may be arranged on the lower surface.

Further, the periphery of the noise filter relay circuit may be formed as a modularized probe block, and two or more such probe blocks may be assembled and mounted on a probe board.

[0028]

It is assumed that a short circuit has occurred between a power supply contact and a substrate contact in a certain semiconductor device. In this case, if the ground side relay is opened, the circuit itself does not exist, so that the back bias voltage does not drop to the ground. Similarly, when a failure occurs in which a short circuit occurs between the ground contact and the substrate contact, no circuit exists. In any case, opening the ground-side relay disconnects the bypass capacitor and the semiconductor device from the system. Therefore, the defective semiconductor element does not adversely affect the measurement test of the good semiconductor element.

[0029]

1 shows an example of a noise filter relay circuit according to the present invention, and FIGS. 2 and 3 show an example of a noise filter relay board equipped with such a noise filter relay circuit. In the noise filter relay circuit 101 shown in FIG. 1, a unit relay circuit having the same circuit configuration is formed along a back bias line 112 connected to the back bias power supply 104 of the tester 109 and an earth line 114 similarly connected to the earth 116. 103 or more are connected in parallel. Usually, the unit relay circuit 103 has a number equal to the number of simultaneous measurement tests of the semiconductor element, for example, “16”.
In the case of the "individual" parallel test method, 16 test pieces are provided. Each semiconductor element and the tester 109 are connected by a signal input line 106 and a signal output line 108, and a signal is transmitted through these lines. The number of these lines is appropriately increased or decreased according to the measurement test conditions.

Each unit relay circuit 103 includes a power supply side contact 1
11 and ground-side contacts 113, and the number of these contacts is appropriately increased or decreased according to measurement test conditions. The power supply side contact 111 is connected to the power supply 102 (for example, 5 V) via the tester relay 110 and is connected to the bypass capacitor 119 via the power supply side bus line 105.
It is connected to the. Here, the bypass capacitor 119 functions as a noise filter that reduces noise during the measurement test of the semiconductor device M.

The bypass capacitor 119 is connected to the ground line 114 via the ground-side bus line 107 and the relay 117. Ground contact 11
3 is the ground bus line 107 and the relay 1
17 is connected to the ground line 114. As will be described later, the relay 117 is used to replace a defective semiconductor device during a measurement test with the system, that is, the noise filter relay circuit 1.
It is separated from 01. In addition, a back bias contact 121 connected to the back bias line 112 is provided separately, and the back bias contacts 121 of each semiconductor element are connected to each other by a substrate (not shown). Here, the back bias voltage applied to the contact 121 is for stabilizing the operation of the semiconductor element.

In the noise filter relay board 131 shown in FIGS. 2 and 3, the probe board 133 on which the above-described noise filter relay circuit 101 is mounted has a substantially central portion penetrated in the thickness direction. To confirm the contact state of the contact to the semiconductor element,
It has a viewing window 135. In addition, this viewing window 135
Are concentrically surrounded by an insertion hole 138 for a signal transfer wire (not shown). The number of the contact holes 138 is equal to the maximum number of simultaneous measurement tests of the semiconductor device in the parallel test.

The probe board 1 spans the viewing window 135
A filter relay base 141 is provided on the base 33, and the power supply side bus line 105, the ground side bus line 107, and the ground side relay 117 are mounted on the filter relay base 141 in respective arrangements. The bypass capacitor 11 is connected to both bus lines 105 and 107 below the ground side relay 117.
9 is attached.

Further, insertion holes 137 for the contacts 111 and 113 are provided along the outer edges of both bus lines 105 and 107. The number of the contact holes 137 is equal to the maximum number of simultaneous measurement tests of the semiconductor device in the parallel test. Each contact 111 (113) extends from the front side to the rear side of the probe board 133 through the corresponding through hole 137. An arrangement board 139 is provided on the lower surface of the probe board 133 along both edges of the viewing window 135.
Is attached, and a groove for directing the contactor is formed on the lower surface of each arrangement board 139. That is, these grooves are engaged with the contacts 111 (113) exposed on the back side of the probe board 133, and correspond to the arrangement of the pads of the semiconductor elements on the wafer.
3) Align the tips.

In the noise filter relay circuit of the present invention as described above, two semiconductor elements CP1 and CP
A parallel test is performed on P2, and the semiconductor element CP1 is a defective product in which a short circuit occurs between the power contact 111 and the substrate contact 121 or between the ground contact, the contact 113, and the substrate contact 121. Suppose there is. If the ground side relay 117 is opened when a failure occurs, the circuit itself does not exist in any case. That is, the bypass capacitor 119 and the semiconductor element CP of the unit relay circuit in which the failure has occurred.
Since 1 is separated from the entire system, the measurement test of the non-defective semiconductor element CP2 is not adversely affected.

As described above, in the present invention, the number of relays used for each unit relay circuit is reduced by half, and the bypass capacitor is arranged at the position where the filter function can be exhibited most, and the noise of the system is combined. Although the reduction ability is remarkably improved, this effect will be proved by various experimental data below.

First, FIGS. 4 and 5 show changes with time in the voltage between contacts. FIG. 4 shows a conventional noise filter relay circuit, and FIG. 5 shows a noise filter relay circuit of the present invention. Curve I in both figures
Is the potential difference between the power contact and the substrate contact,
Curve II shows the potential difference between the power contact and the ground contact. The vertical axis represents the voltage (100 mV per scale).
The horizontal axis indicates time.

First, in the case of the prior art shown in FIG. 4, VPP (peak-to-peak voltage difference) of curve I is 190 mV,
The VPP of curve II is 510 mV. On the other hand, in the case of the present invention shown in FIG. 5, the VPP of the curve I is 120 m.
v, and the VPP of curve II is 280 mV.

As described above, in the case of the present invention, VPP (peak-to-peak voltage difference) is remarkably small as compared with the prior art. This means that the output voltage is less disturbed by noise, and thus indicates that the system of the present invention is very excellent in noise reduction capability. By reducing the noise in this way,
The true performance of a semiconductor device can be measured and tested.

The lower the noise, the more the system, that is, the noise filter relay circuit, can operate properly without being disturbed by noise over a wider voltage range. The data in Table 1 prove this fact.

[0041]

[Table 1]

In this table, the "reference" means a voltage which can be applied in the case of the conventional noise filter relay circuit, and the numbers on the right thereof are semiconductor device samples measured and tested by the noise filter relay circuit of the present invention. Number. In addition, the numerical values written in the cells of each sample indicate a range in which the voltage can be increased or decreased as compared with the reference while ensuring proper operation of the semiconductor element. In other words, it shows how far the semiconductor element can operate properly even when the applied voltage is increased or decreased (for example, 8 to 9 V) from a certain reference specification (for example, 5 V). The numerical value is 0.1 = 100 mV.

For example, in the case of sample 1, the semiconductor element operates properly even when the voltage is lowered by 0.1 (100 mV) below the reference, and conversely, when the voltage is increased by 0.3 (300 mV), It works properly. The average of the 16 semiconductor devices used in the experiment is a minimum of -0.1 and a maximum of 0.2. That is, by adopting the present invention, the semiconductor element operates properly even if the voltage is lowered by an average of 0.1 (100 mV) lower than that of the conventional noise filter relay circuit, and conversely increases by 0.2 (200 mV). Even if the voltage is increased, the semiconductor device operates properly.

FIGS. 6 and 7 show a first modified embodiment of the noise filter relay board of the present invention.
A vertical contact is used in place of the bent oblique contact in the basic embodiment shown in FIGS. That is, the same number of signal transfer wire through holes 138 as the maximum number of simultaneous measurement tests of semiconductor elements in the parallel test method are formed concentrically on the probe board 133.
A filter relay base 141 is mounted on the probe board 133 at a position that does not affect the extraction of the signal transfer wire 136 penetrated through these through holes 138, and a power supply is further mounted thereon. Side bus line 1
05, a ground side bus line 107 and a ground side relay 117 are mounted. Each bus line 105 (1
07), the contact 111 (113) drawn outward.
Extends vertically downward just outside the bus line 105 (107) and projects below the probe board 133.

FIG. 8 shows an example of the arrangement of the contacts. The tips of the contacts are arranged in a double row inside the viewing window 135 of the probe board 133. FIG. 9 shows another example of the arrangement of the contacts, in which the tips of the contacts are arranged in a single line in the viewing window 135 of the probe board 133. However, the arrangement of the contact tips is not limited to these, but by appropriately changing the specifications of the arrangement board 139 (see FIG. 3),
It can be set freely according to the parallel test method.

FIG. 10 shows the extension of the contact in the basic embodiment shown in FIG. 2, and FIG. 11 shows the extension of the contact in the first modified embodiment. is there. As is evident from this comparison, in the case of the basic embodiment, the contacts once extend outwardly, vertically downward, and further obliquely inwardly.
In contrast, in the case of the first variant, the length of the contact is significantly reduced. In a noise filter relay circuit, the contact also forms a kind of impedance element, so a short contact means a small circuit impedance, and the degree of diminishing the filter function of the bypass capacitor is small. It turns out that.

FIGS. 12 and 13 show a second modified embodiment of the noise filter relay board of the present invention. As in the case of the first modified embodiment, FIGS.
In this embodiment, a vertical contact is used in place of the bent oblique contact in the basic embodiment shown in FIG. That is, in the probe board 133, the same number of signal transfer wire through holes 138 as the maximum simultaneous measurement test number of semiconductor elements in the parallel test are formed concentrically. On the probe board 133, a filter relay base 141 is mounted, and further thereon a power supply side bus line 105, a ground side bus line 107, and a ground side relay 117.
Is installed. The contacts 111 (113) drawn outward from each bus line 105 (107) extend vertically downward just outside the bus line 105 (107), are held by the arrangement board 139, and are It protrudes downward.

In this modified embodiment, the signal transfer wire 13 is used.
Reference numeral 6 is arranged directly on the upper surface of the probe board 133 by pattern wiring. Thus, the signal transfer wire 13
6 does not protrude above the probe board 133,
Compared to the previous modified embodiment, the overall structure is thin and flat, and the storage and transportability is improved. Also, since the signal transfer wire will not be damaged during handling or transportation,
Maintenance is also improved. Further, as in the case of the previous embodiment, the contact is of the vertical type, so that the circuit impedance is correspondingly small, and the degree of diminishing the filter function of the bypass capacitor is small.

FIGS. 14 and 15 show a third variation of the noise filter relay board according to the present invention, in which a noise filter relay circuit is disposed below the probe board using a thin film (membrane). Things. That is, the thin film 143 is attached to the lower side of the probe board 113 by the holder 145.
Holds the filter relay base 141. The signal transfer wires are provided directly on the lower surface of the probe board 133 by pattern wiring. On the filter relay base 141, the power supply side base line 105, the ground side base line 107, and the ground side relay 117
And so on. In the case of this embodiment, bump-shaped contacts 111 and 113 are used, and the degree of protrusion downward from the filter relay base 141 is as small as about 100 μm.

The above bumps are formed integrally with the thin film 143 by a photolithography technique.
One example is shown in FIG. 16 and FIG. First, in the manufacture of the thin film (membrane) side, a mask is formed on the substrate film 151, and the signal trace 153 and the ground trace 155 are formed by photoetching. Next, after forming a via hole, a ground plane 157 is formed on the back side of the substrate film 151, and finally a bump 159 is formed.
Is formed so as to slightly protrude from the back side of the substrate film 151. The thin film side thus obtained is assembled with a probe board side manufactured by separately mounting a filter relay circuit to form a noise filter relay board.

If bumps are used as compared with the case where needles are used as the contacts as in the above-described embodiment, all bumps can be manufactured at once without the need for complicated procedures such as assembly and mounting, so that the manufacturing cost is greatly reduced. To be reduced. Also one
500 or more bumps can be manufactured with extremely high positional accuracy at a pitch of 00 μm or less, and a complicated pattern can be easily and relatively inexpensively manufactured according to the specifications of the parallel test. Further, there is an advantage that damage to the pad on the semiconductor element side is extremely small as compared with the case of the needle.

FIG. 18 shows a fourth modified embodiment of the noise filter relay board according to the present invention in which the noise filter relay circuit is arranged on the lower surface side of the probe board as in the previous embodiment.
And FIG. In this embodiment, a noise filter relay circuit is arranged on the lower surface side of the probe board as in the previous embodiment. That is, the filter relay base 1 attached to the lower surface of the probe board 133
The bus lines 105 and 107, the ground-side relay 117, and the like are mounted on 41. From the filter relay base 141, the mesa VLS method and the SOI
The pins (contacts 111 and 113) are integrally formed so as to protrude by the method. Signal transfer wire is probe board 13
The pattern wiring is directly carried out on the lower surface of the reference numeral 3.

As an example of a technique for growing a pin, Mesa V
The LS method will be described with reference to FIGS. First, as shown in FIG. 20, an Au bump 162 is formed on a silicon substrate 161 by a photolithography technique. Next, the entire surface of the silicon substrate 161 other than the Au bumps 162 is etched by a photoetching technique to form a portion serving as a growth nucleus 163 as shown in FIG. Then, the whole is dipped in an Au silicon melt heated to 950 ° C. to fuse the core 163 on the silicon substrate 161. As a result, as shown in FIG. 22, a bump 164 having silicon as a nucleus for pin growth as a nucleus and covering the surface with Au is formed. The bump 164 is exposed to a SiCl4-H2 (silicon tetrachloride) gas to grow a pin 165 as shown in FIG.

Another example of a technique for growing pins is SO.
The method I will be described with reference to FIGS. A silicon substrate 161 used in the VLS method is replaced with a Si layer 16 as shown in FIG.
1a, a SiO 2 layer 161b and a Si layer 161c. Next, a pattern 166 of a signal transfer wire is formed on the Si layer 161a by a photo etching technique as shown in FIG. Thereafter, the pin 167 is grown by the mesa VLS method, and the pin 167 and the pattern 1 are formed.
The surface of 67 is plated. Finally, the tip of the pin 167 is trimmed as shown in FIG.

In the case where pins are grown as contacts as in this embodiment, a large number of pins can be manufactured simultaneously, as in the case of forming the bumps in the previous embodiment. The manufacturing cost is greatly reduced as compared with the case where a needle is used.

FIGS. 27 to 29 show a fifth embodiment of the noise filter relay board according to the present invention. In this embodiment, the circuit elements constituting the noise filter relay circuit are formed into modular modules to form probe blocks, and a predetermined number of the modularized probe blocks are assembled and mounted on a probe board.

FIGS. 27 and 28 show an example of the above probe block. This probe block 20
0 has a base holder 201 for holding other elements, and this base holder 201 is made of an insulator such as a synthetic resin. A filter relay base 241 is attached to the front of the base holder 201,
A power supply side bus line 205, a ground side bus line 207, a bypass capacitor 219 and the like are mounted thereon. A power contact 211 is connected to the power bus line 205, and a ground contact 213 is connected to the ground bus line 297. The ground side relay 217 is mounted directly on the filter relay base 241 at a position above the bypass capacitor 219.

A predetermined number of such probe blocks 200 are grouped together, and as shown in FIG.
3 Here, six probe blocks 200 are mounted, but the number of mounted probe blocks 200 is not limited to this, and the number can be set appropriately and freely according to the specifications of the parallel test. it can.

The relay used in the noise fill relay circuit has a thickness of about 5 ± 1 to 2 mm, and the bypass capacitor has a thickness of about 0.8 mm. Therefore, when both are arranged in an overlapping manner, a total of 5.8 ± 1
It occupies a space in the thickness direction of 2 mm. Here, the thickness T (see FIG. 29) of the probe block is limited by the dimension of the semiconductor element on the wafer in the short side direction. That is, the pitch between adjacent probe blocks is set according to the pitch between adjacent semiconductor elements.
Therefore, it is desirable that the thickness of the probe block is not increased as much as possible. For this reason, in this embodiment, the relay is not mounted on the bypass capacitor, but is arranged on the upper filter relay base.

[0060] By modularizing the noise filter relay circuit element as described above, if a contact breaks during use, only the probe block to which the contact belongs needs to be replaced, and the entire noise filter relay board needs to be replaced. No need to replace. For this reason, maintenance costs are greatly reduced.

Since the work for mounting the contacts can be divided, the work can be sped up, and strict demands for delivery can be dealt with smoothly. For example, to attach 64 contacts,
If they are not modularized, they must be installed one by one. However, in the case of modularization, for example, the probe blocks are divided into eight probe blocks, and the mounting of the contacts on each probe block can be performed in parallel.

Even if there is a change in the number of simultaneous measurement tests in the parallel test, it is possible to flexibly cope with it by increasing or decreasing the number of probe blocks. That is, the degree of freedom in changing the specifications is increased.

[0063]

According to the noise filter relay circuit of the present invention, the bypass capacitor is disposed between the power contact and the ground contact. For this reason, the distance between both contacts and the bypass capacitor becomes very small, and the circuit impedance becomes small accordingly, so that the filtering function of the bypass capacitor, that is, the noise elimination ability is reduced less. In other words, the filter function of the bypass capacitor is maximized. In contrast, in a conventional noise filter relay circuit, a relay is arranged between a contact and a bypass capacitor. Since the relay is close to 10 mm in size, it becomes a considerable impedance element itself, which increases the circuit impedance and reduces the filtering function of the bypass capacitor.

Further, the number of relays is reduced by half compared with the conventional case. Since the relay has a dimension at the level of a semiconductor element in the longitudinal direction, the total space occupied by the relay on the probe board is greatly reduced, which can greatly contribute to miniaturization of the noise filter relay board.

Of course, the manufacturing cost is halved, but in addition, the replacement cycle of the relay is doubled as a system, so that the maintenance cost is also significantly reduced.

The current consumption per relay is about 200 m
Because of A, considerable power consumption can be saved as a whole.

In a parallel test of 32 pieces, tentatively 600
Even if a current of × 32 mA flows to the ground at the same time and the ground level rises as noise, the filter function of the bypass capacitor is fully exhibited, so that it is possible to sufficiently cope with it.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a noise filter relay circuit of the present invention.

FIG. 2 is a partial sectional side view showing a configuration of a basic embodiment of a noise filter relay board of the present invention.

FIG. 3 is a perspective view showing a configuration of a basic embodiment of a noise filter relay board of the present invention.

FIG. 4 is a graph showing a temporal change of a voltage between contacts in a conventional noise filter relay circuit.

FIG. 5 is a graph showing a temporal change of a voltage between contacts in the noise filter relay circuit of the present invention.

FIG. 6 shows a first embodiment of the noise filter relay board of the present invention.
FIG. 10 is a partial cross-sectional side view showing a configuration of a variation example.

FIG. 7 shows a first embodiment of the noise filter relay board of the present invention.
FIG. 9 is a perspective view showing a configuration of a variation example of FIG.

FIG. 8 is a bottom view showing an example of an arrangement of contacts according to the present invention.

FIG. 9 is a bottom view showing another example of the arrangement of the contacts in the present invention.

FIG. 10 is a partial cross-sectional side view showing a manner in which a contact extends in a basic embodiment of the noise filter relay board of the present invention.

FIG. 11 is a partial cross-sectional side view showing an extending mode of a contact in the noise filter relay board according to the first embodiment of the present invention.

FIG. 12 is a partial cross-sectional side view showing a configuration of a second modified example of the noise filter relay board of the present invention.

FIG. 13 is a perspective view showing a configuration of a second modified embodiment of the noise filter relay board of the present invention.

FIG. 14 is a partial cross-sectional side view showing a configuration of a third modified example of the noise filter relay board of the present invention.

FIG. 15 is a perspective view showing a configuration of a third modified example of the noise filter relay board of the present invention.

FIG. 16 is a sectional side view showing a step of forming a bump (contact) by a photolithography technique.

FIG. 17 is a flowchart showing a step of forming a bump (contact) by a photolithography technique.

FIG. 18 is a partial cross-sectional side view showing a configuration of a fourth modified example of the noise filter relay board of the present invention.

FIG. 19 is a perspective view showing a configuration of a third modified example of the noise filter relay board of the present invention.

FIG. 20 is a perspective view showing a step of forming a pin (contact) by a mesa VLS method.

FIG. 21 is a perspective view showing a step of forming a pin (contact) by a mesa VLS method.

FIG. 22 is a perspective view showing a step of forming pins (contacts) by a mesa VLS method.

FIG. 23 is a perspective view showing a step of forming pins (contacts) by a mesa VLS method.

FIG. 24 is a cross-sectional side view showing a step of forming pins (contacts) by the SOI method.

FIG. 25 is a sectional side view showing a step of forming pins (contacts) by the SOI method.

FIG. 26 is a cross-sectional side view showing a step of forming a pin (contact) by the SOI method.

FIG. 27 is a sectional side view showing a configuration of a probe block in a fifth embodiment of the noise filter relay board of the present invention.

FIG. 28 is a perspective view showing a configuration of a probe block in a fifth embodiment of the noise filter relay board of the present invention.

FIG. 29 is a perspective view showing the configuration of a fifth embodiment of the noise filter relay board of the present invention.

FIG. 30 is a circuit diagram showing a configuration of a conventional noise filter relay circuit.

FIG. 31 is a partial cross-sectional side view showing a configuration of a conventional noise filter relay board.

FIG. 32 is a perspective view showing a configuration of a conventional noise filter relay board.

FIG. 33 is a circuit diagram showing a configuration of an improved noise filter relay circuit of the related art.

[Explanation of symbols]

 1, 101: noise filter relay circuit 3, 103: unit relay circuit 5, 105: power supply side bus line 7, 107: ground side bus line 9, 109: tester 10, 110: tester relay 11, 111: power supply contact 13, 113: ground side contact 15: power supply side relay 17, 117: ground side relay 19, 119: bypass capacitor 21, 121: substrate side contact 23, 123: substrate 31, 131: noise filter relay board 33 133: Probe board 35, 135: Visual window 37, 137: Contact insertion hole 136: Signal transfer wire 138: Signal transfer wire insertion hole 39, 139: Arrange board 141: Filter relay base 143: Thin film (membrane) ) 145: Holder 15 1: substrate film 159: bump 161: silicon substrate 164: bump 165: pin 167: pin 200: probe block 201: base holder 203: top guard 205: power supply side bus line 207: ground side bus line 211: power supply side contact 213: ground contact 217: ground relay 219: bypass capacitor

Claims (8)

[Claims] 1. A noise filter relay circuit for measuring and testing a semiconductor device for transmitting a predetermined signal between a plurality of semiconductor devices arranged in a matrix on a semiconductor wafer and a tester, wherein a predetermined power supply potential is supplied from the tester. Power supply-side bus line, a ground-side bus line to which a ground voltage is supplied, and a power-side contact that is connected to the power-side bus line and can contact a predetermined pad formed on the semiconductor element. And a plurality of bypass capacitors connected to the ground-side bus line via a relay and a ground-side contact that can be in contact with a predetermined pad formed on the semiconductor element. A noise filter relay circuit for a semiconductor device measurement test, comprising: a unit relay circuit. 2. A noise filter for a semiconductor device measurement test for transmitting a predetermined signal between a contactor capable of contacting pads formed on a plurality of semiconductor devices arranged in a matrix on a semiconductor wafer and a tester. A relay board, a power supply side bus line to which a predetermined power supply voltage is supplied from a tester, and a ground side bus line to which a ground voltage is supplied,
A plurality of units each including a power supply contact connected to the power supply bus line, a ground contact connected to the ground bus line via a relay, and a bypass capacitor interposed between the contacts. A noise filter relay board for a semiconductor device measurement test, comprising a relay circuit. 3. The noise filter relay board according to claim 2, wherein said contacts are attached to the probe board so as to project obliquely below the probe board. 4. The probe according to claim 1, wherein the contact is vertically attached to the lower side of the probe board and is attached to the probe board, and a signal transfer wire is arranged to project to the upper side of the probe board. The noise filter relay board according to claim 2. 5. The probe according to claim 1, wherein the contact is vertically protruded from a lower side of the probe board and is attached to the probe board, and a signal transfer wire is directly arranged on the upper surface of the probe board from a pattern high fiber. The noise filter relay board according to claim 2, wherein 6. A thin film is mounted on a lower side of the probe board, and components of a noise filter relay circuit are mounted on a filter relay base mounted on an upper surface of the thin film, and a lower surface of the probe board is mounted on a lower surface of the probe board. 3. The noise filter relay board according to claim 2, wherein the signal transfer wires are directly arranged by pattern wiring, and the bumps formed integrally and vertically projecting from the thin film constitute the contacts. . 7. A component of a noise filter relay circuit is mounted on a filter relay base mounted on a lower surface of a probe board, and signal transfer wires are directly arranged on the lower surface of the probe board by pattern wiring. 3. The noise filter relay board according to claim 2, wherein pins formed integrally and vertically projecting from the filter relay base constitute the contact. 8. At least two modularized probe blocks are mounted side by side on a probe board, and in each probe block, a filter relay base is attached to a front surface of a base holder. 3. The relay base according to claim 2, wherein at least two or more sets of components of the noise filter relay circuit are arranged on the relay base, and the relays belonging to the same circuit and the bypass capacitors are arranged vertically shifted. The noise filter relay board described in 1.