JPH10270859A - Method for manufacturing multilayer wiring board - Google Patents

Abstract

(57) Abstract: Provided is a method for manufacturing a reliable build-up multilayer wiring board having excellent line insulation characteristics between conductor circuits.
Further, the present invention provides a method of manufacturing a build-up substrate capable of performing high-yield surface metallization even when the distance between the outermost conductor circuits is small. A repeating the conductor circuit forming step and the interlayer insulating film forming step are alternately, making the re multilayer wiring board by the build-up method, the insulating resin surface of the conductor circuits after the conductor circuit formation O ₂ plasma treatment Alternatively, after etching lightly by UV / O ₃ treatment, it is chemically removed by washing with water.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for manufacturing a multilayer wiring board.

[0002]

2. Description of the Related Art As electronic devices have become more sophisticated and semiconductor devices have become more highly integrated, printed circuit boards have also been required to have higher densities. At present, multilayer boards have become the mainstream. There are two widely known methods for manufacturing a multilayer wiring board, a lamination bonding method and a build-up method. The laminating method is
A blind hole for forming a blind via hole is formed by drilling a laminated plate serving as an inner layer, and a plating plate is formed on the laminated plate to form a laminated plate having a blind via hole, and an outer layer is laminated on the laminated plate having the blind via hole. This is a method of manufacturing a multilayer wiring board by punching through holes after plating and plating. However, in this laminate bonding method, the blind via holes and through holes for interlayer connection are opened by mechanical drilling, so the dimensions are relatively large,
It is difficult to increase the wiring density. In recent years, in recent years, as various types of consumer electronic devices have become smaller and thinner, the space for accommodating wiring boards constituting a predetermined electric circuit has become very limited. In order to house the wiring board that constitutes the desired electric circuit in
2. Description of the Related Art Thinning and densification by a build-up method in which conduction between layers is achieved by fine photo via holes using a photosensitive resin has become an effective technique.

A method of manufacturing a multilayer wiring board by a build-up method using a photosensitive resin for an interlayer insulating film is disclosed, for example, in Japanese Patent Application Laid-Open No. 4-148590. This wiring board has a structure in which a glass epoxy copper-clad laminate is used as a base material, an insulating layer is photosensitive epoxy resin, and a conductor layer is sequentially laminated by copper plating. In the method of manufacturing a multilayer wiring board by the build-up method, it is very important that the insulating layer and the conductive circuit, particularly the conductive circuit on the insulating layer, are firmly bonded. As a technique for firmly bonding a conductor circuit onto the insulating layer, for example, as disclosed in JP-A-6-260763 or JP-A-7-15139, the insulating layer is roughened with a chromic acid or potassium permanganate solution. The method of forming a conductor layer on the surface thereof has been widely performed.

[0004]

The roughening step is indispensable and the most important step in the build-up method. At the same time, however, the following problems are accompanied by the roughening step, so that the This is an obstacle to high density and high definition.
The first is the problem of line insulation between conductor circuits. In other words, in the build-up method, in order to enhance the adhesion with the conductor circuit on the resin, the inorganic filler in the resin is melted by the roughening or, conversely, the resin is dissolved to form a porous uneven shape on the insulating resin surface. ing. Thereafter, the entire surface is plated to form a conductive circuit by etching. However, on the resin surface between the circuits after the formation of the conductive circuit, the porous irregularities formed during the roughening step are present in the same shape. In the insulating resin layer having many gaps, water vapor easily penetrates and absorbs moisture during the constant temperature and constant humidity test, so that melting or migration of metal near the conductor circuit is easily promoted. In particular, conductive circuits that are not covered with the outermost layer of solder resist are directly exposed to the outside air. As a result, dew condensation easily occurs, and migration proceeds much faster than that of the inner layer. In addition, when a conductive circuit is formed by etching a metal layer formed by plating on an insulating resin, the metal is likely to remain in the concave portion of the resin, and further, the cleaning of the processing solution penetrated into the concave portion of the resin is sufficient. The fact that ionic residues are likely to remain without being performed also leads to the promotion of migration progress.

[0005] The second problem is that abnormal plating is deposited between conductor circuits. That is, components are mounted on the surface pads of the substrate via solder, but the copper pads themselves cause a large amount of solder erosion. Therefore, nickel plating is usually applied to provide repair resistance, and gold plating is applied on the nickel film to ensure solder wettability. This nickel plating or gold plating is performed by electroless plating because not all surface pads are electrically connected. However, a layer having a porous concavo-convex shape formed during the roughening step remains on the resin surface between the conductor circuits, and the concave portions have metal residues, that is, the catalyst Pd at the time of forming the underlying conductive film and the post-circuit formation. There is a slight copper etching residue. At the time of nickel plating, this metal residue becomes a nucleus and nickel is precipitated, so that abnormal plating occurs. In addition, since many holes are present on the roughened resin surface, hydrogen generated during nickel plating is easily trapped on the resin surface between the conductors. If the hydrogen has an activity, it reduces nickel, and as a result, nickel particles precipitate and adhere between the conductor circuits. In particular, this phenomenon becomes more remarkable as the interval between the conductor circuits becomes smaller.

As a method for removing a metal residue, an ionic residue, and a resin surface layer having a porous uneven shape on the roughened surface, for example, polishing can be considered. However, where the space between conductor circuits is narrow, residue removal near the conductor circuits is incomplete, and the polishing method also removes the conductor metal at the same time, so the conductor powder removed by polishing adheres to the insulating resin. There is also a possibility. Therefore, the physical removal method by polishing cannot be an essential countermeasure even if it can be used for coping.

It is an object of the present invention to firstly provide a method for manufacturing a highly reliable multilayer wiring board having excellent line insulation between conductor circuits, and secondly, to provide a method in which the interval between outermost conductor circuits is narrow. However, it is an object of the present invention to provide a method for manufacturing a multilayer wiring board which does not cause abnormal plating deposition and can perform surface metallization at a high yield.

[0008]

The above object is achieved by removing the surface of the insulating resin between the conductor circuits by etching after the formation of the conductor circuits. In this case, as the etching method, both a dry process and a wet process can be used. In the dry process, it is effective to pass a water washing step after performing an O ₂ plasma treatment or a UV / O ₃ treatment. The O ₂ plasma treatment can be a plasma treatment using pure water O _{2 or} a plasma treatment using a mixed gas of O ₂ and CF 4 mixed at various ratios.

When the O ₂ plasma treatment or the UV / O ₃ treatment is performed, a chemically extremely active species containing atomic oxygen is generated, and an oxidation reaction with the active species decomposes organic matter in the insulating resin. As a result, the insulating film surface is etched. At this time, the metal etching residue (catalyst Pd at the time of forming the underlying conductive film and the copper etching residue after the formation of the circuit) or the ionic residue existing in the concave portion of the insulating film surface does not react with the active species. It remains concentrated on the inorganic filler in the membrane. However, since the insulating resin surface has been hydrophilized by the O ₂ plasma treatment or the UV / O ₃ treatment, the filler residue layer is removed in the next washing step, and the metal residue and the ionic residue are removed together with the filler residue layer. Removed together. In other words, the inter-conductor insulating resin after the O ₂ plasma treatment or UV / O ₃ is almost in the same state as the resin surface before the insulating resin is roughened. Therefore, since there is no resin surface layer having a porous unevenness and a metal residue and an ionic residue that are easy for water vapor to penetrate and absorb moisture during the constant temperature and humidity test, promotion of metal dissolution, that is, migration, near the conductor circuit is suppressed. As a result, the insulation between lines between the conductor circuits is improved.

[0010] In addition, with regard to abnormal plating deposition, there is no metal residue between the conductor circuits, and there is no resin surface layer having a porous uneven shape that easily traps hydrogen generated during nickel plating. Since active hydrogen is partially oxidized by the added -OOH or the like, nickel deposition between conductor circuits can be significantly suppressed.

On the other hand, wet etching is performed by lightly etching using a solution containing an oxidizing agent having a high oxidizing power such as chromate, chromate, dichromate, manganate, and permanganate. Is valid. in this case,
As a result, the resin surface layer having the porous irregularities is dissolved and removed, and the metal etching residue (catalyst Pd when the underlying conductive film is formed and copper etching residue after the circuit is formed) existing in the concave portion on the surface of the insulating film is also removed. The interline insulation between the circuits is improved, and the deposition of plating between conductors at the time of metallizing the surface of the conductor circuit can be suppressed. However, if the processing time is long, a resin surface layer having a porous uneven shape is newly formed, and line insulation between the conductor circuits is reduced.

As a method of removing the insulating resin surface between the conductor circuits, it is of course possible to use both a dry process and a wet process. In addition, the present invention is not limited to the build-up method using a photosensitive resin as an interlayer insulating film, but may be a method of forming a via hole by a laser using a thermosetting resin as an interlayer insulating film. The method can be applied to all the build-up methods including a step of roughening the insulating resin in order to reduce the cost.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a multilayer wiring board according to the present invention will be described below with reference to FIG.

(Embodiment 1) Wiring board 1 shown in FIG.
00, a glass cloth substrate was impregnated with epoxy resin and solidified, and copper foil was adhered on both sides of the laminate (copper foil thickness 1).
8 μ) was prepared, and a circuit board 101 formed as a first wiring layer on a copper foil in advance by a known method was used as a sample substrate.

Next, as shown in FIG. 1B, an insulating layer 102 was formed on the wiring substrate by applying a spray coater (about 50 μm). The insulating resin used was a photosensitive resin composition, which was obtained by mixing (a) to (c) and an appropriate amount of a solvent (ethyl cellosolve), heating and stirring at 80 ° C. for 30 minutes, and then heating the other components (d) at room temperature. To (H) and kneaded with a three-roll mill.

(A) diallyl phthalate resin 100 g (b) epoxy resin (Epicoat 828) 30 g (c) pentaerythritol triacrylate 20 g (d) benzoin isopropyl ether 4 g (e) dicyandiamide 4 g (f) 2,4-diamino-6 -[2'-Methylimidazolyl- (1 ')]-ethyl-s-triazine 1g (g) Fine particle silica 20g (h) Others (additives for improving coating characteristics) Proper amount Next, FIG. As shown in the drawing, a 400 W high-pressure mercury lamp was used for exposure to UV light for 2 minutes through a negative mask on which a via hole pattern was formed, and a via hole 103 was formed in a desired portion by development.

Subsequently, as shown in FIG. 1D, the surface of the resin layer 102 is subjected to a surface roughening treatment in order to secure an adhesive strength between the insulating resin layer 102 and the underlying conductive film in a later step. The surface 102 'was formed. As a roughening solution, a potassium permanganate solution was used, immersed in this solution for 10 to 20 minutes, and then manganese dioxide was neutralized with hydroxylamine hydrochloride.

Further, as shown in FIG. 1E, as a pretreatment for forming the underlying conductive film 104 by plating, the roughened layer 102 'of the substrate is activated by immersing it in a Sn, Pd-based catalyst solution. The underlying conductive film 104 was formed by electroless copper plating. Thereafter, through a pretreatment step of electrolytic copper plating by washing the substrate, thick copper electroplating was performed to form a plated conductive film 105 shown in FIG. 1 (f).

Next, as shown in FIG. 1 (g), wiring patterns of the plated conductive films (104, 105) were formed by a selective etching method. That is, a photosensitive etching dry film is laminated on the plating conductive film 105 of the substrate by a conventional method, and after being exposed through a predetermined circuit pattern mask, a circuit having a width of about 100 μm is formed on the resin through development, etching, and peeling steps. (A two-layer structure of 104 ′ and 105 ′) was formed as a second wiring layer.

Next, as shown in FIG. 1 (h), the substrate on which the conductor circuit was formed was subjected to plasma etching. Oxygen was used as an etching gas. The dry etching apparatus and processing conditions used are shown below.

Apparatus: O ₂ plasma asher (DEM-451M manufactured by Nidec Anelva) O ₂ flow rate: 50 sccm Gas pressure: 10 pa RF power: 300 W Self-bias: −710 V Processing time: 5 to 30 minutes After plasma etching, the insulating resin surface The residue layer was removed by washing with water. Washing was performed in running water for 2 minutes.

Thereafter, with respect to the formation of the third wiring layer, the same operations as those from the formation of the insulating layer 102 in FIG. 1B to the step of forming the second wiring layer in FIG. After the formation of the three wiring layers, the outermost insulating resin surface was subjected to plasma etching under the same conditions as described above, and finally, a solder resist was applied, exposed, and developed to produce a multilayer wiring board having a three-layer structure.

Example 2 A multilayer wiring board was manufactured using the same photosensitive insulating resin as in Example 1 and in the same process as in Example 1. The difference from the first embodiment is that UV / O ₃ treatment is performed as etching of the resin surface between the conductor circuits after the formation of the conductor circuits. The processing conditions are shown below.

O ₃ flow rate: 8 NL / min Temporary current: 5 A Temperature: 160 ± 10 ° C. Distance from lamp: 15 cm Processing time: 5 to 20 minutes Multilayer wiring of the present invention manufactured by the method of Example 1 and Example 2 The insulation characteristics of the substrate were evaluated. The insulation characteristics were evaluated by applying a voltage of 50 V in a thermo-hygrostat and measuring the insulation resistance between the outer conductor circuits (150 μ) after 500 hours. The temperature and humidity test environment was set at a temperature of 6
The test was performed at 5 ° C. and 95% humidity. For comparison, the same measurement was performed on a substrate on which no O ₂ plasma treatment or UV / O ₃ treatment was applied to the resin surface between the conductor circuits after the formation of the conductor circuits.

The multilayer wiring boards of the first and second embodiments are
While the initial value before the test was 1 × 10 ⁷ megohms or more, the resistance was kept at 1 × 10 ⁶ megohms or more even after 500 hours of the constant temperature and humidity test. On the other hand, when no O ₂ plasma treatment or UV / O ₃ treatment is applied to the resin surface between the conductor circuits after the formation of the conductor circuits, the resistance value after 500 hours of the constant temperature and humidity test is 1 × 10 ² or less. There were many substrates. From this, it is understood that the multilayer wiring board according to the present invention exhibits better insulating properties than the board manufactured by the conventional method.

Example 3 The substrate manufactured by the method of Example 1 was used, and electroless nickel plating and displacement gold plating were applied as surface metallization of the outermost conductor circuit. The plating solution and plating conditions used are as follows.

(Electroless Nickel Plating) ICP Nicoron U (Ni-P) manufactured by Okuno Pharmaceutical Co., Ltd. Liquid temperature 85 ° C. Plating time 20 minutes (displacement gold plating) Lectroless Prep Liquid temperature 90 manufactured by Nippon Electroplating Engineers Co., Ltd. C. Plating time: 20 minutes After the electroless nickel plating and the displacement gold plating, the surface of the substrate was observed with a metallographic microscope. As a result, no short circuit was observed even at the narrowest portion (150 μ) between the outermost conductor circuits. In contrast, O ₂ after the conductor circuit formation
On the substrate not subjected to the plasma treatment, occurrence of a short circuit between the narrowest conductor circuits after nickel plating was observed, so that the effectiveness of the manufacturing method shown in this example was confirmed.

Example 4 The substrate manufactured by the method of Example 2 was used, and electroless nickel plating and displacement gold plating were applied as a surface metallization of the outermost conductor circuit. The plating solution and plating conditions used are as described in Example 3.

When the surface of the substrate was observed with a metallographic microscope after electroless nickel plating and displacement gold plating, no occurrence of short circuit was observed even in the narrowest portion (150 μm) between the outermost conductor circuits.

Example 5 Using the same photosensitive insulating resin as in Example 1, a multilayer wiring board was manufactured in the same steps as in Example 1. The difference from the first embodiment is that a potassium permanganate solution is used for etching the resin surface between the conductor circuits after the outermost conductor circuit is formed. The composition of the processing solution and the processing conditions are shown below.

Composition: potassium permanganate 0.1-0.5 mol / l (liter) Sodium hydroxide 0.2-0.4 mol / l (liter) Liquid temperature: 50-90 ° C. Processing time: 3-5 minutes Using the substrate manufactured by this method, electroless nickel plating and displacement gold plating were applied as surface metallization of the outermost conductor circuit. The plating solution and plating conditions used are as described in Example 3.

When the surface of the substrate was observed with a metallographic microscope after electroless nickel plating and after substitutional gold plating, no short circuit was observed even in the narrowest portion (150 μm) between the outermost conductor circuits.

[0033]

According to the present invention, a highly reliable build-up multilayer wiring board having excellent line insulation properties between conductor circuits can be easily manufactured. Further, according to the present invention, a build-up substrate capable of performing high-yield surface metallization with no abnormal deposition of plating between the plated conductor circuits even when the interval between the outermost conductor circuits is small can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a multilayer wiring board according to one embodiment of the present invention.

[Explanation of symbols]

 100: double-sided copper-clad laminate, 101: circuit pattern, 102: photosensitive insulating resin layer, 102 ': surface-roughened insulating resin layer, 103: via hole, 104: underlying conductive film, 104': circuit pattern, 105: plating conductive film, 105 ′: circuit pattern, 106: gap between circuit patterns.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Makio Watanabe 216 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.

Claims (8)

[Claims] In a method of manufacturing a multilayer wiring board by a build-up method by alternately repeating a conductive circuit forming step and an interlayer insulating film forming step, an insulating resin surface between the conductive circuits is removed by etching after forming the conductive circuits. A method for manufacturing a multilayer wiring board, comprising: 2. The step of removing the surface of the insulating resin by etching includes the steps of removing an organic component using a dry process and concentrating an inorganic component on the resin surface, and a step of removing the concentrated inorganic component by washing with water. 2. The method for manufacturing a multilayer wiring board according to claim 1, comprising: 3. The method according to claim ₂ , wherein O ₂ plasma is used as said dry process. 4. The method according to claim 2, wherein UV / O ₃ is used as said dry process. 5. A method for etching an insulating resin surface according to claim 1, wherein a solution containing an oxidizing agent having a large oxidizing power is used, and the insulating resin surface is lightly etched and then subjected to a neutralization process. Item 2. The method for manufacturing a multilayer wiring board according to Item 1. 6. The oxidizing agent having a large oxidizing power is chromic acid,
5. The method for manufacturing a multilayer wiring board according to claim 4, comprising a chromate, a dichromate, a manganate, or a permanganate. 7. A photosensitive material comprising the interlayer insulating film according to claim 1 comprising a polyfunctional unsaturated compound which is solid at least at room temperature, an epoxy resin, an acrylate monomer, a photopolymerization initiator, an amine-based thermosetting agent, and an inorganic filler. A method for producing a multilayer wiring board comprising a conductive insulating resin composition. 8. An interlayer insulating film according to claim 1, wherein a polyfunctional solid epoxy resin having a plurality of functional groups obtained by addition reaction of at least an unsaturated group, an acrylate monomer, a photopolymerization initiator, an amine-based thermosetting agent, and an inorganic material. A method for producing a multilayer wiring board comprising a photosensitive insulating resin composition comprising a filler.