JPH10271088A5

JPH10271088A5 -

Info

Publication number: JPH10271088A5
Application number: JP1997075669A
Authority: JP
Filing date: 1997-03-27
Publication date: 2004-11-25
Anticipated expiration: 2017-03-27

Description

【０００１】
【発明の属する技術分野】
本発明は、周波数成分が互いに直交関係にある複数のキャリアを用いて信号を変調した直交周波数分割多重被変調信号の受信装置に関する。[0001]
[Technical Field to which the Invention Belongs]
The present invention relates to a receiver for an orthogonal frequency division multiplexed modulated signal obtained by modulating the signal using a plurality of carriers whose frequency components are orthogonal to one another.

【０００６】
ＤＡＢ信号は、現在のところ、モード１、２、３、４の信号が知られている。ＤＡＢ信号では、基本周期として、Ｔ（＝１／２０４８ＭＨｚ＝０．４８８２８μsec ）が定められている。ここでは、モード１のＤＡＢ信号を代表して図５に示す。図５では、この基本周期Ｔと、時間とが併記されている。モード１のＤＡＢ信号の１フレームは、１９６６０８Ｔ（＝９６ｍsec ）で、継続時間が２６５６Ｔ（＝１．２９７ｍsec ）の１個のヌルシンボル（シンボル番号Ｉ＝０）と、それに続く継続時間が共に２５５２Ｔ（＝１．２４６ｍsec ）の７６個のシンボル（シンボル番号Ｉ＝１〜７６）から構成されている。[0006]
Currently, DAB signals are known in modes 1, 2, 3, and 4. The fundamental period of a DAB signal is defined as T (= 1/2048 MHz = 0.48828 μsec ). A representative DAB signal in mode 1 is shown in FIG. 5, which shows both the fundamental period T and time. One frame of a mode 1 DAB signal is 196608T (= 96 msec), and is composed of one null symbol (symbol number I = 0) with a duration of 2656T (= 1.297 msec), followed by 76 symbols (symbol numbers I = 1 to 76), each with a duration of 2552T (= 1.246 msec).

【０００７】
シンボル番号Ｉ＝１〜７６のシンボルは、それぞれその始めの部分の継続時間が５０４Ｔ（＝２４６μsec ）のガードインターバルと、それに続く継続時間が２０４８Ｔ（＝１ｍsec ）の有効シンボルから構成されている。シンボル番号Ｉ＝１〜７６の各シンボルの有効シンボルには、ｋ＝１５３６個の互いに周波数を異にするマルチキャリアが含まれている。０で示されるキャリアが中心周波数のキャリア（そのキャリアの周期がＴである）、１５３６／２（＝７６６）で示されるキャリアが最高周波数のキャリア、−１５３６／２（＝−７６６）で示されるキャリアが最低周波数のキャリアである。１シンボルのデータ量は、１５３６波あり、そのデータ量は１５３６×２ｂｉｔｓ、４８ＣＵ（キャパシティユニット）×６４ｂｉｔｓある。[0007]
Each symbol with symbol numbers I = 1 to 76 consists of a guard interval with a duration of 504T (= 246 μsec) at the beginning, followed by an effective symbol with a duration of 2048T (= 1 msec). Each effective symbol with symbol numbers I = 1 to 76 includes k = 1536 multi-carriers with different frequencies. The carrier indicated by 0 is the center frequency carrier (the carrier period is T), the carrier indicated by 1536/2 (= 766) is the highest frequency carrier, and the carrier indicated by -1536/2 (= -766) is the lowest frequency carrier. One symbol has 1536 waves, and the data volume is 1536 x 2 bits, or 48 CUs (capacity units) x 64 bits.

【０００８】
シンボル番号Ｉ＝１〜７６のシンボルの全体がＯＦＤＭ（オーソゴナルフリケンシディビジョンマルチプレクス：直交周波数分割多重）シンボルと称されている。[0008]
The symbols with symbol numbers I =1 to 76 are all called OFDM (Orthogonal Frequency Division Multiplex) symbols.

【０００９】
例えば、モード１の場合を例にとれば、シンボル番号Ｉ＝０のヌルシンボル、Ｉ＝１のシンボルはＴＦＰＲシンボル（時間周波数位相基準シンボル）とそれぞれ呼ばれ、これら２つのシンボルは、シンクロナイゼイションチャンネル（同期チャンネル）と呼ばれている。シンボル番号Ｉ＝２〜４はＦＩＣ｛ファスト（高速）インフォメーションチャンネル｝と呼ばれ、ＦＩＣ全体は１２個のＦＩＢ（ファストインフォメーションブロック）に分割される。残りのシンボル番号Ｉ＝５〜７６は４つのＣＩＦ（コモンインターリーブドフレーム）と呼ばれるものに分割される。[0009]
For example, in mode 1, the null symbol with symbol number I = 0 and the symbol with symbol number I = 1 are called TFPR symbols (time frequency phase reference symbols), and these two symbols are called synchronization channels. Symbol numbers I = 2 to 4 are called FIC (Fast Information Channel), and the entire FIC is divided into 12 FIBs (Fast Information Blocks). The remaining symbol numbers I = 5 to 76 are divided into four CIFs (Common Interleaved Frames).

【００４０】
図２Ｂに示すように、フェージングやマルチパスによって、複数のキャリアのレベルｒ₁、ｒ₂、ｒ₃、…………、ｒ_(M-1)、ｒ_M間に大きな差があるときは、ＡＧＣ２８によって、可変利得増幅器２４の利得下げるようにする。即ち、このＡＧＣ２８では、１フレーム中のＭ個のキャリアのうち、所定基準レベル以上のものが所定個数ｍ以上あるととき、可変利得増幅器２４の利得を下げ、所定個数ｍ未満のときは、可変利得増幅器２４の利得を上げるように、可変利得増幅器２４の利得を制御する。又、１フレーム中のＭ個のキャリアのうち、所定基準レベル以上のものが所定個数ｍ未満のときは、ＡＧＣ６１よりの自動利得制御信号によって、ＡＧＣ１６、２８の可変時定数回路の時定数を大きくして、応答速度を低速にする。因み、図２Ａは、複数のキャリアのレベルｒ₁、ｒ₂、ｒ₃、…………、ｒ_(M-1)、ｒ_Mが揃っている場合を示す。尚、Ｍは、モード１の直交周波数分割多重被変調信号の場合、１５３６である。[0040]
As shown in FIG. 2B , when there is a large difference between the levels _r1 , _r2 , _r3 , ..., r _(M-1) , and _rM of multiple carriers due to fading or multipath, the AGC 28 lowers the gain of the variable gain amplifier 24. That is, the AGC 28 controls the gain of the variable gain amplifier 24 so that when a predetermined number m or more of the M carriers in one frame are above a predetermined reference level, the gain of the variable gain amplifier 24 is lowered, and when the number is less than the predetermined number m, the gain of the variable gain amplifier 24 is increased. Furthermore, when the number of the M carriers in one frame that are above the predetermined reference level is less than the predetermined number m, the automatic gain control signal from the AGC 61 increases the time constant of the variable time constant circuit of the AGC 16, 28, thereby slowing down the response speed. Incidentally, FIG. 2A shows a case where the levels _r1 , _r2 , _r3 , ..., r _(M-1) , and _rM of multiple carriers are the same. Note that M is 1536 in the case of a mode 1 orthogonal frequency division multiplexed modulated signal.

【００４２】
これを図２Ｃを参照して、具体的に説明する。図２Ｃは、差動復号器３５ｂより出力されるデジタル差動レベルΔｒ及びデジタル差動位相Δθを、直交Ｉ、Ｑ座標上の原点Ｏから、第１、第２、第３及び第４象限の点Ｐ１、Ｐ２、Ｐ３、Ｐ４に向かうベクトルで表し、それぞれのベクトルの長さ及び角度をそれぞれΔｒ１〜Δｒ４及びΔθ１〜Δθ４で表したものである。これらの点Ｐ１〜Ｐ４が、半径が１の円周上にあり、即ち、Δｒ１〜Δｒ４が共に１となり、且つ、Δθ１、Δθ２、Δθ３及びΔθ4が、それぞれπ／４、３π／４、−３π／４、−π／４のときは、原点Ｏから点Ｐ１〜Ｐ４に向かうベクトルは基準値（０，０）、（０，１）、（１，１）、（１，０）を示すものとする。そして、基準値（０，０）、（０，１）、（１，１）、（１，０）におけるデジタル差動位相メトリックをそれぞれ７、０、−７、０とする。[0042]
This will be explained in detail with reference to Fig. 2C. Fig. 2C shows the digital differential level Δr and digital differential phase Δθ output from the differential decoder 35b as vectors directed from the origin O on the orthogonal I-Q coordinate system to points P1, P2, P3, and P4 in the first, second, third, and fourth quadrants, with the lengths and angles of each vector being represented as Δr1 to Δr4 and Δθ1 to Δθ4, respectively. When these points P1 to P4 are on a circle with a radius of 1, i.e., Δr1 to Δr4 are all 1, and Δθ1, Δθ2, Δθ3, and Δθ4 are π/4, 3π/4 , -3π/4, and -π/4, respectively, the vectors directed from the origin O to points P1 to P4 indicate the reference values (0,0), (0,1), (1,1), and (1,0). The digital differential phase metrics at the reference values (0,0), (0,1), (1,1), and (1,0) are set to 7, 0, −7, and 0, respectively.

【００４３】
複数のキャリアのうちの任意のキャリアのデジタル差動位相レベルに対し、該任意のキャリアのデジタルレベルが所定基準レベル以上のときは、掛算器６３でにおいて、原点Ｏから点Ｐ１〜Ｐ４に向かうベクトルのデジタル差動位相Δθ１、Δθ２、Δθ３、Δθ４がそれぞれπ／４、３π／４、−３π／４、−π／４の場合、Δθ１、Δθ２、Δθ３、Δθ４の差動位相メトリックは、基準の差動位相メトリック７、０、−７、０にそれぞれ現在のデジタルレベルｒ_t、１シンボル周期前のデジタルレベルｒ_-T及びσ（定数）（ここでは、σ・ｒ_t・ｒ_-T＜１となる）を掛けて、例えば、３、０、−３、０にして、ビタビ復調器３７に供給する。[0043]
When the digital differential phase level of any of the multiple carriers is equal to or higher than a predetermined reference level, and the digital differential phases Δθ1, Δθ2, Δθ3, and Δθ4 of the vectors pointing from the origin O to points P1 to P4 are π/4, 3π/4, −3π/4, and −π/4, respectively, the differential phase metrics of Δθ1, Δθ2, Δθ3, and Δθ4 are multiplied by the reference differential phase metrics 7, 0 , −7 , and 0, respectively, by the current digital level _r , the digital level r _-T of one symbol period earlier, and σ (a constant) (here, σ· _r ·r _-T < 1), to obtain values such as 3, 0 , −3, and 0, and then supplied to the Viterbi demodulator 37.

【００４４】
又、複数のキャリアのうちの任意のキャリアのデジタル差動位相レベルに対し、該任意のキャリアのデジタルレベルが所定基準レベル未満のときは、掛算器６３において、原点Ｏから点Ｐ１〜Ｐ４に向かうベクトルのデジタル差動位相Δθ１、Δθ２、Δθ３、Δθ４がそれぞれπ／４、３π／４、−３π／４、−π／４の場合、Δθ１、Δθ２、Δθ３、Δθ４の差動位相メトリックは、基準の差動位相メトリック７、０、−７、０にそれぞれ０を掛けて、ビタビ復調器３７に供給する。[0044]
Furthermore, when the digital differential phase level of any of the multiple carriers is less than a predetermined reference level, if the digital differential phases Δθ1, Δθ2, Δθ3 , and Δθ4 of the vectors from the origin O toward points P1 to P4 are π/4, 3π/4, −3π/4, and −π/4, respectively, the differential phase metrics of Δθ1, Δθ2, Δθ3, and Δθ4 are multiplied by 0 to the reference differential phase metrics 7, 0, −7, and 0, respectively, and supplied to the Viterbi demodulator 37.

Claims

an automatic gain control means to which a received signal of an orthogonal frequency division multiplexed modulated signal obtained by modulating an information signal using a plurality of carriers whose frequency components are orthogonal to one another is supplied;
a null detection means for detecting a null symbol period of the orthogonal frequency division multiplexing modulated signal ,
When the null symbol period is detected by the null detection means , the response speed of the automatic gain control means is controlled to a slow speed in accordance with the detection output from the null detection means .

a receiver having a demodulator comprising: automatic gain control means to which a received signal of an orthogonal frequency division multiplexed modulated signal obtained by modulating an information signal using a plurality of carriers whose frequency components are orthogonal to one another is supplied; A/D conversion means for A/D converting the orthogonal frequency division multiplexed modulated signal from the automatic gain control means; time synchronization signal generation means to which a digital orthogonal frequency division multiplexed modulated signal from the A/D conversion means is supplied; automatic frequency control means to which the digital orthogonal frequency division multiplexed modulated signal is supplied; fast Fourier transform means to which the automatically frequency controlled orthogonal frequency division multiplexed modulated signal from the automatic frequency control means and the time synchronization signal from the time synchronization signal generation means are supplied; and differential decoding means to which a digital level signal and a digital phase signal from the fast Fourier transform means are supplied, wherein a digital differential phase signal of the digital information signal is obtained from the differential decoding means;
a digital automatic gain control means, to which the digital level signal is supplied, is provided between the fast Fourier transform means and the differential decoding means;
A receiving apparatus characterized in that the response speed of the automatic gain control means is controlled by the automatic gain control signal from the digital automatic gain control means.

further comprising null detection means for detecting a null symbol period of the orthogonal frequency division multiplexing modulated signal from said automatic gain control means;
3. The receiving apparatus according to claim 2, wherein when said null symbol period is detected by said null detection means, the response speed of said automatic gain control means is controlled to a slow speed in accordance with the detection output from said null detection means.

3. The receiving apparatus according to claim 2, wherein when the level of said digital level signal is equal to or lower than a predetermined reference level, the response speed of said automatic gain control means is controlled to a slow speed by an automatic gain control signal from said digital automatic gain control means.

a receiver having a demodulator comprising: automatic gain control means to which a received signal of an orthogonal frequency division multiplexed modulated signal obtained by modulating an information signal using a plurality of carriers whose frequency components are orthogonal to one another is supplied; A/D conversion means for A/D converting the orthogonal frequency division multiplexed modulated signal from the automatic gain control means; time synchronization signal generation means to which a digital orthogonal frequency division multiplexed modulated signal from the A/D conversion means is supplied; automatic frequency control means to which the digital orthogonal frequency division multiplexed modulated signal is supplied; fast Fourier transform means to which the automatically frequency controlled orthogonal frequency division multiplexed modulated signal from the automatic frequency control means and the time synchronization signal from the time synchronization signal generation means are supplied; and differential decoding means to which a digital level signal and a digital phase signal from the fast Fourier transform means are supplied, wherein a digital differential phase signal of the digital information signal is obtained from the differential decoding means;
A receiving device comprising multiplying means for multiplying a digital differential phase level of an arbitrary carrier among a plurality of carriers by a current digital level of the arbitrary carrier by a digital level of one symbol period earlier when the digital level of the arbitrary carrier is equal to or higher than a predetermined reference level, and for outputting the result, and for multiplying the digital level of the arbitrary carrier by a 0 level when the digital level of the arbitrary carrier is lower than the predetermined reference level.