JPH1027863A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] In a semiconductor package, a power supply terminal, an input / output signal terminal, and the like are used in a mixed state under the limitation of the number of pin terminals. Cannot be used for transmission signals. A semiconductor package is made of a conductive material dedicated to a power supply voltage Vdd and a conductive material dedicated to a ground voltage Vss.
By providing the power terminal, the transmission signal, the power supply voltage Vdd,
It is separated from the ground voltage vss. As a result, all the lead frames inside the package can be constituted only by transmission signals.
A potential is supplied to the power supply voltage Vdd portion or the ground voltage Vss portion inside the semiconductor chip 105 from the conductive portions 101 and 102 of the semiconductor package. Therefore, it is possible to use all the number of terminals of the lead frame exclusively for transmitting input / output signals without going through the lead frame section 106. [Effect] All input / output pads can be used as a signal transmission system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor package which is a part of a signal transmission path between another signal on a component substrate of a final product and the inside of the semiconductor device. , Power supply voltage Vdd terminal and ground voltage V
The ss terminal is separated from other signal transmission paths, and the power supply voltage Vdd terminal of the semiconductor package and the ground voltage Vs
The present invention relates to a semiconductor device including a pad for a power supply voltage Vdd terminal connected to an s terminal and a semiconductor chip having a pad for a ground voltage Vss terminal.

[0002]

2. Description of the Related Art FIG. 4 shows an example in which a conventional semiconductor device is used in a package.

[0003] In the drawing, reference numeral 401 is usually enclosed by a resin material such as plastic and is hermetically sealed, but is shown in a lid shape for the explanation of the present invention. In the figure, reference numeral 402 denotes a terminal (hereinafter, referred to as a "pad") provided on a semiconductor device and a semiconductor chip and an external connection terminal (hereinafter, referred to as a "pin") for a signal transmission path between the package and the outside. This is the lead frame to be connected. Input signal, or output signal, or input / output signal,
Further, the power supply voltage Vdd and the ground voltage Vss are supplied from outside or transmitted to outside. 40 in the figure
3 is a pin mounted on the product circuit board from the semiconductor package. In the figure, reference numeral 404 denotes a semiconductor chip. 405 in the figure
Reference numeral denotes a semiconductor package for enclosing a semiconductor chip, which is usually formed of a resin such as plastic as in the case of 401 in the figure. That is, the power supply voltage Vd of the semiconductor chip 404 in the figure
d and the ground voltage Vss are handled in the same manner as other input signals, output signals, or input / output signals, and are mounted on a product circuit board through the lead frame of 402 in the figure and the pins of the semiconductor device in 403 in the figure. Is done.

[0004]

The conventional semiconductor device shown in FIG. 4 has a required power supply voltage Vdd within a limited number of input / output terminals in advance in a semiconductor package and a semiconductor chip. The number and the number of ground voltages Vss are ensured, and the rest constitutes an input terminal, an output terminal, and an input / output terminal, thereby realizing signal exchange with a product circuit board.
Therefore, depending on the operating frequency of the semiconductor chip and the specifications of the final product, the number of input / output signal terminals for signal transmission increases, and if the power supply voltage Vdd terminal and the ground voltage Vss terminal are sufficiently provided, the semiconductor chip or the semiconductor The number of input / output terminals, which is limited by the number of pin terminals of the package, is exceeded, which hinders the selection of an optimum semiconductor chip or necessitates an increase in the size of the semiconductor chip.

[0005]

An object of the present invention is to at least distribute input / output signals to normal pins of a semiconductor chip, and to provide at least two or more conductive materials for a power supply voltage Vdd terminal and a ground voltage Vss. Is provided separately from a normal read frame, and by using the same, a dedicated pin terminal different from the pin terminal of the input / output signal is provided outside, and the power supply voltage is applied to the semiconductor chip therefrom. Vd
The problem can be solved by supplying d and the ground voltage Vss.

That is, the semiconductor device according to claim 1 is
In a semiconductor device in which a terminal provided on a semiconductor chip is connected to an external connection terminal, a first external connection terminal connected to a signal terminal provided on the semiconductor chip; And a second external connection terminal connected to the power supply terminal.
The terminal for external connection and the second terminal for external connection are formed from different lead frames.

Further, the semiconductor device described in claim 2 is
2. The semiconductor device according to claim 1, wherein a horizontal position of a lead frame forming the first external connection terminal is different from a horizontal position of a lead frame forming the second external connection terminal. .

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the conductive region of the second external connection terminal is located inside the conductive region of the first external connection terminal. It is characterized by being arranged.

The semiconductor device according to claim 4 is the semiconductor device according to claim 2 or 3, wherein
Wherein the shape of the external connection terminal is different from the shape of the second external connection terminal.

[0010]

According to the above construction of the present invention, a signal terminal whose number of terminals is limited by a semiconductor chip or a semiconductor package (the signal terminal includes an input terminal, an output terminal, a bidirectional input / output terminal, etc.). The power supply voltage Vdd terminal and the ground voltage Vss terminal do not need to be allocated, and can be occupied only for signal transmission. Also, the power supply voltage Vdd
The terminal and the ground voltage Vss terminal can be arranged in the direction of the center of the chip different from the arrangement position of the normal pins, and the supply voltage source is efficiently taken in a wide range without obstructing other signal lines. Therefore, anxiety factors such as a voltage drop are extremely reduced. Further, the power supply voltage Vdd terminal and the ground voltage V
By configuring the ss terminal etc. in a shape different from the normal pin shape, low resistance and low impedance effects can be expected,
Further, mixed mounting such as a ball grid array method is also possible.

[0011]

FIG. 1, FIG. 2, and FIG. 3 show an embodiment of the present invention.

FIG. 1 shows an embodiment in which a semiconductor chip is sealed using the semiconductor package of the present invention. In the figure, 101 and 102 are semiconductor packages of the present invention.
This is the lid on the top side of Ji. Usually, it is formed of a resin material such as plastic and sealed, but a conceptual diagram of the structure is described for the description of the present invention. In the figure, reference numerals 101 and 102 are formed of a conductive material, and are connected to a power supply voltage line on a circuit board of a final product through a pin terminal 103 in the figure, and the other is connected to a ground voltage line. And 10 in the figure
5, a power supply voltage Vdd portion of an internal circuit portion of the semiconductor chip,
Alternatively, a potential is supplied to the ground voltage Vss section via 101 and 102. In the figure, reference numeral 104 denotes a pin terminal dedicated to an input / output transmission signal. Various input / output transmission signals are transmitted and received from 104. In the figure, reference numeral 106 denotes a conventional lead frame.
Like the system, the signal transmission path from the final product circuit board to the circuit inside the semiconductor chip or the signal transmission path from the circuit inside the semiconductor chip to the final product circuit board
This is a do-frame part. That is, 104 in the figure and 105 in the figure
Are connected by a method such as a lead wire or a film tab. In the prior art described above, a plurality of power supply voltage Vdd terminals and a plurality of ground voltage Vss terminals must be provided within the number of the lead frames, and the lead frames exclusively used for signal transmission are used. Is the power supply voltage Vdd
The total amount of the terminal and the ground voltage Vss terminal is limited. In the present invention shown in FIG. 1, a power supply voltage Vdd terminal and a ground voltage Vss terminal are connected to a conductive portion of a semiconductor package.
1 and 102, the lead frame 106 in the figure
It is possible to use all the number of terminals of the lead frame exclusively for transmitting input / output signals without passing through the frame section. 107 in the figure is 101 in the top view of the semiconductor package.
And for electrically isolating 102 in the figure from the lead frame 106 in the figure.

FIG. 2 is a sectional view of a semiconductor package according to the present invention. In the figure, reference numeral 201 denotes a lid portion of the semiconductor package of the present invention. In the figure, reference numeral 202 denotes a semiconductor chip. 20 in the figure
1, a semiconductor chip 202 is arranged, and a power line dedicated lead portion 206 in the figure is efficiently joined to an internal circuit power supply voltage Vdd line or a ground voltage Vss line of the semiconductor chip. In the power-only lead portion 206 in the figure, a low-resistance material or the like is used and joined by a technique such as a bump. As described with reference to FIG. 1, the lead for exclusive use of the power supply can be installed in various shapes, so that the restriction on the arrangement is reduced, and 101 or 102 in FIG. 1 and 206 in FIG.
Below, any number of semiconductor chips can be arranged at any place on the semiconductor chip, so that a stable semiconductor circuit can be supplied with extremely few malfunctions due to a voltage drop or the like. In the figure, reference numeral 203 denotes a lead portion for input / output signals of the semiconductor chip, which interfaces with an external final product circuit board through a pin terminal of the semiconductor package 204 in the figure.
In the figure, reference numeral 205 denotes a resin-encapsulated portion of the semiconductor package.
In the figure, reference numeral 207 denotes an insulator for preventing the short circuit between the 206 and the read / write signal exclusive lead 203.
In the drawing, reference numeral 208 denotes a power-only lead portion and reference numeral 20 denotes a semiconductor chip.
This is an example of a case where a bump bonding portion obtained by bonding No. 3 with a bump or the like is used. In the figure, reference numeral 209 denotes a connection point between the semiconductor package and an external power supply line of the final product circuit board.

FIG. 3 is basically the same as FIG. 1, but shows an embodiment in which the shapes of the power-only leads 101 and 102 in FIG. 1 and 301 and 302 in FIG. 3 are changed. is there. In the figure, reference numerals 301 and 302 denote power-only leads. 3 in the figure
Reference numeral 03 denotes a pin terminal dedicated to a power supply, which is connected to a final product substrate. In the figure, reference numeral 304 denotes a pin terminal dedicated to input / output signals. This is the same specification as the conventional technology. 305 in the figure
Is a semiconductor chip. In the figure, reference numeral 306 denotes a lead section dedicated to input / output signals. In the figure, reference numeral 307 denotes a power-only lead section 30.
1, 302 and an insulator for electrically separating the input / output signal lead portion.

[0015]

As described above, the power supply voltage Vdd or the ground voltage Vss of the internal circuit of the semiconductor chip is set to at least two or more first and second conductors different from a normal lead frame. Using semiconductor materials, the first,
By supplying the respective second potentials, providing an input / output signal dedicated terminal and a power dedicated pin terminal as pin terminals of the semiconductor package, and connecting them to a final product circuit board, The number of signals transmitted between the internal circuit of the semiconductor chip and the final product substrate circuit by the conventional read frame is not limited to the power supply voltage Vdd or the ground voltage Vss, and all the numbers are dedicated to input / output signals. As a result, a highly integrated and highly reliable semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment in which a semiconductor chip is arranged using a semiconductor package of the present invention.

FIG. 2 is a diagram showing one embodiment of a cross-sectional view when a semiconductor chip is arranged using the semiconductor package of the present invention.

FIG. 3 is a diagram showing one embodiment in which a semiconductor chip is arranged using the semiconductor package of the present invention.

FIG. 4 is a diagram showing one embodiment of a conventional semiconductor device in which a semiconductor chip is sealed in a semiconductor package.

[Explanation of symbols]

Reference numeral 101: Upper cover of the semiconductor package and a lead portion dedicated to power supply 102 ... Upper cover of the semiconductor package and a lead portion dedicated to power supply 103: Power supply voltage Vdd or ground voltage Vss
Supply lead terminal 104: Pin terminal dedicated to input / output transmission signal 105: Semiconductor chip. 106: Lead frame 107: Insulator (insulating film) 108: Lower part of semiconductor package 201: Upper lid of semiconductor package and lead part exclusively for power supply 202 ... Semiconductor chip 203: Lead section dedicated to input / output transmission signals 204: Pin terminal dedicated to input / output transmission signals 205: Lower part of semiconductor package 206: Lead section dedicated to power supply 207: Insulation Body (insulating film) 208: Power supply dedicated lead bump junction 209: Power supply dedicated pin terminal 301: Upper cover of semiconductor package and power supply dedicated lead 302: Semiconductor package Upper lid and power supply lead section 303: power supply voltage Vdd or ground voltage Vss
Supply lead terminal 304 ... I / O transmission signal dedicated pin terminal 305 ... Semiconductor chip. 306: Lead frame 307: Insulator (insulating film) 308: Lower part of semiconductor package 401: Cover of conventional semiconductor package 402: Lead frame 403 ... I / O terminal 404 ... Semiconductor chip 405 ... Lower part of semiconductor package

Claims (4)

[Claims] 1. A semiconductor device having terminals provided on a semiconductor chip connected to external connection terminals, wherein a first terminal connected to a signal terminal provided on the semiconductor chip is provided.
, And a second external connection terminal connected to a power supply terminal provided on the semiconductor chip, wherein the first external connection terminal and the second external connection terminal A semiconductor device comprising a lead frame different from a terminal. 2. The semiconductor device according to claim 1, wherein a horizontal position of a lead frame forming said first external connection terminal is different from a horizontal position of a lead frame forming said second external connection terminal. A semiconductor device characterized by the above-mentioned. 3. The semiconductor device according to claim 2, wherein a conductive region of said second external connection terminal is disposed inside a conductive region of said first external connection terminal. Semiconductor device. 4. The semiconductor device according to claim 2, wherein a shape of said first external connection terminal and said second external connection terminal are different from each other.
Wherein the external connection terminals have different shapes.