JPH1027891A - Non-volatile semiconductor memory - Google Patents

Abstract

(57) Abstract: A nonvolatile semiconductor memory capable of improving reliability is provided. SOLUTION: A P-type single crystal silicon substrate has N
^{A ++} type source region 2 and an N ⁺ type drain region 3 are formed. In the memory operation region Z1, a floating gate electrode 6 is formed on a silicon substrate via a silicon oxide film, and a control gate electrode 8 is formed on the floating gate electrode 6 via a silicon oxide film.
Are formed. In the transistor in the dummy cell region Z2, which is in contact with the memory operation region Z1, a floating gate electrode 13 is formed on the LOCOS oxide film 12, and a strip-shaped control gate electrode 15 is formed on the floating gate electrode 13 via a silicon oxide film. . In the dummy cell region Z2, the drain region 3, the source region 2, and the control gate electrodes 8, 15 are at the substrate potential by the aluminum wiring 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable nonvolatile semiconductor memory.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory (EEPROM)
In the write operation, as shown in FIG.
By applying a control gate voltage VG higher than D, hot electrons generated near the drain are injected into the floating gate electrode. As shown in FIG. 6, the erase operation is performed by grounding the control gate and applying a high voltage V to the source.
S is applied and FN current between the source region and the floating gate electrode is used.

Here, in order to make the characteristics uniform in a writable and erasable nonvolatile memory, it is essential to place a dummy cell which does not perform a memory operation in the periphery. The role of this dummy cell is as follows. The performance of the memory transistor is greatly affected by the shape of the gate electrode. The shape of the gate electrode is determined by the material of the photoresist, exposure conditions, and etching, and these conditions are strongly affected by the peripheral pattern. The memory area has a regular array, but the regularity is lost in the periphery. As a result,
Even if the same planar structure is drawn, the cross-sectional shape differs at the outermost periphery. As a result, the peripheral memory transistors have different write characteristics. To avoid this, dummy cells having the same planar structure and not operated are arranged in the outermost periphery of the memory region or in the region inside the other stage.

FIGS. 7 and 8 show the specific structure. FIG. 7 is a plan view of a nonvolatile memory area including a dummy cell. FIG. 8 is a sectional view taken along line CC of FIG. FIG.
In FIG. 8, a dummy cell formation region (dummy cell region) Z2 that is not operated as a storage element is formed on the outer peripheral side of a storage cell formation region (memory operation region) Z1 operated as a storage element. In the drawing, reference numeral 30 denotes a P-type silicon substrate, 31 denotes a source region, 32 denotes a drain region, 33 denotes a tunnel oxide film, 34 denotes a floating gate electrode, and 35 denotes a control gate electrode. Show.

Normally, a cell (transistor) in the dummy cell region Z2 has a control gate electrode 35 connected to the ground,
The drain contact is not connected and the source line is
1 and Z2 are connected in common.

[0006]

However, at the time of erasing, a voltage as high as 12 volts is applied to the source with respect to the ground, and electrons are drawn out of the floating gate electrode 34 of the dummy cell at the time of erasing, resulting in an over-erased state. As a result, in this state, the dummy cell is in an over-erased state unless irradiated with ultraviolet light, a high electric field is generated in unnecessary bits, and the memory cell has a negative threshold voltage, that is, a depletion state in the over-erased state. This cell does not affect other cells, but the cell that does not operate has a shortage of electrons, and the tunnel oxide film 3
3, an electric field is applied, which is not preferable in terms of reliability.

An object of the present invention is to provide a nonvolatile semiconductor memory capable of improving reliability.

[0008]

According to a first aspect of the present invention, an outer peripheral side of a formation region of a storage cell operated as a storage element in a semiconductor substrate is formed as a formation region of a dummy cell not operated as a storage element. The cell formation region for dummy cells and the cell formation region for dummy cells are separated by a LOCOS oxide film.

With this configuration, even if a high voltage is applied to the source during writing / erasing of the cells in the storage cell formation region, no special electric field is applied to the dummy cells in the dummy cell formation region. That is, the source region of the dummy cell is electrically separated from the memory region that operates normally, and no voltage is applied to the source region of the dummy cell, and no extra voltage is applied to the floating gate electrode regardless of writing / erasing. Therefore, the state is always in an equilibrium state, and the reliability can be improved.

A second aspect of the present invention is characterized in that the source region, the drain region, and the control gate electrode in the dummy cell formation region in the first aspect of the present invention have a substrate potential. Therefore, the source region of the dummy cell is always at the same potential as the substrate potential regardless of writing / erasing,
No extra voltage is applied to the floating gate electrode.

According to a third aspect of the present invention, in the first aspect of the present invention, a LOCOS oxide film is formed on a surface of a semiconductor substrate in the dummy cell formation region, and a dummy floating gate electrode and a LOCOS oxide film are formed thereon. It is characterized in that a control gate electrode is arranged. Therefore, since the insulating film between the semiconductor substrate and the floating gate electrode in the dummy cell is thick, electrons are not injected or extracted from the floating gate electrode.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of the flash memory, and FIG. 2 is a sectional view taken along line AA of FIG.

In the plan view shown in FIG. 1, a large number of memory transistors (memory cells) are arranged vertically and horizontally, and a dummy cell region Z2 is formed on the semiconductor substrate on the outer peripheral side of the memory operation region Z1. Memory operation area Z1
Is a formation region of a storage cell operated as a storage element, and a dummy cell region Z2 is a formation region of a dummy cell not operated as a storage element.

The details will be described below. As shown in FIG. 2, a P-type single-crystal silicon substrate 1 serving as a semiconductor substrate has an N ⁺⁺ type source region (impurity diffusion region) 2 and an N ⁺ type drain region (impurity diffusion region) for each cell on its surface. ) 3
Are formed. Source region (impurity diffusion region) 2
Are formed deeper than the drain region (impurity diffusion region) 3. As shown in FIG. 1, a band-shaped N ⁺⁺ type source common line (impurity diffusion region) 4 extends from the source region 2,
The source region 2 of each transistor is connected to the source common line 4.

As shown in FIG. 2, a thin silicon oxide film (or nitride film) 5 having a thickness of about 10 nm as a tunnel insulating film is formed on the silicon substrate 1 in the memory operation region Z1. On the silicon oxide film 5, a floating gate electrode 6 made of polycrystalline silicon for each memory transistor is formed. Floating gate electrode 6
Has a rectangular shape and extends so as to pass between the source region 2 and the drain region 3. Further, a silicon oxide film 7 as an insulating film between gates is formed on the floating gate electrode 6.
A belt-like control gate electrode 8 is formed through the gate electrode. Control gate electrode 8 is made of polycrystalline silicon.

Control gate electrode 8 in memory operation area Z1
On top of this is formed a silicon oxide film 9 as an interlayer insulating film, on which a drain wiring 10 made of aluminum is formed. As shown in FIG. 1, the strip-shaped drain wiring 10 extends in one column (bit line) of the memory operation region Z 1, and extends in one column (bit line) of the memory operation region Z 1 through a contact hole (opening) 11. It is connected to the drain electrode 10 of each transistor. This drain electrode 10
Is connected to an external circuit.

The control gate electrode 8 (word line) extends in a direction perpendicular to the direction in which the drain wiring 3 extends, as shown in FIG. The transistor in contact with the memory operation area Z1 in the dummy cell area Z2 is LOCO
A floating gate electrode 13 is formed on an S oxide film (thick oxide film) 12, and a diffusion layer in the dummy cell region Z2 and the memory operation region Z1 is separated by the LOCOS oxide film 12.
The floating gate electrode 13 is made of polycrystalline silicon, has a rectangular shape, and extends so as to pass between the source region 2 and the drain region 3. Further, a band-shaped control gate electrode 15 is formed on the floating gate electrode 13 via a silicon oxide film 14 as an insulating film.

The other transistors in the dummy cell area Z2 have the same structure as the transistors in the memory operation area Z1. That is, a floating gate electrode 6 made of polycrystalline silicon is formed on a silicon oxide film (or a nitride film) 5, and a band-like control gate is formed on the floating gate electrode 6 via a silicon oxide film 7 as an insulating film. An electrode 8 is formed. Control gate electrode 8 is made of polycrystalline silicon.

The wiring 10 connected to the drain region 3 of the memory operation region Z1 is not connected to the dummy cell region Z2, and another wiring (aluminum wiring) 16 is
Is formed on. The aluminum wiring 16 is electrically connected to the drain region 3, the source region 2, and the control gate electrodes 8 and 15 of the dummy cell region Z2 by contact holes 17, 18, and 19 as shown in FIG. It is connected to the silicon substrate 1 through the hole 20. The substrate contact is made through a P ⁺ type region (not shown) formed in the surface layer of the silicon substrate 1. This aluminum wiring 16 allows dummy cell region Z2
Drain region 3, source region 2, control gate electrode 8,
15 are equal potentials.

Next, the operation of the flash memory thus configured will be described. At the time of writing, hot electrons generated near the drain are injected into the floating gate electrode 8 by applying a control gate voltage VG higher than the drain voltage VD.

At the time of erasing, the control gate electrode 8 is set to the ground potential, and a high voltage (+12 volts) is applied to the source terminal through the source common line 4 to cause the source region 2 to pass through the tunnel oxide film 5. Hot electrons are removed by the FN current between the gate electrode and the floating gate electrode 6.

As described above, the high voltage is applied to the source region 2 at the time of erasing, but the floating gate electrode 13 in the cell adjacent to the memory operation region Z1 in the dummy cell region Z2 is arranged on the LOCOS oxide film 12. Therefore, no strong electric field is applied, and no electron injection / extraction is performed. The other cells in the dummy cell region Z2 are electrically isolated by the LOCOS oxide film 12 (the dummy cell region Z2 and the memory operation region Z1).
Are separated by the LOCOS oxide film 12), no voltage is applied to the source region 2 and the floating gate electrodes 6 and 13 of the dummy cell region Z2 during the memory operation. Further, the source / drain regions 2 and 3 of the dummy cell region Z1 and the control gate electrode 8 are always fixed at the substrate potential, and no voltage is applied to the floating gate electrodes 6 and 13 of the dummy cell region Z2 during operation. In this way, unnecessary voltage is not applied to the dummy cell.

Therefore, no extra voltage is applied to the floating gate electrode of the dummy cell as compared with the memory having the conventional structure shown in FIGS. Therefore, as described above, the floating gate electrode is not over-erased, and no extra electric field is applied to the tunnel insulating film. This eliminates malfunctions and improves reliability.

As described above, the present embodiment has the following features. (A) The LOC between the memory operation area (storage cell formation area) Z1 and the dummy cell area (dummy cell formation area) Z2
Even if a high voltage is applied to the source at the time of writing / erasing a cell in the memory operation area Z1 even when separated by the OS oxide film 12,
No special electric field was applied to the dummy cells in the dummy cell region Z2. That is, the source region 2 of the dummy cell is electrically separated from the memory operation region Z1 in which the normal operation is performed, and no voltage is applied to the source region 2 of the dummy cell, and the floating gate electrodes 6, 13
No extra voltage is applied. Therefore, it is always in an equilibrium state, and malfunction can be suppressed to improve reliability. (B) Since the source region 2, the drain region 3, and the control gate electrodes 8, 15 in the dummy cell region Z2 are set to the substrate potential, the source region 2 of the dummy cell is always at the same potential as the substrate potential regardless of writing / erasing, and the floating gate Electrodes 6, 13
No extra voltage is applied. (C) LO is applied to the surface of the substrate 1 in the dummy cell region Z2.
Since the COS oxide film 12 is formed and the floating gate electrode 13 for dummy and the control gate electrode 15 are arranged thereon, the insulating film between the semiconductor substrate 1 and the floating gate electrode 15 in the dummy cell is thicker. Electrons are not injected or extracted in the floating gate electrode 13. (Second Embodiment) Next, a second embodiment of the present invention will be described, focusing on differences from the first embodiment.

As shown in FIGS. 3 and 4, the dummy cell region Z
2 is an element isolation oxide film LO for all cells.
A COS oxide film 25 is disposed, and a floating gate electrode 1 is formed thereon.
3 and a control gate electrode 15 are arranged. Accordingly, in addition to the effects of the first embodiment, since all the dummy cells are electrically isolated, the occurrence of troubles such as latch-up does not occur.

[Brief description of the drawings]

FIG. 1 is a plan view of a flash memory according to a first embodiment.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a plan view of a flash memory according to a second embodiment.

FIG. 4 is a sectional view taken along line BB of FIG. 3;

FIG. 5 is an explanatory diagram for explaining a write operation.

FIG. 6 is an explanatory diagram for explaining an erasing operation.

FIG. 7 is a plan view of a flash memory for explaining a conventional technique.

FIG. 8 is a sectional view taken along the line CC of FIG. 7;

[Explanation of symbols]

1 ... P-type single crystal silicon substrate as semiconductor substrate, 2 ...
Source region, 3 ... drain region, 5 ... silicon oxide film as insulating film, 6 ... floating gate electrode, 7 ... silicon oxide film as insulating film, 8 ... control gate electrode, 12 ... LOC
OS oxide film, 13 ... floating gate electrode, 14 ... silicon oxide film as insulating film, 15 ... control gate electrode.

Claims (3)

[Claims] A source region and a drain region for each cell are separately formed in a surface layer portion of the semiconductor substrate; a floating gate electrode is disposed on the semiconductor substrate between the two regions via a thin insulating film; In a nonvolatile semiconductor memory in which a control gate electrode extends over a floating gate electrode via an insulating film, a dummy that does not operate as a storage element on an outer peripheral side of a storage cell forming region in the semiconductor substrate that operates as a storage element A non-volatile semiconductor memory, wherein a storage cell formation region and a dummy cell formation region are separated by a LOCOS oxide film. 2. The non-volatile semiconductor memory according to claim 1, wherein a source region, a drain region, and a control gate electrode in the dummy cell formation region have a substrate potential. 3. The semiconductor device according to claim 1, wherein a LOCOS oxide film is formed on the surface of the semiconductor substrate in the dummy cell formation region, and a dummy floating gate electrode and a control gate electrode are disposed thereon. Nonvolatile semiconductor memory.