JPH1027901A - Manufacture of mos transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high speed operation of a MOS transistor and suppression of variations in characteristics, by increasing an on-current and reducing a parasitic capacitance. SOLUTION: A well region 12 is provided on a silicon substrate 11, and an element isolation region 13 is formed therein to demarcate an element region. Impurities are doped into the element region to form a lightly doped source- drain region 14, and an insulating film 15 is deposited on the entire surface of the region 14. The insulating film 15 is formed therein with an opening for exposure of a channel part, impurity doping is carried out through the opening to form a channel doped region 16. The region 16 is thermally oxidized to form a gate oxide film 17, on which an electrically conductive film of tungsten or the like is formed, and then the conductive film and insulating film 15 is subjected to a patterning process to form a gate electrode 18. The laminate is subjected to an impurity coping process with the gate electrode 18 used as a mask to thereby form a heavily doped source/drain region 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and a method for manufacturing the same, and more particularly to an LDD (lightly
The present invention relates to a MOS transistor having a Doped Drain structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a miniaturized MOS transistor, there is a short channel effect in which a threshold voltage is reduced due to a shortened channel length. As a countermeasure for this, a digging gate type transistor has been proposed. I have. In the digging gate method, by digging the gate portion, the junction of the source / drain portion viewed from the gate electrode becomes shallow, and the short channel effect can be suppressed. In addition, by restricting channel implantation to only the gate electrode portion, the impurity concentration in the wells other than the channel portion can be reduced, and the junction capacitance at the source / drain portions can be reduced. In addition, the channel length can be easily reduced by depositing a sidewall such as a silicon oxide film inside the dug portion, and a T-shaped gate electrode having a longer gate length than the channel length can be formed. It is characterized in that the resistance of the gate electrode can be reduced even if the length is shortened.

FIG. 4 shows a conventional digging gate type MO.
FIG. 9 is a cross-sectional view in the order of steps for describing the manufacturing process of the S transistor. This method is, for example, an IEEE ED V
ol. 42, no. 1, p. 94, 1995 and the like. A p-well 32 on an n-type silicon substrate 31
Is formed, a LOCOS oxide film 32 is formed by a selective oxidation method, an active region is defined in the p well, and an n-type impurity is doped in the active region to form an n ⁻ source / drain region 3.
4 is formed. Thereafter, a non-doped silicon oxide film 35 is deposited on the substrate, and the silicon oxide film 35 in the channel portion is formed by photolithography and dry etching.
And etching down the silicon substrate to a predetermined depth. Next, using the silicon oxide film 35 as a mask, an impurity (for example, boron) is doped for adjusting the threshold value (FIG. 4A).

After forming a gate oxide film 37 by thermal oxidation, a tungsten (W) film is deposited, and the tungsten film and the underlying silicon oxide film 35 are patterned to form a T-shaped gate electrode 38. I do. Thereafter, the n ⁺ source
A drain region 39 is formed (FIG. 4A). In this manufacturing method, the n ⁻ source / drain region 34 is formed by etching the silicon substrate when forming a channel portion.
It is cut off to the source side and the drain side.

[0005]

In the above-mentioned conventional digging method, as shown in FIG. 5, there is a problem that the side surface of the gate electrode also becomes a channel, and the actual channel length becomes longer, thereby reducing the on-current. there were. That is, in the conventional digging method, since the channel is formed in a portion deeper than the LDD region (n ^- source / drain region 34), the LD
For example, the depth l of the trench to be dug deeper than the D region is required to be about 0.1 μm, and even if a gate electrode having a channel length of 0.1 μm is manufactured, the substantial channel length is 0.3 μm. In addition, since the silicon substrate serving as a channel is etched, there is a problem that carrier mobility in the channel portion is reduced to about half due to etching damage. Further, in the conventional structure, since the source / drain region and the gate electrode face each other via a thin gate oxide film, a large parasitic capacitance is generated between the gate electrode and the source / drain, and channel-doped impurities are formed in the channel portion. By doping other well regions, the impurity concentration of the well increases, which causes an increase in junction capacitance.

Therefore, the problems to be solved by the present invention are:
It is an object of the present invention to provide a MOS transistor with a reduced effective channel length, reduced parasitic capacitance, improved carrier mobility in a channel, high-speed operation, and low power consumption.

[0007]

According to the MOS transistor of the present invention, a MOS transistor is formed on a silicon substrate via a gate oxide film.
A gate electrode having a V-shape is formed, an insulating film not doped with impurities is formed between the eaves portion of the gate electrode and the silicon substrate, and the low-concentration source / drain region is aligned with the leg portion of the gate electrode. The high concentration source / drain electrodes are formed so as to be aligned with the eaves of the gate electrode. And, preferably,
The gate electrode is formed of a refractory metal such as tungsten.

Further, the method of manufacturing a MOS transistor according to the present invention includes the following steps: (1) The first method includes:
Forming a low-concentration source / drain region by doping a second-conductivity-type impurity in a surface region of a conductive-type semiconductor region; (2) forming an insulating film over the entire surface; and (3) the insulating film. Forming an opening that exposes the surface of the semiconductor region to be a channel region by selectively etching away the semiconductor region; and (4) forming a channel region by doping impurities into the semiconductor region through the opening. (5) forming a gate oxide film on the surface of the semiconductor region exposed by performing thermal oxidation; and (6) forming a conductor layer for forming a gate electrode, and forming the conductor layer and a layer under the conductor layer. Patterning the insulating film to form a gate electrode;
(7) Doping a second conductivity type impurity into a surface region of the semiconductor region using the gate electrode as a mask to form a high concentration source
Forming a drain region.

[Operation] In the manufacturing method according to the present invention, only the insulating film deposited on the substrate is etched and the silicon substrate is not dug, so that the channel length does not increase and the damage to the substrate surface is suppressed. As a result, a decrease in carrier mobility is suppressed. Further, since the substrate is not dug, variations in channel length are suppressed. Also, since channel doping is performed in a self-aligned manner with the gate electrode,
It is possible to realize a reduction in junction capacitance, a suppression of an inverse short channel effect, and the like without increasing the well concentration in portions other than the channel portion. Further, when the gate electrode is formed of a high melting point metal, the gate electrode is not depleted, and a high on-current can be obtained without a decrease in on-current due to depletion.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view in the order of steps for explaining an embodiment of the present invention. Silicon substrate 11
On top, although not required, a well region 12 is formed,
The element isolation region 13 for defining the active region is
It is formed by the S method or the like. Next, an impurity of a conductivity type opposite to that of the well region 12 is doped to form a low concentration source / drain region 14. Thereafter, a non-doped insulating film 15 is deposited on the entire surface of the substrate, the insulating film 15 in the channel portion is removed by etching to form an opening, and an impurity of the same conductivity type as that of the well region 12 is doped. 16 (FIG. 1A).

Next, a gate oxide film 17 is formed on the channel region by thermal oxidation. Thereafter, a conductor film such as tungsten is deposited, and this conductor film and the insulating film 15 thereunder are deposited.
Is patterned to form a T-shaped gate electrode 18 (FIG. 1B). Next, using the gate electrode 18 and the insulating film 15 as a mask, an impurity having a conductivity type opposite to the conductivity type of the well region 12 is doped into the well region to form a high concentration source / drain region 19 [FIG. (C)]. Through the above steps, a MOS transistor in which only the insulating film in the channel portion is dug can be formed. In the transistor of the present invention, when the gate electrode 18 is formed by using a high melting point metal such as tungsten, the impurity to be channel-injected by the work function difference is smaller than that in the case of the polysilicon gate. Since it is not necessary to completely cancel the impurity implanted into the region, the threshold value can be controlled with good controllability.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. 2 and 3 are sectional views in the order of steps showing an embodiment of the present invention. A p-well 22 is formed by doping a p-type impurity (for example, boron) on the surface of the silicon substrate 21, and LOC is formed by a selective oxidation method in order to separate an element region.
An OS oxide film 23 is formed (FIG. 2A). Next, an n-type impurity such as arsenic (As) or phosphorus (P) is
Energy 5-100 keV, dose 1 × 10 ¹³ -5
Ions are implanted under the condition of × 10 ¹⁴ cm ^-2 to form n ^- source / drain regions 24 in the surface region of the p-well (FIG. 2B).

Next, a silicon oxide film 25 containing no impurities is deposited to a thickness of 50 to 300 nm on the entire surface of the substrate by the CVD method (FIG. 2C). Subsequently, a photoresist film (not shown) having an opening in a channel portion is formed on the silicon oxide film 25 by photolithography, and the surface of the silicon substrate is exposed by RIE (Reactive Ion Etching) using this as a mask. Form an opening.
Next, using the silicon oxide film 25 as a mask, boron (B) is supplied at an energy of 5 to 100 keV and a dose of 1 ×.
Ion implantation is performed under the condition of 10 ¹¹ to 1 × 10 ¹⁴ cm ^-2 ,
Arsenic or phosphorus in the n ⁻ source / drain region 24 previously implanted is compensated to form a channel doped region 26 (FIG. 2D). Here, when the gate electrode to be formed in the future is a metal gate, it is not necessary to completely compensate for the impurities in n ⁻ source / drain region 24.

Next, a gate oxide film 27 having a thickness of 3 to 10 nm is grown on the substrate surface at the channel opening by thermal oxidation. This step of forming the gate oxide film can be performed before performing the channel doping. After that, CV
A tungsten film 28a having a thickness of 50 to 500 nm is formed by the method D (FIG. 3E). Next, a photoresist film (not shown) having a predetermined pattern is formed on the tungsten film 28 by a photolithography method, and the tungsten film 28a and the silicon oxide film 25 are removed by etching using the photoresist film as a mask to form the gate electrode 28. [FIG. 3 (f)]. Next, using the gate electrode 28 and the silicon oxide film 25 as a mask, arsenic (As) or phosphorus (P) is applied at an energy of 20 to 100 keV and a dose of 1 × 10 ¹⁴ to 1 × 10 ^16.
Ions are implanted under the condition of cm ⁻² to form n ⁺ source / drain regions 29 (FIG. 3G). In the above embodiment, the gate electrode is formed using tungsten, but instead of tungsten, molybdenum (Mo) or titanium (Ti) is used.
For example, it may be formed using another high melting point metal.

When tungsten is used for the gate electrode,
The threshold voltage is determined when n-type polysilicon is used (n-channel polysilicon).
+0.65 compared to the case of a channel MOS transistor)
mV, and p-channel MOS transistor
-0.47mV change compared to the case of using polysilicon
Become Therefore, if the gate is polysilicon, n ^- 
The dose for forming the source / drain regions 24 is
1 × 10¹³cm^-2, The channel doping region
The dose for forming 26 is 1 × 10¹³~ 3 × 10
¹³cm^-2Need to be implanted to the extent that conductivity is reversed.
However, in the case of a tungsten gate, the conductivity is inverted.
No need, injection volume is 5 × 10¹²cm^-2Just a little less
Only, the controllability of the threshold value is improved.

[0016]

As described above, the MO according to the present invention is
Since the S transistor does not dig into the silicon substrate in the channel portion, the substantial channel length can be shortened, and the decrease in channel current can be suppressed.
Further, since the substrate is not etched, damage to the channel portion is suppressed, and a decrease in carrier mobility can be suppressed. In addition, variations in channel length are reduced, and variations in characteristics can be reduced. In addition, since channel implantation is performed in a self-aligned manner with the gate electrode, an increase in well concentration other than the channel portion can be prevented, an increase in junction capacitance can be suppressed, and a reverse short channel effect can be suppressed. . Further, since the gate electrode and the source / drain region do not face each other via the thin gate oxide film, the parasitic capacitance can be reduced. In the case where the gate electrode is formed of a high melting point metal, the dose of channel doping can be reduced, and the controllability of the threshold voltage can be improved. Further, since the gate electrode is not depleted, the channel does not have high resistance due to the depletion of the gate electrode, and a high on-state current can be obtained. Therefore, according to the present invention, it is possible to provide a MOS transistor with small variations in characteristics, capable of high-speed operation, and low current consumption.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in the order of steps for describing an embodiment of the present invention.

FIG. 2 is a part of a process order sectional view for explaining one embodiment of the present invention.

FIG. 3 is a step-by-step cross-sectional view in a step that follows the step of FIG. 2 for explaining one embodiment of the present invention.

FIG. 4 is a sectional view of a conventional example in the order of steps.

FIG. 5 is an enlarged cross-sectional view for explaining a problem of the conventional example.

[Explanation of symbols]

11, 21, 31 silicon substrate 12 well region 22, 32 p well 13 element isolation region 23, 33 LOCOS oxide film 14 low concentration source / drain region 24, 34 n ^- source / drain region 15 insulating film 25, 35 silicon oxide film 16, 26 channel doped regions 17, 27, 37, gate oxide films 18, 28, 38 gate electrode 28a tungsten film 19 high concentration source / drain regions 29, 39 n ⁺ source / drain regions

Claims (3)

[Claims] 1. A T-shaped gate electrode is formed on a silicon substrate via a gate oxide film, and an insulating film not doped with impurities is formed between an eaves portion of the gate electrode and the silicon substrate. A MOS transistor, wherein a low-concentration source / drain region is formed in alignment with a leg portion of a gate electrode, and a high-concentration source / drain region is formed in alignment with an eaves portion of the gate electrode. 2. The MOS transistor according to claim 1, wherein said gate electrode is formed of a refractory metal. (3) a step of forming a low-concentration source / drain region by doping a second conductivity type impurity in a surface region of a first conductivity type semiconductor region surrounded by an element isolation region; (3) a step of forming an insulating film over the entire surface; (3) a step of selectively etching away the insulating film to form an opening exposing a surface of a semiconductor region to be a channel region; and (4) a step of forming an opening through the opening. Forming a channel region by doping the semiconductor region with an impurity by using the method described above; (5) forming a gate oxide film on the exposed surface of the semiconductor region by performing thermal oxidation; and (6) forming a gate electrode. Forming a conductor layer for
Patterning the conductor layer and the insulating film thereunder to form a gate electrode; and (7) doping a second conductivity type impurity into a surface region of the semiconductor region using the gate electrode as a mask. Concentration source
Forming a drain region, wherein each step is performed in this order or the order of the (4) th and (5) th steps is reversed. .