JPH10289990A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [PROBLEMS] To reduce the number of steps and increase the density of a nonvolatile memory having a memory cell region and a peripheral circuit region. SOLUTION: A tunnel oxide film 21 and a polycrystalline silicon film 22 serving as a floating gate electrode are deposited on a semiconductor substrate 10 having a memory cell region Rmemo and a peripheral circuit region Rperi. Further, after the pad oxide film 23 and the silicon nitride film 24 are formed, a trench 101 for element isolation is formed, and the trench 101 is formed by filling the trench 101 with the insulating film 31.
Then, after removing unnecessary films, the peripheral circuit region Rperi
Is formed, and the control gate electrode 111 and the floating gate electrode 112 in the memory cell region Rmemo are formed. The trench isolation of each of the regions Rmemo and Rperi can be formed in one step, and the flatness as a whole is improved because there is no underlying step, and the floating gate electrode 112 is formed in a self-alignment with the trench isolation. Densified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a semiconductor device having a nonvolatile memory provided with a floating gate and a control gate.

[0002]

2. Description of the Related Art In recent years, as the price of system equipment has fallen and the product cycle has been shortened, there has been an increasing demand for flash memories in which system developers can freely write and erase programs. Also, with the increase in the capacity of programs and data handled by the system equipment, it is necessary to increase the memory capacity without increasing the occupied area.

Here, conventionally, for example, Japanese Patent Laid-Open No. 2-21
As disclosed in Japanese Unexamined Patent Publication No. 657,657, Japanese Unexamined Patent Publication No. Hei 2-163964 and Japanese Unexamined Patent Publication No. Hei 3-295276, various methods of manufacturing a semiconductor device for reducing the cell area of a flash memory have been proposed.

According to the above conventional method, a semiconductor device is formed, for example, by the following procedure.

First, after forming a LOCOS isolation film in a peripheral circuit region, a tunnel oxide film and a floating gate electrode are selectively formed in a memory cell region. After that, a trench for element isolation is formed in the memory cell region by lithography and etching, and an insulating film is deposited over the entire surface of the substrate and flattened, thereby filling the trench with the insulating film to form a trench isolation. Thereafter, a gate oxide film and a gate electrode film are formed on the entire surface, and a floating gate electrode and a control gate electrode in the memory cell region and a gate electrode in the peripheral circuit region are formed by lithography and etching. That is, by forming a trench isolation in the memory cell region, it is possible to miniaturize the memory cell and to suppress an increase in occupied area due to an increase in memory capacity.

The following method has also been adopted.
After first forming a LOCOS isolation film in the peripheral circuit area,
A tunnel oxide film and a floating gate electrode are selectively formed in a memory cell region. After that, a gate oxide film and a gate electrode film are formed on the entire surface, a trench for element isolation is formed in the memory cell region by lithography and etching, and an insulating film is deposited on the entire surface of the substrate and flattened. The trench is filled with an insulating film to form a trench isolation.
Thereafter, a floating gate electrode and a control gate electrode in the memory cell region and a gate electrode in the peripheral circuit region are formed by lithography and etching. As described above, by forming the element isolation in a self-aligned manner with the floating gate electrode, the cell area is reduced.

[0007]

However, the above-mentioned conventional method has the following problems.

In the former method among the above-mentioned conventional manufacturing methods, the floating gate electrode and the trench isolation cannot be formed in a self-aligned manner as in the latter method, so that the density of the memory cell region cannot be sufficiently increased. .

On the other hand, the latter method is effective for increasing the density of the memory cell region. However, in the planarization process for forming the trench isolation, the LOC of the peripheral circuit region is reduced.
It is difficult to perform planarization so that the OS isolation film is not reduced, and as a result, the flatness of the entire substrate cannot be maintained satisfactorily.

Further, in any of the methods, there is a waste that a process for forming element isolation in the peripheral circuit region and the memory cell region is individually required.

The present invention has been made in view of the above circumstances, and an object of the present invention is to form a trench isolation not only in a memory cell region but also in a peripheral circuit region as a method of manufacturing a semiconductor device having a nonvolatile memory cell. By doing
It is an object of the present invention to maintain the flatness of the entire semiconductor device and to increase the density of the entire semiconductor device while reducing the number of steps.

[0012]

In order to achieve the above object, the present invention provides means for manufacturing a semiconductor device according to the present invention.

According to a first method of manufacturing a semiconductor device of the present invention,
A nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film and a control gate electrode is disposed in a memory cell region of a semiconductor substrate, while the gate insulating film and the gate electrode are arranged as described in claim 1. A method for manufacturing a semiconductor device, comprising arranging a field-effect transistor having a structure in a peripheral circuit region of a semiconductor substrate, comprising: forming a tunnel insulating film and a first conductor film over a memory cell region and a peripheral circuit region of the semiconductor substrate. A first step of forming the first conductive film, the tunnel insulating film, and the semiconductor substrate by using a first mask member having an opening in the trench isolation formation region to selectively remove the element isolation trench. A second step of forming, a third step of forming a trench isolation by filling the trench with an insulating film, and forming the first conductive film and the tunnel in the peripheral circuit region. A fourth step of removing the insulating film, a fifth step of forming a gate insulating film and a second conductive film over the entire surface of the substrate, and a step of forming the first conductive film, the gate insulating film, and the second conductive film. Patterning the conductive film to form a floating gate electrode and a control gate electrode in the memory cell region, and forming a gate electrode in the peripheral circuit region;
Steps.

In the semiconductor device formed by this method, the transistors are isolated not only in the memory cell region but also in the peripheral circuit region by trench isolation which can exhibit a high isolation function at a smaller interval than the LOCOS isolation film. Thus, the density of the entire semiconductor device can be increased. In addition, in the flattening step when forming the trench isolation, it is not necessary to consider the reduction in the LOCOS film, so that the entire substrate can be flattened with high accuracy.
Moreover, since the floating gate electrode is formed in a self-aligned manner with respect to the trench isolation, a margin for mask alignment is not required, and the density in the memory cell region can be increased.

According to a second aspect of the present invention, in the first aspect, in the sixth step, etching is performed using a second mask member that covers the memory cell region and the gate electrode formation region in the peripheral circuit region. To selectively remove the second conductor film to form a gate electrode in the peripheral circuit region; and, after removing the second mask member, form a gate electrode formation region in the peripheral circuit region and the memory cell region. And the third covering
Forming a floating gate electrode and a control gate electrode in the memory cell region by selectively removing the second conductive film, the gate insulating film, and the first conductive film sequentially by performing etching using the mask member of (1). Can be included.

According to this method, since the control gate electrode and the floating gate electrode in the memory cell region are formed using the same third mask member, a margin for masking the two is not required, and the memory cell region is not required. The density will be further increased.

According to a third aspect of the present invention, in the first aspect, the sixth step includes a step of forming an electrode protection film on the second conductor film, and a step of forming a memory cell region and a peripheral circuit. Etching is performed using a second mask member that covers the gate formation region of the region, and the electrode protection film and the second conductor film are selectively removed to form a control gate electrode in the memory cell region and a gate electrode in the peripheral circuit region. Forming, and after removing the second mask member, etching using the third mask member covering the peripheral circuit region and opening the entire memory cell region and the remaining portion of the electrode protection film as a mask And forming a control gate electrode in the memory cell region by sequentially and selectively removing the gate insulating film and the first conductor film.

According to this method, the floating gate electrode in the memory cell region is formed by using the same second mask member as the control gate electrode. The density of the memory cell area is further increased.

According to a second method of manufacturing a semiconductor device of the present invention,
The nonvolatile memory cell having the tunnel insulating film, the floating gate electrode, the gate insulating film and the control gate electrode is arranged in the memory cell region, while the electric field having the gate insulating film and the gate electrode is provided. A method of manufacturing a semiconductor device in which an effect transistor is arranged in a peripheral circuit region, comprising: a first step of forming a tunnel insulating film and a first conductor film over a memory cell region and a peripheral circuit region of a semiconductor substrate. And a second step of selectively removing the first conductor film, the tunnel insulating film, and the semiconductor substrate by using a first mask member having an opening in a trench isolation formation region to form an element isolation trench. A third step of forming a trench isolation by filling the trench with an insulating film; and opening a peripheral circuit region and covering a floating gate electrode formation region of a memory cell region. A fourth step of performing etching using the second mask member to selectively remove the first conductor film and the tunnel insulating film sequentially to form a floating gate electrode in the memory cell region; and After removing
A fifth step of forming a gate insulating film and a second conductive film over the entire surface of the substrate, and patterning the second conductive film to extend over the floating gate electrode and the semiconductor substrate via the gate insulating film A sixth step of forming a control gate electrode in the region and a gate electrode in the peripheral circuit region.

According to this method, the same effect as that of the first aspect can be obtained for a semiconductor device having a nonvolatile memory cell capable of injecting charges into the floating gate electrode using channel hot electrons.

According to a fifth aspect, in any one of the first to third aspects, the fifth step includes:
After forming a first gate insulating film on the entire surface of the substrate, at least a part of the thickness of the first gate insulating film in the peripheral circuit region is selectively removed, and then the first gate insulating film is formed on the entire surface of the substrate. After forming the second gate insulating film, the second conductor film can be formed.

According to this method, the gate insulating film between the floating gate electrode and the control gate electrode in the memory cell region is composed of the first and second gate insulating films, and the gate insulating film in the peripheral circuit region is the second gate insulating film. Since the gate insulating film is composed of only the film or the second gate insulating film and a part of the first gate insulating film, it is easy to make the thicknesses of the gate insulating films in the memory cell region and the peripheral circuit region different from each other. Therefore, it is possible to form a gate insulating film having an appropriate thickness different between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit.

According to a sixth aspect, in any one of the first to fifth aspects, after the first step and before the second step, the upper surface of the first conductor film is formed. Preferably, an etching stopper film is formed first.

According to this method, the flattening can be surely performed.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, a method of manufacturing a semiconductor device according to a first embodiment will be described. 1A to 1G are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the present embodiment.

First, in the step shown in FIG. 1A, the entire surface of the semiconductor substrate 10 having the memory cell region Rmemo and the peripheral circuit region Rperi is oxidized to form a tunnel oxide film 21 having a thickness of about 10 nm, A polycrystalline silicon film 22 having a thickness of about 200 nm is deposited as a film. Further, on the polycrystalline silicon film 22, the polycrystalline silicon film is oxidized or C
Depending on whether VD is performed, a pad oxide film 23 having a thickness of about 10 nm is formed, and a silicon nitride film 24 having a thickness of about 150 nm is further formed.

Next, in the step shown in FIG. 1B, a resist film 51 having an opening in a region where element isolation is to be formed on the substrate is formed.
Is formed, silicon nitride film 24, pad oxide film 2
3. The polycrystalline silicon film 22, the tunnel oxide film 21, and the substrate 10 are sequentially etched to form a substrate with a depth of about 300 nm.
A groove 101 for element isolation is formed.

Next, in the step shown in FIG.
1 is removed, an insulating film 31 having a thickness of about 700 nm is deposited on the entire surface of the substrate, and then the upper surface of the substrate is planarized by performing CMP using the silicon nitride film 24 as a stopper film, thereby forming the groove 101. The trench isolation is formed by filling with an insulating film 31.

Next, in the step shown in FIG. 1D, after the silicon nitride film 24 and the pad oxide film 23 are all removed, a resist film 52 covering the memory cell region Rmemo is formed, and the polycrystalline silicon film in the peripheral circuit region Rperi is formed. 22 and the tunnel oxide film 21 are removed by etching.

Next, in the step shown in FIG. 1E, the thickness of at least the peripheral circuit region Rperi is about 1
A gate insulating film 25 having a thickness of 0 nm and a polycrystalline silicon film 26 having a thickness of about 200 nm as a second conductor film are sequentially deposited.

Thereafter, formation of the gate electrode is performed in the following two steps.

First, in a step shown in FIG. 1F, after forming a resist film 53 covering the memory cell region Rmemo and a region where the gate electrode of the peripheral circuit region Rperi is to be formed, etching is performed using the resist film 53 as a mask. To selectively remove the polycrystalline silicon film 26 in the peripheral circuit region Rperi to remove the gate electrode 110 in the peripheral circuit region Rperi.
To form

Next, in the step shown in FIG. 1g, after forming a resist film 54 covering the peripheral circuit region Rperi and a region where the control gate electrode of the memory cell region Rmemo is to be formed, this resist film 54 is masked. Then, the polycrystalline silicon film 26, the gate insulating film 25 and the polycrystalline silicon film 22 in the memory cell region Rmemo are sequentially etched to form the control gate electrode 111 and the floating gate electrode 112 in the memory cell region Rmemo.

Although illustration of subsequent steps is omitted, formation of an interlayer insulating film, formation of a contact hole, formation of a wiring layer, and the like are performed to complete a semiconductor device on which a flash memory is mounted.

According to the present embodiment, as shown in FIG. 1B, the memory cell region R
Since trench isolation can be formed in both the memo and the peripheral circuit region Rperi, the number of steps can be reduced.

The groove 101 in the step shown in FIG.
Even when the buried insulating film is planarized, there is no underlying step between the memory cell region Rmemo and the peripheral circuit region Rperi, so that the insulating film can be planarized very easily, and the flatness of the substrate is maintained in the subsequent steps. The processing can be performed while doing so. Further, unlike the case where the LOCOS isolation film is formed in the peripheral circuit region Rperi, there is no possibility that the element isolation function is deteriorated due to the decrease in the LOCOS isolation film.
CMP or the like for flattening can be performed without limitation, and flatness is particularly improved.

Further, the isolation trench 101 is formed in a self-aligned manner with the floating gate electrode 112. Figures 2a, 2b
FIG. 3A is a plan view showing the control gate electrode 111 removed in the step shown in FIG. 1G and a cross-sectional view taken along a line orthogonal to the gate length direction (a cross-section taken along line IIb-IIb). In other words, when forming the floating gate electrode after forming the trench isolation, it is necessary to separate the floating gate electrode between the cells. Therefore, a mask for forming the floating gate electrode and a mask for forming the trench isolation are required. Requires a margin in consideration of the positional deviation. On the other hand, in the present embodiment, the floating gate electrode 112 is formed by trench isolation (insulating film 31).
Are separated from each other, so that a margin for such mask alignment is not required, so that the density of the memory cell region Rmemo can be increased. In the manufacturing process of the present embodiment, since the floating gate electrode 112 and the control gate electrode 111 are formed using the same resist film 54 as a mask, compared with the case where both are formed separately,
A margin for mask alignment is not required, and higher density can be achieved.

Therefore, in this embodiment, it is possible to improve the flatness and increase the density of the entire semiconductor device while reducing the number of steps.

In this embodiment, when forming each gate electrode, first, the gate electrode 110 of the peripheral circuit region Rperi is formed.
After the formation of the control gate electrode 111 and the floating gate electrode 112 in the memory cell region Rmemo, the control gate electrode 111 and the floating gate electrode 112 in the memory cell region Rmemo are formed first, and then the peripheral circuit region Rpe
An ri gate electrode 110 may be formed.

(Second Embodiment) Next, a method of manufacturing a semiconductor device according to a second embodiment will be described. FIG.
FIGS. 7A to 7G are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the second embodiment.

First, in the step shown in FIG. 3A, the entire surface of the semiconductor substrate 10 having the memory cell region Rmemo and the peripheral circuit region Rperi is oxidized to form a tunnel oxide film 21 having a thickness of about 10 nm, and the first conductor A polycrystalline silicon film 22 having a thickness of about 200 nm is deposited as a film. Further, a pad oxide film 23 having a thickness of about 10 nm is formed on the polycrystalline silicon film 22 by oxidizing the polycrystalline silicon film or performing CVD, and a silicon nitride film 24 having a thickness of about 150 nm is further formed. .

Next, in a step shown in FIG. 3B, a resist film 51 having an opening in a region where element isolation is to be formed on the substrate.
Is formed, silicon nitride film 24, pad oxide film 2
3. The polycrystalline silicon film 22, the tunnel oxide film 21, and the substrate 10 are sequentially etched to form a substrate with a depth of about 300 nm.
A groove 101 for element isolation is formed.

Next, in the step shown in FIG.
1 is removed, an insulating film 31 having a thickness of about 700 nm is deposited on the entire surface of the substrate, and then the upper surface of the substrate is planarized by performing CMP using the silicon nitride film 24 as a stopper film, thereby forming the groove 101. The trench isolation is formed by filling with an insulating film 31.

Next, in the step shown in FIG. 3D, after the silicon nitride film 24 and the pad oxide film 23 are all removed, a resist film 52 covering the memory cell region Rmemo is formed, and the polycrystalline silicon film in the peripheral circuit region Rperi is formed. 22 and the tunnel oxide film 21 are removed by etching.

Next, in the step shown in FIG. 3E, the thickness of at least the peripheral circuit region Rperi is reduced to about 1 on the entire surface of the substrate.
A gate insulating film 25 having a thickness of 0 nm and a polycrystalline silicon film 26 having a thickness of about 200 nm as a second conductor film are sequentially deposited. Furthermore, a thickness of about 1
A 00 nm cap oxide film 27 is deposited.

Next, in the step shown in FIG. 3F, a resist film 55 is formed to cover the region where the control gate electrode is to be formed in the memory cell region Rmemo and the region where the gate conductor film is to be formed in the peripheral circuit region Rperi. Then, etching is performed using the resist film 55 as a mask, and the cap oxide film 27 and the polycrystalline silicon film 26 are selectively removed to form the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 110 in the peripheral circuit region Rperi. I do.

Next, in a step shown in FIG. 3G, a resist film 56 covering the peripheral circuit region Rperi and exposing the entire memory cell region Rmemo is formed, and etching is performed using the resist film 56 and the cap oxide film 27 as a mask. Do
The gate insulating film 25 and the polycrystalline silicon film 22 in the memory cell region Rmemo are sequentially and selectively removed to form the floating gate electrode 112 in the memory cell region Rmemo.

Although illustration of subsequent steps is omitted, formation of an interlayer insulating film, formation of a contact hole, formation of a wiring layer, and the like are performed to complete a semiconductor device on which a flash memory is mounted.

According to the present embodiment, as in the first embodiment, it is possible to improve the flatness of the entire semiconductor device and increase the density while reducing the number of steps.

In addition, in the present embodiment, in the step shown in FIG.
And the gate electrode 110 of the peripheral circuit region Rperi are formed at the same time, so that there is no need to take a margin for extra mask alignment at the boundary region between the memory cell region Rmemo and the peripheral circuit region Rperi. The density can be further increased by the amount.

(Third Embodiment) Next, a method of manufacturing a semiconductor device according to a third embodiment will be described. FIG. 4a
1 to f are cross-sectional views illustrating the steps of manufacturing the semiconductor device according to the present embodiment.

First, in the step shown in FIG. 4A, the entire surface of the semiconductor substrate 10 having the memory cell region Rmemo and the peripheral circuit region Rperi is oxidized to form a tunnel oxide film 21 having a thickness of about 10 nm, and the first conductor A polycrystalline silicon film 22 having a thickness of about 200 nm is deposited as a film. Further, on the polycrystalline silicon film 22, the polycrystalline silicon film is oxidized or C
Depending on whether VD is performed, a pad oxide film 23 having a thickness of about 10 nm is formed, and a silicon nitride film 24 having a thickness of about 150 nm is further formed.

Next, in the step shown in FIG. 4B, a resist film 51 having an opening on a substrate where an element isolation is to be formed is formed.
Is formed, silicon nitride film 24, pad oxide film 2
3. The polycrystalline silicon film 22, the tunnel oxide film 21, and the substrate 10 are sequentially etched to form a substrate with a depth of about 300 nm.
A groove 101 for element isolation is formed.

Next, in the step shown in FIG.
1 is removed, an insulating film 31 having a thickness of about 700 nm is deposited on the entire surface of the substrate, and then the upper surface of the substrate is planarized by performing CMP using the silicon nitride film 24 as a stopper film, thereby forming the groove 101. The trench isolation is formed by filling with an insulating film 31.

Next, in the step shown in FIG. 4D, after the silicon nitride film 24 and the pad oxide film 23 are all removed, the peripheral circuit region Rperi is exposed and the region where the floating gate electrode is to be formed in the memory cell region Rmemo. Is formed using the resist film 57 as a mask, and the polycrystalline silicon film 22 and the tunnel oxide film 21 are selectively removed to make the floating gate electrode 112 in the memory cell region Rmemo first. Form.

Next, in a step shown in FIG. 4E, the thickness of at least the peripheral circuit region Rperi is reduced to about 1 on the entire surface of the substrate.
A gate insulating film 25 having a thickness of 0 nm and a polycrystalline silicon film 26 having a thickness of about 200 nm as a second conductor film are sequentially deposited.

Next, in a step shown in FIG. 4F, a resist film 55 is formed to cover the region where the control gate electrode is to be formed in the memory cell region Rmemo and the region where the gate electrode is to be formed in the peripheral circuit region Rperi. , This resist film 5
5 is used as a mask to selectively remove the polycrystalline silicon film 26 to form the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 110 in the peripheral circuit region Rperi. At this time, the memory cell area Rmemo
Of the control gate electrode 111 is on the upper surface of the floating gate electrode 112, while the other is
Over the semiconductor substrate 10.

Although illustration of subsequent steps is omitted, formation of an interlayer insulating film, formation of a contact hole, formation of a wiring layer, and the like are performed to complete a semiconductor device on which a flash memory is mounted.

According to the present embodiment, as in the first and second embodiments, it is possible to improve the flatness of the entire semiconductor device and increase the density while reducing the number of steps.

Further, in the present embodiment, similarly to the second embodiment, in the step shown in FIG.
And the gate electrode 110 of the peripheral circuit region Rperi are formed at the same time, so that a margin for extra mask alignment in the boundary region between the memory cell region Rmemo and the peripheral circuit region Rperi is taken. It is not necessary, and the density can be further increased.

Further, in this embodiment, the control gate electrode 111 extending from the floating gate electrode 112 to the semiconductor substrate 10
Is formed, it is possible to inject charges into the floating gate electrode 112 using channel hot electrons, and it is possible to reliably prevent the adverse effect of heat generation due to high density of the semiconductor device by lowering the voltage of the flash memory. There is.

In the first, second and third embodiments, the steps of implanting ions and heat treatment for forming transistors and wells have been omitted, but it is needless to say that these steps can be performed by a known technique. Absent.

(Other Embodiments and Modifications) In the first to third embodiments, CMP is used to planarize the buried insulating film 31 in the element isolation trench 101, but the resist etch back method or the spin etching is used. Method may be used. In this case, the pad oxide film 23 and the silicon nitride film 24 do not need to be used as long as the polycrystalline silicon film 22 has a selection ratio enough to function as an etching stopper film.

The gate insulating film 25 in the first to third embodiments functions as a gate insulating film of the transistor in the peripheral circuit region Rperi and a gate insulating film between the floating gate and the control gate in the memory cell region Rmemo. They have a common thickness. However, since conditions such as applied voltage are different between the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 110 in the peripheral circuit region Rperi, both can be formed to have different film thicknesses.
In that case, the following steps can be performed.

First, in the steps shown in FIGS. 1E, 3E, and 4E, a gate insulating film 25 (first gate insulating film) is formed by deposition by an oxidation method or a CVD method, and then a resist covering the memory cell region Rmemo is formed. A film is formed, and the thickness of the gate insulating film 25 in the peripheral circuit region Rperi is reduced or the entire thickness is removed. Thereafter, a second gate insulating film is formed over the entire surface by oxidation or CVD, and then a polycrystalline silicon film 26 may be deposited as a second electrode. Through these steps, gate insulating films having different thicknesses can be formed in the peripheral circuit region Rperi and the memory cell region Rmemo. However, FIGS. 1e, 3e,
In the step shown in FIG. 4E, when the gate insulating film 25 is formed by an oxidation method, the oxidation progresses faster in polycrystalline silicon than in single crystal silicon. Circuit area R
Generally, the thickness of the gate insulating film 25 is considerably larger than that of the gate insulating film 25 in the peri. Therefore, it is possible to increase only the thickness of the gate insulating film in the memory cell region Rmemo without necessarily performing the above steps.

Further, the gate insulating film on the thick side is formed not only in the memory cell region Rmemo but also in the peripheral circuit region Rpe.
It may be used for a transistor for high withstand voltage or input / output at ri.

In each of the above embodiments, a polycrystalline silicon film is used as the second conductor film. However, a laminated film (such as a polycide film) of a polycrystalline silicon film and a metal or a metal compound may be used.

[0068]

According to the present invention, a method of manufacturing a semiconductor device in which a nonvolatile memory cell is arranged in a memory cell region and a field effect transistor is arranged in a peripheral circuit region of a semiconductor substrate is provided. And the peripheral circuit region are formed with trench isolation in the same process, and the floating gate electrode and the trench isolation in the memory cell region are self-aligned, so that the semiconductor is highly dense and has good flatness as a whole. A method for manufacturing a semiconductor device for forming a device in a small number of steps can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is a plan view for explaining the structure of a floating gate electrode of the semiconductor device according to the first embodiment and a cross-sectional view taken along line IIb-IIb.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment.

FIG. 4 is a sectional view illustrating a manufacturing process of a semiconductor device according to a third embodiment.

[Explanation of symbols]

 Reference Signs List 10 semiconductor substrate 21 tunnel insulating film 22 polycrystalline silicon film (first conductive film) 23 pad oxide film 24 silicon nitride film 25 gate insulating film 26 polycrystalline silicon film (second conductive film) 27 cap insulating film (electrode protection) 31) Insulating film (trench isolation) 51-57 Resist film 101 Element isolation groove 110 Gate electrode 111 Control gate electrode 112 Floating gate electrode

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/792 (72) Inventor Takaaki Ueda 1006 Ojidoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Arai Masato 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Masaru Moriwaki 1006 Kadoma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (6)

[Claims] A nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film and a control gate electrode is arranged in a memory cell region of a semiconductor substrate.
A method of manufacturing a semiconductor device in which a field effect transistor having a gate insulating film and a gate electrode is arranged in a peripheral circuit region of a semiconductor substrate, comprising: a tunnel insulating film extending over a memory cell region and a peripheral circuit region of the semiconductor substrate; A first step of forming a first conductor film, and selectively removing the first conductor film, the tunnel insulating film, and the semiconductor substrate by using a first mask member having an opening in a trench isolation formation region. A second step of forming a trench for element isolation, a third step of forming a trench isolation by filling the groove with an insulating film, and a step of forming the first conductive film and the tunnel insulating film in the peripheral circuit region. A fourth step of removing, a fifth step of forming a gate insulating film and a second conductive film over the entire surface of the substrate, and a step of removing the first conductive film, the gate insulating film, and the second conductive film. Paternin To, while forming a floating gate electrode and control gate electrode in the memory cell region, a method of manufacturing a semiconductor device characterized by and a sixth step of forming a gate electrode in the peripheral circuit region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the sixth step, etching is performed using a second mask member covering a memory cell region and a gate electrode formation region in a peripheral circuit region. ,
Forming a gate electrode in the peripheral circuit region by selectively removing the second conductor film; and covering the peripheral circuit region and the gate electrode formation region in the memory cell region after removing the second mask member. Forming a floating gate electrode and a control gate electrode in a memory cell region by selectively removing the second conductor film, the gate insulating film, and the first conductor film by performing etching using a third mask member; And a method of manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said sixth step includes a step of forming an electrode protection film on said second conductor film, and a step of forming a memory cell region and a peripheral circuit region. Etching is performed using a second mask member that covers the gate formation region, and the electrode protection film and the second conductor film are selectively removed to form a control gate electrode in the memory cell region and a gate electrode in the peripheral circuit region. After removing the second mask member, etching is performed using the third mask member covering the peripheral circuit region and opening the entire memory cell region and the remaining portion of the electrode protection film as a mask. Forming a control gate electrode in the memory cell region by sequentially and selectively removing the gate insulating film and the first conductor film. 4. A nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film and a control gate electrode is arranged in a memory cell region, and a field effect transistor having a gate insulating film and a gate electrode is arranged in a peripheral circuit. A method of manufacturing a semiconductor device, wherein a first step of forming a tunnel insulating film and a first conductor film over a memory cell region and a peripheral circuit region of a semiconductor substrate; A second step of selectively removing the first conductive film, the tunnel insulating film, and the semiconductor substrate by using the opened first mask member to form a trench for element isolation; A third step of forming a trench isolation by burying the second mask member, and a second mask member that opens the peripheral circuit region and covers the floating gate electrode formation region of the memory cell region. A fourth step of selectively removing the first conductor film and the tunnel insulating film in order to form a floating gate electrode in the memory cell region, and removing the second mask member. Forming a gate insulating film and a second conductive film on the entire surface of the semiconductor device; and patterning the second conductive film to form a memory cell region extending over the floating gate electrode and the semiconductor substrate via the gate insulating film. And a sixth step of forming a control gate electrode and a gate electrode in a peripheral circuit region. 5. The method for manufacturing a semiconductor device according to claim 1, wherein in the fifth step, after forming a first gate insulating film over the entire surface of the substrate, the method further comprises: After selectively removing at least a part of the thickness of the first gate insulating film in the circuit region, and then forming a second gate insulating film over the entire surface of the substrate, forming the second conductive film A method of manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 1, wherein said first conductive film is formed on said first conductive film after said first process and before said second process. And a method of manufacturing a semiconductor device, wherein an etching stopper film is formed.