JPH10290010A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: Provided is a vertical insulated gate field effect transistor made of silicon carbide, which has a highly reliable gate insulating film and a method for manufacturing the same. SOLUTION: A p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4
An n ⁺ -type source region 5 is formed in a predetermined region in the surface layer portion. A low-resistance p-type silicon carbide region 6 is formed in a predetermined region in a surface portion of p-type silicon carbide semiconductor layer 3. n ⁺ -type grooves 7 in a predetermined region of the source region 5 is formed, the groove 7 extends through the n ⁺ -type source region 5 and the p-type silicon carbide semiconductor layer 3 n ^- has reached the -type silicon carbide semiconductor layer 2 . The groove 7 has a side surface 7 a perpendicular to the surface of the semiconductor substrate 4 and a bottom surface 7 b parallel to the surface of the semiconductor substrate 4. Groove 7
The hexagonal region surrounded by the side surface 7a of FIG. A highly reliable gate insulating film 8 is obtained by forming a gate insulating film on the side surface 7a surrounding the island-shaped semiconductor region 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device, for example, a high power vertical insulated gate field effect transistor.

[0002]

2. Description of the Related Art In recent years, a vertical power MOSFE manufactured using a silicon carbide single crystal material as a power transistor.
T has been proposed. In this method, a groove is formed in a semiconductor substrate from the substrate surface, and the side surface of the groove is used as a channel region.
In a power transistor, it is necessary that the leak current between the source and the drain when the gate voltage is off is small and the resistance between the source and the drain when the gate voltage is on (hereinafter referred to as on-resistance) is small. On the other hand, as a power transistor that can effectively reduce the leak current and the on-resistance when a high voltage is applied by taking advantage of the electronic properties of hexagonal silicon carbide, see, for example,
Japanese Patent Application Laid-Open No. 31016 and Japanese Patent Application Laid-Open No. 7-326755 have been proposed.

[0003]

However, in the trench gate type power MOSFETs disclosed in JP-A-7-131016 and JP-A-7-326755, the channel mobility is not necessarily improved, and the on-resistance still remains. There was a problem of high. Further, there is a problem that the life of the gate insulating film is shorter than that of the silicon MOSFET.

An object of the present invention is to provide a transistor having a highly reliable gate insulating film in a vertical insulated gate field effect transistor made of silicon carbide and a method of manufacturing the same. An object of the present invention is to provide a transistor capable of improving the degree of resistance and effectively reducing the on-resistance, and a method for manufacturing the same.

[0005]

According to a first aspect of the present invention, there is provided an island-shaped semiconductor region which is surrounded by a side surface of a groove of a vertical insulated gate field effect transistor and serves as a channel portion. The gist is a silicon carbide semiconductor device in which a gate insulating film is formed on a groove side surface surrounding the island-shaped semiconductor region. That is, the island-shaped semiconductor region is surrounded by the gate insulating film.

According to a second aspect of the present invention, the planar shape of the island-shaped semiconductor region in the first aspect of the present invention is a polygon, and the interior angles of any of the polygons are less than 180 degrees. Make a summary. Claim 3 or Claim 6
The invention described in the above, the sides of the polygon, that is, the groove side surface,
The gist is that the gate insulating film is substantially parallel to the [11-00] direction and the gate insulating film is an insulating film formed by thermal oxidation in a wet atmosphere.

The gist of the invention described in claim 4 is that the polygon in the invention of claim 3 is a hexagon whose interior angles are substantially equal. Hereinafter, the present invention will be described in more detail based on experiments performed by the present inventors and considerations based on the results. First, with respect to the problem of obtaining a highly reliable gate insulating film, if the interface state density derived from carbon atoms can be reduced, a highly reliable gate insulating film can be obtained. We thought that life could be extended.

The inventors of the present invention have proposed a vertical insulated gate field effect transistor composed of a silicon carbide single crystal substrate having an MO having a triangular, quadrangular, hexagonal, circular or other surface shape on the groove side surface.
An SFET was designed, and one having a groove formed inside and one having a groove formed outside the SFET were manufactured and evaluated. As a result, it was found that the life of the gate insulating film was relatively longer when the groove was formed outside.

The reason for this will be described with reference to FIGS. FIGS. 14A and 15A are plan views of a vertical insulated gate field effect power MOSFET made of silicon carbide, in which a source region is formed on the surface and a channel region is formed on a side surface thereof. The p-type silicon carbide semiconductor layer 3 (the island-shaped semiconductor region 12 in FIG. 15), the trench 7 and the gate insulating film 8 are illustrated. FIGS. 14B and 15B are partially enlarged views of FIGS. 14A and 15A, respectively. In FIG. 14, a square groove 7 is formed in the p-type silicon carbide semiconductor layer 3, and in FIG. 15, the island-shaped semiconductor region 12 is formed by forming the groove 7. That is, the one shown in FIG. 14 corresponds to one having a groove formed inside, and the one shown in FIG. 15 corresponds to one having a groove formed outside.

FIG. 14 is a partially enlarged view of FIG.
In the case where a groove is formed inside as shown in (b), the diffusion of carbon atoms generated by thermal oxidation at the time of forming the gate insulating film is reduced in the oxide film at the corner A where the channel surface intersects. There is a region where the density of carbon atoms is high, and the interface state density originating from carbon atoms becomes extremely large at the corner where the channel surface intersects, so the reliability of the gate insulating film is reduced. Concluded that

On the other hand, as shown in FIG. 15 (b), which is a partially enlarged view of FIG. 15 (a), in the case where a groove is formed on the outside, the inside of the oxide film at the corner where the channel surface intersects the channel surface. Thus, diffusion of carbon atoms generated by thermal oxidation during formation of the gate insulating film is not suppressed, and there is no region where the density of carbon atoms is particularly large. Therefore, it was concluded that the reliability of the gate insulating film did not decrease due to the concentration of carbon atoms generated by thermal oxidation.

The reason why the diffusion of carbon atoms generated by thermal oxidation during the formation of the gate insulating film differs between the case where the groove is formed inside and the case where the groove is formed outside is as follows.
14 (b), the path through which carbon atoms diffuse during thermal oxidation indicated by arrows in FIG. 15 (b) is densely formed especially at the corners in the case where a groove is formed inside FIG. 14 (b). On the other hand, in the case where the groove is formed outside of FIG. 15B, it is considered that the path does not become dense. That is, when a groove is formed on the inside, a region serving as a recess is formed, and carbon atoms are not easily diffused during thermal oxidation. On the other hand, when a groove is formed on the outside, a region serving as a recess is formed. However, it can be said that carbon atoms are easily diffused during thermal oxidation.

As described above, the reliability of the gate insulating film can be improved by forming the groove outside. In addition, for the problem that the channel mobility is still low, the present inventors depend on the surface shape dependence of the side surface of the transistor groove, the crystal plane orientation dependence of the channel surface, and the conditions for forming the gate insulating film on the electrical characteristics of the transistor. The dependence was examined and tested.

MOSFE having a main surface of a (0001-) carbon surface and a channel direction of a vertical insulated gate field effect transistor, that is, a MOSFE having a groove side surface changed by 5 degrees.
T was fabricated and the channel mobility was evaluated. As a result, the MO in which the gate insulating film is formed by thermal oxidation in a wet atmosphere is formed.
In the SFET, the channel mobility shows a periodicity of 60 degrees,
When the plane orientation of the channel plane was parallel to [11-00], the channel mobility showed a maximum. In addition, when the interface state density was estimated, it was found to be minimal when it was parallel to [11-00]. FIG. 16 shows the plane orientation dependency of the interface state density obtained from the evaluation of the present inventors. Here, a MOSFE in which a gate insulating film is formed by thermal oxidation in a dry atmosphere.
At T, the channel mobility was lower than that of the MOSFET formed in the wet atmosphere, the interface state density was large, and no strong plane orientation dependence was exhibited.

This result is one of the causes of the decrease in channel mobility.
First, the interface state density resulting from the crystal structure of the hexagonal silicon carbide semiconductor is important. The present inventors consider that MOSF formed of a silicon carbide semiconductor
The origin of the interface state density of ET is different from the case of a silicon semiconductor composed of a single atom, in which carbon atoms existing on the channel surface play an important role, and are one more than those of a MOSFET formed from a silicon semiconductor. It was concluded that the interface state density, which is greater than an order of magnitude, was attributed to carbon atoms. The reason is that the hexagonal silicon carbide has a higher interface state density on the (0001-) carbon surface than on the (0001) silicon surface, and the distribution of the interface state density in FIG. This is because there was a good correlation with the carbon atom density per unit area calculated mathematically from

Therefore, the density of the carbon atoms existing in the channel surface and the gate oxide film is reduced to the maximum, and the interface state density originating from the carbon atoms is reduced to reduce the density of the MOSFET formed of silicon carbide. We thought that channel mobility could be improved. It has been confirmed by experiments of the present inventors that it is effective to make the channel surface parallel to [11-00] and to form the gate insulating film by thermal oxidation in a wet atmosphere. Also in the case of forming a groove on the outside shown in FIG. 15, since there is no dense region where carbon atoms are left in the gate insulating film as described above, the interface state density caused by carbon atoms is reduced. It can be said that it is possible to improve the channel mobility by lowering it.

Therefore, according to the first or fifth aspect of the present invention, an island-shaped semiconductor region which is surrounded by the side surface of the groove of the vertical insulated gate field effect transistor and serves as a channel portion is formed. In other words, since the groove is formed on the outside and the gate insulating film is formed on the side surface of the groove of the island-shaped semiconductor region, when forming the groove on the inside when forming the gate insulating film by thermal oxidation, In comparison, carbon atoms generated by the oxidation of silicon carbide can be easily diffused into the atmosphere, thereby eliminating an increase in interface state density due to non-diffusion of carbon atoms, improving channel mobility and improving gate oxide film. The life can be improved.

According to the invention of claim 2, according to claim 1,
In addition to the effect of the invention described in (1), since the island-shaped semiconductor region is polygonal, it is possible to easily design a planar shape.
In addition, since the interior angles of any of the polygons are less than 180 degrees, it is possible to eliminate an increase in interface state density due to non-diffusion of carbon atoms. Claim 3 or Claim 6
According to the invention described in (1), since the sides of the polygon, that is, the groove side surfaces are substantially parallel to the [11-00] direction, the MOS interface is formed on the plane where the carbon atom density based on the silicon carbide crystal structure is minimized. As a result, the interface state density can be effectively reduced as shown by the experimental results of the present inventors.

According to the invention described in claim 4, according to claim 3,
In addition to the effect of the invention described in (1), since the planar shape of the side surface is a hexagon having substantially the same interior angle, the angle forming the interior angle on each side of the hexagon is approximately 120 degrees. Therefore, when a high voltage is applied between the source and the drain when the vertical insulated gate field effect transistor is turned off, avalanche breakdown due to electric field concentration occurs in the semiconductor portion formed by the hexagonal groove on the side surface. Less likely to occur. That is, in order to align the sides of the polygon in a predetermined direction as described in claim 3, there may be a triangle or a rhombus, but in such a shape, an acute angle portion is generated, and avalanche breakdown easily occurs due to electric field concentration. However, an avalanche breakdown is unlikely to occur in a hexagon since there is no region where the angle becomes acute. Therefore, in the source-drain breakdown voltage design, the breakdown voltage determined by the impurity concentration and the film thickness of the high-resistance semiconductor layer and the second conductivity type semiconductor layer may be considered.
High breakdown voltage design becomes possible.

In the present specification, when the plane and the direction axis of the hexagonal single-crystal silicon carbide are expressed, a bar is added to a required numeral as originally described in the drawings. Although the expression should be taken, due to the restriction of the expression means, instead of the expression in which a bar is added above the required number, the required number is represented by adding "-" after the required number.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an n-channel type vertical insulated gate field effect transistor (hereinafter referred to as a vertical power MOSFET) in this embodiment. Hexagonal silicon carbide is used for n ⁺ -type silicon carbide semiconductor substrate 1 as a low-resistance semiconductor layer. On this n ⁺ -type silicon carbide semiconductor substrate 1, an n ⁻ -type silicon carbide semiconductor layer 2 and a p-type silicon carbide semiconductor layer 3 as high-resistance semiconductor layers are sequentially laminated.

Thus, n ⁺ type silicon carbide semiconductor substrate 1
And n ⁻ -type silicon carbide semiconductor layer 2 and p-type silicon carbide semiconductor layer 3
Thus, a semiconductor substrate 4 made of single-crystal silicon carbide is formed, and its upper surface is substantially a (0001-) carbon surface. An n ⁺ -type source region 5 as a semiconductor region is formed in a predetermined region in a surface portion in p-type silicon carbide semiconductor layer 3. Further, a low-resistance p-type silicon carbide region 6 is formed in a predetermined region in a surface layer portion in p-type silicon carbide semiconductor layer 3.

A groove 7 is formed in a predetermined region of the n ⁺ type source region 5.
Is formed, and penetrates n ⁺ -type source region 5 and p-type silicon carbide semiconductor layer 3 to reach n ⁻ -type silicon carbide semiconductor layer 2. The groove 7 is a side surface 7 perpendicular to the surface of the semiconductor substrate 4.
a and a bottom surface 7 b parallel to the surface of the semiconductor substrate 4. A hexagonal region (only a part of the hexagon is shown in FIG. 1) surrounded by the side surface 7a of the groove 7 becomes the island-shaped semiconductor region 12. That is, the island-shaped semiconductor region 12 includes the p-type silicon carbide semiconductor layer 3 formed on the n ⁻ -type silicon carbide semiconductor layer 2, the n ⁺ -type source region 5 formed on the p-type silicon carbide semiconductor layer 3, and the low resistance. A plurality of regions including the p-type silicon carbide region 6 and separated from other island-shaped semiconductor regions 12. In the present embodiment, the side surface 7a of the groove 7 is substantially [11-0].
0] direction. Further, the planar shape of the side surface 7a of the groove 7 is a hexagon whose interior angles are substantially equal. That is,
In the plan view of the substrate 4 shown in FIG.
1, S2, S3, S4, S5, S6, and edges S1 and S
2, the angle between the sides S2 and S3 (the interior angle), the angle between the sides S3 and S4 (the interior angle), the sides S4 and S5
(Inner angle), an angle (inner angle) between sides S5 and S6, and an angle (inner angle) between sides S6 and S1 are approximately 120 °. By forming the island-shaped semiconductor region 12 in this manner, a region that becomes a concave portion in the planar shape is not formed.

Further, the surface of the side surface 7a in the groove 7 and the groove 7
A gate insulating film 8 is formed on the bottom surface 7b of the substrate. Groove 7
Inside the gate insulating film 8, a gate electrode layer 9 is formed.
Is filled. Gate electrode layer 9 is covered with insulating film 10. Source electrode layer 11 as a first electrode layer is formed on the surface of n ⁺ -type source region 5 and the surface of low-resistance p-type silicon carbide region 6. On the surface of n ⁺ -type silicon carbide semiconductor substrate 1 (the back surface of semiconductor substrate 4), a drain electrode layer 13 as a second electrode layer is formed.

As described above, the vertical power MOSFET is
The channel forming surface is parallel to the [11-00] direction.
As shown in FIG. 2, outside the hexagonal island-shaped semiconductor region 12,
A groove is arranged on the side. Next, the vertical power MOSFET
The manufacturing process of T will be described with reference to FIGS. First,
As shown in FIG. 3, the main surface is substantially (0001-) carbon
N which is a surface⁺Type silicon carbide semiconductor substrate 1 is prepared and its table
N on face^-Type silicon carbide semiconductor layer 2 is epitaxially grown
And then n^-P-type silicon carbide on p-type silicon carbide semiconductor layer 2
The semiconductor layer 3 is epitaxially grown. Like this
And n⁺-Type silicon carbide semiconductor substrate 1 and n ^-Type silicon carbide semiconductor
Semiconductor substrate comprising body layer 2 and p-type silicon carbide semiconductor layer 3
4 are formed.

Next, as shown in FIG.
In a predetermined region of the surface portion of the conductor layer 3, n ⁺Mold source region 5
For example, it is formed by ion implantation of nitrogen. Furthermore, p-type
Low resistance p is applied to another predetermined region of the surface layer portion of silicon carbide semiconductor layer 3.
Type silicon carbide region 6 for ion implantation of aluminum, for example.
Formed. Then, as shown in FIG.
RIE (Reactive Ionetching)
n⁺Source region 5 and p-type silicon carbide semiconductor layer 3
Through n^-Groove 7 reaching type silicon carbide semiconductor layer 2 is formed.
To achieve. At this time, the side surface 7a of the groove 7 is oriented in the [11-00] direction.
The trench 7 is formed so as to be parallel to the island-shaped semiconductor region 12.
To form Therefore, as shown in FIG.
Shape of island semiconductor region 12 in plan view of OSFET
Are hexagonal on the main surface.

Subsequently, as shown in FIG. 6, a gate insulating film 8 is formed on the side surface 7a of the semiconductor substrate 4 and the groove 7 and the bottom surface 7b of the groove 7. At this time, the gate insulating film 8 is formed by thermal oxidation in a wet atmosphere. This wet oxidation is performed by a method called a pyrogenic method. As a film forming condition, the semiconductor substrate 4 on which the groove 7 is formed is placed in a thermal oxidation furnace, the temperature in the furnace is increased to 1100 ° C., and hydrogen (H ₂ )
And oxygen (O ₂ ) were introduced at a ratio of 4: 3, and hydrogen and oxygen were burned to produce steam, thereby forming steam, oxygen, and a thermal oxide film. In this embodiment, the growth rate of the oxide film is 25.
nm / h and grown to 100 nm. On the other hand, dry oxidation is a method of forming an oxide film by supplying only oxygen. Then, as shown in FIG. 7, the inside of the gate insulating film 8 in the trench 7 is filled with the gate electrode layer 9. Further, as shown in FIG. 8, an insulating film 10 is formed on the upper surface of the gate electrode layer 9. Thereafter, as shown in FIG.
The source electrode layer 11 is formed on the source region 5 including the upper region 0 and the low-resistance p-type silicon carbide region 6. Further, a drain electrode layer 12 is formed on the surface of n ⁺ type silicon carbide semiconductor substrate 1 to complete a trench gate type power MOSFET.

As described above, in this embodiment, the groove 7
The shape is such that the island-shaped semiconductor region 12 is surrounded by the side surface 7a of the trench 7 and that no recess is formed in the island-shaped semiconductor region 12 in the plan view as shown in FIG. Is formed, a highly reliable gate insulating film 8 can be obtained. Further, the interface state density can be reduced, the channel mobility can be improved, and the on-resistance can be reduced.

In this embodiment, the vertical MOSF
The side surface 7a of the groove 7 forming the ET channel is set to [11-0].
0] direction, and the gate insulating film 8 is formed on the side surface 7a of the groove 7 by wet oxidation.
16, the interface state can be reduced most as shown in FIG. 16, whereby the channel mobility can be improved, and a transistor which can effectively reduce on-resistance can be provided.

In addition to the configuration described above, for example, n
^The source electrodes formed in ⁺ type source region 5 and low resistance p-type silicon carbide region 6 may be made of different materials. Also, low resistance p
Type silicon carbide region 6 can be omitted. In this case, source electrode layer 11 is formed to be in contact with n ⁺ type source region 5 and p type silicon carbide semiconductor layer 3. Also, the source electrode layer 11
May be formed at least on the surface of the n ⁺ type source region 5.

Further, in the above-described example, the case where the present invention is applied to an n-channel vertical MOSFET has been described.
P-channel vertical MO with p-type and n-type interchanged
The same effect can be obtained in the SFET. Further, in FIG. 1, the side surface 7 a of the groove 7 is substantially 90 ° with respect to the substrate surface, but as shown in FIG. 9, the angle between the side surface 7 a of the groove 7 and the substrate surface is not necessarily close to 90 °. You may. The groove 7 may be V-shaped without a bottom surface. Further, as shown in FIG. 10, the side surface 7a of the groove 7 may not be a flat surface, but may be a smooth curved surface. A better effect can be obtained by designing the angle between the side surface 7a of the groove 7 and the substrate surface so as to increase the channel mobility.

As shown in FIG. 11, the upper portion of gate electrode 9 may have a shape extending above n ⁺ type source region 5. In the present embodiment, the surface shape of the island-shaped semiconductor region 12 is hexagonal. However, the surface shape may be a smooth ellipse or circle as shown in FIG. 12, or a triangular shape as shown in FIG. Even so, if the grooves are formed on the outside, the effect of the present invention can be expected.

[Brief description of the drawings]

FIG. 1 is a perspective view of a vertical power MOSFET.

FIG. 2 is a plan view of a substrate.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of the vertical power MOSFET.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the vertical power MOSFET.

FIG. 5 is a sectional view illustrating a manufacturing process of the vertical power MOSFET.

FIG. 6 is a sectional view illustrating a manufacturing process of the vertical power MOSFET.

FIG. 7 is a sectional view for explaining a manufacturing process of the vertical power MOSFET.

FIG. 8 is a sectional view for explaining a manufacturing process of the vertical power MOSFET.

FIG. 9 is a cross-sectional view of a vertical power MOSFET of an application example.

FIG. 10 is a schematic sectional view of a vertical power MOSFET according to an application example.

FIG. 11 is a schematic cross-sectional view of a vertical power MOSFET of an application example.

FIG. 12 is a plan view of a substrate illustrating an application example.

FIG. 13 is a plan view of a substrate illustrating an application example.

FIG. 14A is a plan view illustrating a conventional semiconductor device. (B) is a partially enlarged view of (a).

FIG. 15A is a plan view illustrating the concept of a semiconductor device of the present invention. (B) is a partially enlarged view of (a).

FIG. 16 is a characteristic diagram showing plane orientation dependency of interface state density in a hexagonal silicon carbide semiconductor.

[Explanation of symbols]

Reference Signs List 1 n ⁺ -type silicon carbide semiconductor substrate 2 n ^-- type silicon carbide semiconductor layer 3 p-type silicon carbide semiconductor layer 4 semiconductor substrate 5 half n ⁺ -type source region 7 groove 7 a side surface 7 b bottom surface 8 gate insulating film 9 gate electrode layer 10 insulating film 11 source electrode layer 13 drain electrode layer

Claims (6)

[Claims] 1. A semiconductor substrate made of single-crystal silicon carbide, in which a low-resistance semiconductor layer of a first conductivity type, a high-resistance semiconductor layer of a first conductivity type, and a semiconductor layer of a second conductivity type are sequentially stacked. A first conductivity type semiconductor region formed in a predetermined region of a surface layer portion of the layer; and a semiconductor region extending from a main surface of the semiconductor layer through the semiconductor region and the semiconductor layer to reach the high resistance semiconductor layer. A groove having a side surface exposing the semiconductor layer and a bottom surface exposing the high-resistance semiconductor layer; an island-shaped semiconductor having the semiconductor layer and the semiconductor region and formed to be surrounded by the side surface of the groove A region, a gate insulating film formed on at least a side surface of the trench surrounding the island-shaped semiconductor region, a gate electrode layer formed on the gate insulating film, and at least the island-shaped semiconductor in the main surface Territory A silicon carbide semiconductor device, comprising: a first electrode formed on a surface of the semiconductor region in a region; and a second electrode formed on a back surface of the low-resistance semiconductor layer. 2. The island-shaped semiconductor region has a polygonal planar shape, and each interior angle of the polygon is 18
The silicon carbide semiconductor device according to claim 1, wherein the angle is less than 0 degrees. 3. The carbonization device according to claim 2, wherein sides of the polygon are substantially parallel to [11-00], and the gate insulating film is a thermal oxide film formed by thermal oxidation in a wet atmosphere. Silicon semiconductor device. 4. The silicon carbide semiconductor device according to claim 3, wherein said polygon is a hexagon whose interior angles are substantially equal. 5. A semiconductor substrate made of single-crystal silicon carbide by sequentially laminating a first-conductivity-type low-resistance semiconductor layer, a first-conductivity-type high-resistance semiconductor layer, and a second-conductivity-type semiconductor layer. A second step of forming a first conductivity type semiconductor region in a predetermined region of a surface layer portion of the semiconductor layer; and a high resistance which penetrates both the semiconductor region and the semiconductor layer from a main surface of the semiconductor layer. Forming a groove having a side surface reaching the semiconductor layer and exposing the semiconductor region and the semiconductor layer and a bottom surface exposing the high-resistance semiconductor layer; and forming a groove having the semiconductor layer and the semiconductor region and a side surface of the groove. A third step of forming an island-shaped semiconductor region surrounded by; a fourth step of forming a gate insulating film on at least side surfaces of the trench surrounding the island-shaped semiconductor region; and a gate electrode layer on the gate insulating film. Fifth process to form And a sixth step of forming a first electrode on at least the surface of the semiconductor region in the island-shaped semiconductor region of the main surface, and forming a second electrode on the back surface of the low-resistance semiconductor layer. A silicon carbide semiconductor device characterized by the above-mentioned. 6. In the third step, the side surface of the groove is formed substantially parallel to the [11-00] direction, and
6. The silicon carbide semiconductor device according to claim 5, wherein in said step, said gate insulating film is formed by thermal oxidation in a wet atmosphere.