JPH10293684A - Computer system and start-up control method thereof - Google Patents

Abstract

[PROBLEMS] To efficiently execute various hardware control functions provided by a system BIOS without impairing compatibility with an existing system. A system BIOS of a BIOS-ROM 14 is provided.
Of these, the system BIOS # 2 including the POST routine and the extension driver routine is in a protected mode, and the system BIOS # 2 is accessible only in the protected mode.
0h and assigned to the CPU address space
For the system BIOS # 1 including the S driver group, the address space F0 accessible in the real mode as in the related art is used.
000h to FFFFFh. As a result, the entire system BIOS can be kept open at all times.
The S processing can be immediately executed, and the system performance can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system and a startup control method thereof, and more particularly to a computer system having a CPU having a real mode and a protection mode and a startup control method thereof.

[0002]

2. Description of the Related Art Generally, an operation mode of a CPU used in a PC / AT compatible personal computer includes:
A real mode in which memory addresses 000000h to 0FFFFFh can be accessed, and a CPU address 000000h
There is a protect mode accessible from h to 0FFFFFFFFh. In the real mode, access to addresses after the CPU address 100000h cannot be performed. These two CPU operation modes have different segment management methods.

[0003] The protect mode is a function mounted from a CPU of microprocessor 80286 or later manufactured by Intel Corporation of the United States, and is not mounted on the 8086 or the like. In addition, the 80286 has a limitation that the CPU must be reset once in order to shift the CPU operation mode from the protect mode to the real mode.
Under such circumstances, it has been determined that the system BIOS used in a PC / AT compatible personal computer operates in the real mode. Even today, when the operating system operating in the protected mode is the mainstream, it is natural that the system BIOS is configured to operate in the real mode.

System BIOS operating in real mode
Cannot access the memory address space after 100000h. Therefore, system B
When the memory address space after 100000h is accessed from the IOS, as shown in the flowchart of FIG. 11, the CPU operation mode is temporarily switched from the real mode to the protect mode, and then the segment register is set to perform the operation after 100000h. Specify memory address space as segment base address,
A method has been adopted in which the access is performed after the mode is shifted to the real mode again (steps S102 to S105).
According to this method, in the protect mode, a memory address value after 100000h, which cannot be specified in the real mode, can be specified as a segment base address, and the set value of the segment register at that time is not changed unless the setting is changed again. This is based on the fact that it is effective even when returning to the mode.

However, in the real mode, actually, only 64 Kbytes of 0000h to 0FFFFh can be accessed in one segment.
To access another segment after the CPU address 100000h, it is necessary to shift to the protect mode again and change the setting of the segment register again. Therefore, when the system BIOS initializes the memory after the CPU address 100000h,
As shown in FIG. 11, the aforementioned step S102
It is necessary to repeat the processing of steps S105 to S105 in units of 64 Kbyte segments until initialization of the last 64 Kbytes of the memory mounted on the system is completed.

In a PC / AT compatible machine, system B
The BIOS-ROM storing the IOS has a CPU address F
It is allocated to 64K bytes of 0000h to FFFFFh, and can be accessed only through the address range of 64K bytes.

However, in recent years, the number of functions such as PnP and power save function has increased, and
Is no longer fit in 64K bytes, 128
Usually, a program size of about K bytes is required.

In this case, the portion of the system BIOS exceeding 64 Kbytes is allocated to a part of the area from C0000h to EFFFFh.
-Since the area is allocated to the BIOS and the option ROM, the system BIOS cannot always be opened there. Further, since the system BIOS operates in the real mode, it cannot be opened in the CPU address space after 100000h. Therefore, the system BIOS
Must be allocated to the area from C0000h to EFFFFh only when necessary, and the system BIOS must be closed when not used.

[0009] Switching of the CPU address mapping involves processing such as cache flush. This is because before and after the switching of mapping, different instructions and data exist in the same memory address space, and a malfunction occurs unless the cache is invalidated.

FIG. 12 shows a closed system BI.
The flow for accessing the OS area is shown. First, the service routine in the system BIOS to be started is determined by CPU addresses F0000h to FFFFFh.
It is checked which of the system BIOS area allocated to 64 Kbytes of the system BIOS area and the closed system BIOS area exists (step S111). If the service routine exists in the system BIOS area allocated to the 64 Kbytes of the CPU addresses F0000h to FFFFFh, the memory mapping is not switched, and the requested processing is immediately executed by activating the service routine. (Step S11
2).

On the other hand, if the service routine to be started exists in the closed system BIOS area,
First, a cache flush is executed (step S1).
13), frequently used instructions and data stored in the cache are invalidated. Next, the memory mapping is switched, and the system BIOS area closed by this is changed from C0000h to EFFFF.
After being rearranged in a part of the area h, the target service routine is executed (steps S114 and S115).
When the processing of the service routine ends, the cache flush is executed again (step S116), and thereafter,
The memory mapping is returned to the original state (step S1
17).

As described above, conventionally, the system BIOS
When a portion exceeding 64 Kbytes is used, it is necessary to switch between the cache flush and the memory mapping each time, and this causes a problem that overhead occurs.

[0013]

As described above, conventionally, since the system BIOS operates in the real mode, when the memory after the CPU address 100000h is initialized and tested, the segment register is set every 64 Kbytes. Has to be changed, which causes a problem that overhead occurs. Further, when a portion exceeding 64 Kbytes of the system BIOS is used, it is necessary to switch the memory mapping accompanied by the cache flush, which causes a problem that overhead occurs.

The present invention has been made in view of the above points, and is a computer capable of efficiently executing various hardware control functions provided by a system BIOS without impairing compatibility with an existing system. It is an object to provide a system and a startup control method thereof.

[0015]

According to the present invention, there is provided a first operation mode in which a first memory address space can be accessed, and a second memory address located in the first memory address space and an address higher than the first memory address space. In a computer system including a CPU having a second operation mode capable of accessing a space and a system ROM storing a system program for hardware control, the system program can operate in the first operation mode And a second program operable in the second operation mode, wherein the first program is arranged in the first memory address space, and the second program is stored in the first memory address space. And a means for arranging in the second memory address space.

In this computer system, a part of the system BIOS is in a protected mode, and that part is assigned to a CPU address space of 100000h or later which can be accessed only in the protected mode. Address space F0000h to FFFF accessible in real mode
Fh. As a result, the entire system BIOS can always be kept open in the memory address space even after the operating system is started.

Therefore, by setting a protection mode in a test program or the like which describes the procedure of hardware initialization and test processing to be executed from the time the computer system is powered on to the time the operating system is started, The main memory can be initialized without performing complicated segment management such as resetting the register in units of 64 Kbytes. As a result, the time from when the computer system is powered on to when the operating system is started can be significantly reduced.

Also, since the entire system BIOS can be kept open at all times, the BIOS processing requested by the operating system or the like can be immediately executed without switching memory mapping or performing cache flush, thereby improving system performance. Can be achieved.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a computer system according to an embodiment of the present invention. This system is for realizing a portable personal computer of a notebook type or a laptop type. As shown in FIG.
PU 11, system controller 12, main memory 13,
BIOS-ROM 14, real-time clock (RT
C) 15, an interrupt controller (PIC) 16, a keyboard controller (KBC) 17, a display controller 18, and the like.

On the system board, a CPU local bus (sometimes called a processor bus) 31,
A system bus 32, a memory address bus 33, and the like are provided.

The CPU 11 is a microprocessor having a large-scale cache memory built therein. For example, Pentium manufactured by Intel Corporation of the United States is used. This CPU1
1 has two types of operation modes having different address calculation formats, a real mode and a protect mode. The real mode is an operation mode in which a memory address space of up to 1 Mbyte can be accessed. A segment base address is determined by a selector value set in a segment register, and a physical memory address is determined by a 16-bit offset value starting from the segment base address. Is determined. The offset value of each segment is 64
Limited to K bytes. In the protect mode, the protect mode is an operation mode in which a memory space of a maximum of 4 Gbytes can be accessed per task. The segment base address is determined by referring to the descriptor table according to the selector value of the segment register, and the segment base address is determined from the segment base address. The linear address is determined by the starting 32-bit offset value. This linear address becomes a physical memory address as it is when paging is not used, and is finally converted to a physical address by a page table when paging is used.

The CPU 11 is connected to the system controller 12 via a CPU local bus 31. CP
The U local bus 31 is a group of signals directly connected to input / output pins of a microprocessor constituting the CPU 11.

Here, a 32 or 64 bit data bus, a 32 bit address bus, and W / R #, MI
Various status signal lines including signal lines such as O # are included. When the W / R # line is at "H" level, it indicates that the current bus cycle is a write access cycle, and when it is at "L" level, it indicates that it is a read access cycle. When the MIO # line is at "H" level, it indicates that the current bus cycle is a memory access cycle, and when it is at "L" level, it indicates that it is an I / O access cycle.

The system controller 12 is connected between the CPU local bus 31 and the system bus 32, and controls a memory and an I / O device in the system according to a request from the CPU 11. The system controller 12 is realized by a single LSI constituted by a gate array, in which a logic for controlling a memory and an I / O is incorporated.

The main memory 13 stores an operating system, an application program to be executed, and various kinds of processing data. This main memory 13
Is composed of a plurality of DRAM banks mounted on a system board. Each DRAM bank has multiple D
It has a RAM chip.

The main memory 13 is a 32-bit or 64-bit memory device, and its data port is connected to the data bus of the CPU local bus 31, and its address input port is connected to the memory address bus 33.
The memory address bus 33 is an address bus dedicated to the DRAM, and the physical address of the DRAM (row address RA / column address C
A) is output from the system controller 12. The main memory 13 is connected to row address strobe signal lines RAS0 to RAS5, a column address strobe signal line CAS, a write enable signal line WE, an output enable signal line OE, and a chip select signal line CS. In this case, RAS0 to RAS5 are respectively connected to a plurality of DRAM banks constituting the main memory 13, and CAS, WE, OE, and CS are commonly connected to all DRAM banks.

In this system, a part of the storage area of the main memory 13 is used as a copy area 131 in which the contents of the BIOS-ROM 14 are copied. The read / write access to the copy area 131 is performed in the same manner as in the other storage areas of the main memory 13 by the memory address from the system controller 12 and various control signals (RA
S, CAS, WE, OE, CS, etc.). In this case, the copy area 131 can be write-protected under the control of the system controller 12 to prohibit write access to the copy area 131.

The BIOS-ROM 14 stores the system bus 3
2 is an 8-bit or 16-bit device, and is configured from a flash memory so that its stored contents can be rewritten. This BIOS-ROM1
4 normally stores a system BIOS and a VGA-BIOS, but in the present embodiment, the system BIOS is divided into two in order to always keep the entire system BIOS open in the CPU address space. One is implemented as a protected mode program. FIG. 2 shows an example of the contents stored in the BIOS-ROM 14.

As shown in FIG. 2, the BIOS-R
The OM 14 includes a first system BIOS (system BIOS).
OS # 1), the second system BIOS (system BIOS)
S # 2), VGA-BIOS, and the like. Among them, the second system BIOS (system BIOS)
OS # 2) is coded to operate in the protected mode, and the first system BIOS
(System BIOS # 1) and VGA-BIOS are coded to operate in the real mode as before.

The system BIOS # 1 is composed of a group of various BIOS drivers started by using a software interrupt instruction (INTXXh) of the CPU. These BIOS drivers are located in the CPU memory address space 0.
It is composed of a plurality of function execution routines each addressed by an interrupt vector existing in an area starting from 0000h. These function execution routines of the BIOS driver group are executed in response to a software interrupt instruction executed by an operating system or an application program, and therefore are not usually executed before the operating system is started. In order to maintain compatibility with the existing system, the system BIOS # 1 is allocated to 64 Kbytes of CPU addresses F0000h to FFFFFh accessible in the real mode after the operating system is started.

The system BIOS # 2 executes POST (Po
(Wer On Self Test) routine, an extension driver for function extension, and various service routines (power save routine,
SMI routine).

The POST routine is a program executed first when the computer system is turned on. The POST routine includes an initialization routine for initializing and testing hardware such as a memory and I / O.
It includes a ROM / RAM copy routine for copying the contents of the IOS-ROM 14 to the main memory 13 composed of a DRAM, a boot routine for starting the OS, and the like. These POST routine programs are usually executed only before the activation of the operating system, and are not executed after the activation.

The extension driver is provided for the purpose of adding a function provided by a driver program of the system BIOS # 1, and the system BIOS called from the operating system or an application program after the operating system is started.
Called as needed by S # 1. The power save routine and the SMI routine are for performing power management of the computer system and various system management using SMI (system management interrupt) in cooperation with the operating system. Called from as needed.

All of the programs included in the system BIOS # 2 are configured to operate in the protect mode. When the system is powered on, the CPU addresses F0000h to FFFFFh are used to enable the POST routine to be executed first. Although allocated to 64 Kbytes, it is relocated to a predetermined 64 Kbyte CPU address space after 100000h.

The VGA-BIOS is a program for controlling the display controller 18 of the computer system. In order to maintain compatibility with the existing system, the CPU address accessible in the real mode after the operating system is started up. From C0000h to C
It is located in 64K bytes of FFFFh.

As described above, in this embodiment, the system BIOS # 1 including the BIOS driver group, which is a program in the real mode, is controlled by the CPU as usual.
The address is allocated to 64 Kbytes of addresses F0000h to FFFFFh. For the system BIOS # 2 configured by a POST routine or the like in the protected mode, it is allocated to the CPU address space after 100000h. Therefore, even after the control is transferred to the operating system, the entire system BIOS can always be kept open in the memory address space.

The real-time clock (RTC) 1 shown in FIG.
5. The interrupt controller (PIC) 16 and the keyboard controller (KBC) 17 are respectively ISA
It is an 8-bit or 16-bit I / O device with specifications.

The display controller 18 conforms to the VGA specification, and controls the display of an LCD panel provided as standard equipment on the computer body and the display of a CRT display that is optionally connected. The video memory (VRAM) 181 stores display data. The read / write control of the video memory (VRAM) 181 is performed by the display controller 18.

Next, the configuration of the memory control subsystem provided in the system controller 12 will be described.
As shown, the memory control subsystem includes a CPU controller 121, an access controller 122, and a DRA.
It comprises an M mapper 123, a DRAM controller 124, and a bus controller 125.

The CPU controller 121 performs bus cycle control of the CPU 11 and CPU address decoding in cooperation with the access controller 122. CPU
An attribute register file 201 provided in the CPU controller 121 is used for address decoding.

Attribute register file 201
Is for defining a memory address map of the computer system, and comprises a plurality of attribute registers respectively corresponding to a plurality of memory address areas constituting a memory address space of the CPU 11.

Each attribute register is an I / O control register that can be read / written by the CPU 11, and each register has a type of a memory device (DRAM, B
Attribute information (ATTRIBUTE) for designating an IOS-ROM, an option ROM, etc. is set. The attribute information includes read attribute information for a memory read cycle and write attribute information for a memory write cycle,
As a result, the type of the memory device to be arranged in each memory address area can be separately specified in the memory read cycle and the memory write cycle.

When the CPU 11 executes a bus cycle for memory access, the CPU address (A31: 0)
The attribute information of the memory address area corresponding to the value of 2) is read from the attribute register file 201 and sent to the access controller 122.

The access controller 122 determines the type of the memory device to be accessed according to the attribute information read from the attribute register file 201, and determines one memory controller corresponding to the type of the memory device, that is, the DRAM controller 1
24 or the bus controller 125 to execute a memory cycle. In this case, the type of the memory device to be accessed is determined by the read attribute information in the attribute information read from the attribute register file 201 when the bus cycle of the CPU 11 is a memory read cycle, and in the case of a memory write cycle. Is determined by the light attribute information. Whether the bus cycle of the CPU 11 is a memory read cycle or a memory write cycle can be detected by the logic level of the W / R # signal.

The DRAM mapper 123 converts the CPU address (A31: 02) into the DRAM address (MA31: 0).
Convert to 2). This conversion is performed in order to allocate a DRAM memory area distributed in the memory address space of the CPU 11 to a continuous address space dedicated to DRAM access. Here, an example of the address conversion operation will be described with reference to FIG.

FIG. 3A is a memory address map used in this embodiment, and FIG.
It is a DRAM address space corresponding to the memory address map of FIG.

The DRMM address space of this embodiment is an example in which a so-called "high-speed ROM" function is employed. The "high-speed ROM" function is a function for reading the contents of the low-speed BIOS-ROM 14 from a DRAM that can be accessed at a high speed. The contents of the BIOS-ROM 14 are read from the DRAM using the ROM / RAM copy routine described above. This is realized by copying to the copy area 131 and mapping the copy area 131 to the CPU address space. When this high-speed ROM function is adopted, the BIOS-
A DRAM is accessed instead of the ROM 14. Therefore, the instruction code of the system BIOS can be fetched from the DRAM at a high speed, and the system BIOS can be fetched.
It is possible to increase the execution speed of an OS or an application program that frequently uses S.

As shown in FIG. 3A, the CPU
In addition to a DRAM address area for arranging a DRAM such as a conventional memory area and an extended memory area, a memory address space other than the DRAM shown by hatching (VRAM, BIOS-ROM, Option ROM
) Are allocated. The address range for accessing the VGA-BIOS is 64 Kbytes from C0000h to CFFFFh. The address range for accessing the system BIOS # 1 is 6 from F0000h to FFFFFh.
4K bytes, the address range for accessing the system BIOS # 2 is 6 at the end of the DRAM address area.
4K bytes (here, FE0000h to FEFFFF
h).

VGA BIOS of BIOS-ROM 14
Since the system BIOS # 1 and # 2 are copied onto the DRAM and used, the CPU addresses (A31: 02) belonging to all the memory address areas except the VRAM and the option ROM are actually changed to the DRAM address (MA31: 02). By this address conversion, the CPU addresses in the DRAM address area immediately before and immediately after the address areas of the VRAM and the option ROM become continuous addresses in the DRAM address space.

The conversion from the CPU address to the DRAM logical address is performed in units of 16 Kbytes, for example. As a result, the lower-order bit portion (MA13: 02) of the DRAM logical address is maintained even after the address conversion.
It is equal to the lower bit part (A13: 02) of the CPU address.

The DRAM logical address (MA31: 02) obtained by the DRAM mapper 123 is the
The data is sent to the RAM controller 124. When the access controller 122 indicates that the bus cycle of the CPU 11 is a DRAM cycle, the DRAM controller 124 sets the access control signals (RAS, CA
S, WE, OE, CS) and DRAM physical addresses (row address RA, column address CA)
The access cycle of the main memory 13, that is, the DRAM is executed. Row address RA and column address CA
Is obtained by decomposing the DRAM logical address (MA31: 02).

When the access controller 122 instructs the bus cycle of the CPU 11 to be a memory access cycle for the BIOS-ROM 14 on the system bus 32, the bus controller 125 sends a chip select signal to the BIOS-ROM 14 on the system bus 32. And the access control of the BIOS-ROM 14 is performed at a timing corresponding to the bus cycle of the system bus 32.

Next, attribute register file 2
The attribute information managed by 01 will be specifically described. First, the relationship between the memory address space of the CPU 11 and the attribute information managed for each area by the attribute register file 201 will be described with reference to FIG.

As described above, the size of one address area managed by the attribute register file 201 is 16 Kbytes, and as shown in FIG.
FFFFFFFFh is 1 in order from 00000000h
An AREA number is defined in units of 6 Kbytes. DR
For AREA in which a plurality of types of memory devices including an AM may be arranged, 8-bit attribute information as shown in FIG. 5 is set in each attribute register.

As shown in FIG. 5, of the 8-bit attribute information, two bits of bit 7 and bit 6 are read attribute information (READ ATTRIBUTE) and bit 5
And bit 4 are write attribute information (WRITE
ATTRIBUTE) and bit3 are used as DRAM write protect information (WP), and two bits of bit2 and bit1 are used as caching control information (CASH).

Read attribute information (READ ATTRIB)
UTE) indicates the type of the memory device to be read-accessed. As shown in FIG. 6, the combination of two bits, bit7 and bit6,
One of a DRAM and a memory on a system bus is specified.

Write attribute information (WRITE ATTRI)
BUTE) indicates the type of the memory device to be write-accessed. As shown in FIG. 7, depending on the combination of the bit5 and bit4, either the DRAM or the memory on the system bus is determined. It is specified.

As described above, by separately defining the read attribute information and the write attribute information for each area, an MO that specifies the same transfer source and transfer destination addresses is designated.
ROM / RAM copy can be realized only by the V instruction.

DRAM write protect information (WP)
Indicates that the DRAM is designated as a write-access target memory device by the write attribute information.
3 indicates whether or not to perform write protection on the DRAM.

[0060] The caching control information (CASH) is DRA based on the read attribute information and the write attribute information.
When M is designated, it controls the validity / invalidity of the caching operation of the RAM, and the write-back cache enable, the write-through cache enable, and the cache are controlled by a combination of two bits of bit2 and bit1. One of disable is specified.

Using the DRAM write protect information (WP) and the caching control information (CASH), write protect is set for the DRAM area where the VGA-BIOS and system BIOS # 1 and # 2 have been copied, Settings such as disabling can be performed.

Next, referring to the flowchart of FIG.
The operation of the system shown in FIG. 1 when the power is turned on will be described.
When the computer system of FIG. 1 is powered on, C
The PU 11 is reset and starts operating in the real mode (step S201). At system power on,
As described above, the system BI of the BIOS-ROM 14
OS # 2 is the CPU memory address E0000-EFFF
F is assigned to the address FF.
Fetch the instruction at FF0. Thereby, the system B
Execution of the POST routine of IOS # 2 is started in a real mode environment.

The POST routine is executed by the CPU 11
The operation mode of the CPU 11 is changed from the real mode to the protect mode by setting a register or the like (step S202). Thereafter, the POST routine starts a memory check in the protect mode (step S203). In this memory check, the storage size of the main memory 13 is checked by a read / write compare process for the DRAM provided in the system. That is, in the memory check, as shown in FIG. 9, the POST routine first sets the segment registers so as to enable access to the entire CPU memory address space (step S301). While sequentially updating the address, the memory write access, the memory read access, the comparison between the write data and the read data are performed, and the DRAM size is checked according to the result (step S302).

As described above, the POST in the protect mode is performed.
Initialization of the memory check by the routine allows all DRs to be set only by setting the segment register once.
It is possible to check the AM address space.

When the memory check is completed, the POST routine executes the BIOS-R by ROM / RAM copy.
The contents of the OM 14 are copied to the copy area 131 of the DRAM (Step S204). This ROM / RAM copy can be realized in various ways, one example of which is as follows.

That is, first, the DRAM and the BIOS-ROM 14 are arranged on the same address space by setting the write attribute information and the read attribute information of the CPU memory address range corresponding to the copy area 131 of the DRAM. In this case, the read device is the BIOS-ROM 14
Then, the write device is set to DRAM. And M
By repeatedly executing the OV instruction while incrementing the address, the VGA-BIOS of the BIOS-ROM 14 and the system B are stored in the DRAM copy area 131.
IOS # 1 and system BIOS # 2 are copied.

Thereafter, the memory mapping is changed by the attribute register file 201, and the VGA-BIOS, the system BIOS # 1, and the system BIOS # 2 on the DRAM are respectively assigned the CPU address C0000h.
To CFFFFh, F0000h to FFFFFh, and FE0000h to FEFFFFh (step S205). And FE0000h-FEFFFF
The control is transferred to the POST routine of the system BIOS # 2 located in the h, and the initialization processing of the I / O device and the execution of the boot routine are performed (step S2).
06). Next, after changing the operation mode of the CPU 11 from the protection mode to the real mode by setting the MSW register of the CPU 11 (step S202),
Control is passed to the OS.

Next, the execution procedure of the BIOS function routine will be described with reference to the flowchart of FIG. As described above, after the OS is started, the system BIOS including the BIOS driver group is used.
Since S # 1 is located at the CPU addresses F0000h to FFFFFh, a request from the OS or the application program is accepted by the system BIOS # 1.

The system BIOS # 1 is composed of a system BIOS # 1 in which a requested service routine in the system BIOS is allocated to 64 Kbytes of CPU addresses F0000h to FFFFFh, and FE0000h to FE0000h.
It is checked which of the system BIOS # 2 allocated to FFFFh exists (step S401). If the service routine exists in the system BIOS # 1,
Upon activation of the service routine, the requested processing is immediately executed (step S402).

On the other hand, if the service routine to be started exists in the extension driver of the system BIOS # 2, the control is transferred to the service routine existing in the system BIOS # 2, and the processing requested by the service routine is executed. (Steps S403 and S40)
4).

As described above, in this embodiment,
A system BIOS # 2 including a POST routine and an extension driver routine is in a protected mode, and the system BIOS # 2 has a CPU of 100000h or later that can be accessed only in the protected mode.
Address space F0000h to FFF which is assigned to the address space and which can be accessed in the real mode as in the conventional system BIOS # 1 including the BIOS driver group
Assigned to FFh. As a result, the main memory 13 can be initialized without performing complicated segment management such as resetting the segment register in units of 64 Kbytes. As a result, the time from when the computer system is powered on to when the operating system is started can be significantly reduced.
Also, since the entire system BIOS can always be open,
The BIOS process requested by the operating system or the like can be executed immediately without switching memory mapping or performing a cache flush, and system performance can be improved.

[0072]

As described above, according to the present invention, the entire system BIOS can be always opened without losing compatibility with existing systems, and various hardware controls provided by the system BIOS can be provided. The function can be executed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to one embodiment of the present invention.

FIG. 2 is a view showing the structure of a system BIOS in the system of FIG. 1;

FIG. 3 is a view showing an example of a memory address map in the system of FIG. 1;

FIG. 4 shows attribute information and CP managed by an attribute register file provided in the system of FIG.
The figure which shows the relationship with U memory address space.

FIG. 5 is a view showing a format of attribute information set in an attribute register file provided in the system of FIG. 1;

FIG. 6 is a view showing contents of lead attribute information included in the attribute information of FIG. 5;

FIG. 7 is a view showing the contents of write attribute information included in the attribute information of FIG. 5;

FIG. 8 is a flowchart showing a procedure of a startup process of the system in FIG. 1;

FIG. 9 is an exemplary flowchart showing the procedure of a memory initialization process executed in the startup process of FIG. 8;

FIG. 10 is a flowchart for explaining a startup processing operation of a BIOS function routine in the system of FIG. 1;

FIG. 11 is a flowchart showing a procedure of a conventional memory initialization process.

FIG. 12 is a flowchart illustrating a conventional BIOS function routine activation processing operation.

[Explanation of symbols]

11 CPU, 12 system controller, 13 main memory, 14 BIOS-ROM, 18 display controller, 121 CPU controller, 122
Access controller, 124: DRAM controller, 125: ISA controller.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshitaka Sanada 1381-1, Shinmachi, Ome-shi, Tokyo Toshiba Computer Engineering Co., Ltd. (72) Inventor Manabu Korai 1381-1, Shinmachi, Ome-shi, Tokyo Toshiba Computer -Within TA Engineering Co., Ltd. (72) Inventor Naobu Fujiwara 1381 Shinmachi, Ome-shi, Tokyo Toshiba Computer Engineering Corporation

Claims (8)

[Claims] 1. A first operation mode in which a first memory address space can be accessed, and a second operation in which the first memory address space and a second memory address space located at an address higher than the first memory address space can be accessed. And a system ROM storing a system program for hardware control, wherein the system program comprises: a first program operable in the first operation mode; And a second program operable in the second operation mode, wherein the first program is arranged in the first memory address space, and the second program is arranged in the second memory address space. A computer system comprising: means for arranging a computer. 2. The first program includes a driver program group describing a procedure of a hardware access process to be executed in response to a request from an operating system or an application program, and the second program is executed by the computer system. 2. The computer system according to claim 1, further comprising an initialization program describing a procedure of hardware initialization and a test process to be executed after power-on until an operating system is started. 3. The computer system according to claim 2, wherein the second program further includes an extension program for extending a function of the first program. 4. The computer system according to claim 3, wherein the extension program is called directly from the operating system or via the first program allocated in the first memory address space. . 5. The initialization program switches an operation mode of the CPU from the first operation mode to a second operation mode when the computer system is powered on,
3. The computer system according to claim 2, wherein a main memory of the computer system arranged over the first and second memory address spaces accessible in the second operation mode is initialized. 6. The system according to claim 1, further comprising: a memory address conversion unit configured to convert a value of a memory address from the CPU into a RAM address for accessing a RAM used as a main memory of the computer system. The first and second programs stored in the system ROM are copied to a predetermined area on a RAM used as a main memory of the computer system, and the area on the RAM where the second program is copied is copied to the RAM. 2. The computer system according to claim 1, wherein the memory system is rearranged in a part of the second memory address space using a memory address conversion unit. 7. A first operation mode in which a first memory address space can be accessed, and a second operation in which the first memory address space and a second memory address space located at an address higher than the first memory address space can be accessed. And a system ROM storing a system program for hardware control, wherein the system program is activated after the computer system is powered on. And an initialization program that describes the procedure of hardware initialization and test processing to be executed by the
A start-up control method used in a computer system configured to be operable in an operation mode, comprising: switching an operation mode of the CPU from the first mode to the second mode when powering on the computer system; Using the initialization program operable in the second operation mode, initializing a main memory of the computer system arranged over the first and second memory address spaces accessible in the second operation mode. A start-up control method. 8. A driver program group further comprising a system program operable in the first operation mode and describing a procedure of hardware access processing to be executed in response to a request from an operating system or an application program. And an extension program configured to operate in the second operation mode for extending a function provided by the driver program group, wherein the driver program group is arranged in the first memory address space. 8. The start-up control method according to claim 7, wherein an operating system is started after arranging the second program in the second memory address space.