JPH10294526A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for easily manufacturing a diffusion inhibition layer so as to prevent the decrease in current constriction effect, etc., due to the diffusion of a dopant, represented by the mutual diffusion of Zn and Fe, when a mesa striped part is buried. SOLUTION: On a semiconductor substrate 1, semiconductor lasers 2 and 3 are laminated and machined in a mesa shape and before its surface and flank are buried in the semiconductor layer 5, an area 6 for inhibiting diffusion is formed on the mesa surface and flank. The diffusion of doped impurities is suppressed among the semiconductor substrate 1, semiconductor layers 2 and 3, and semiconductor layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device comprising a III-V compound semiconductor.

[0002]

2. Description of the Related Art Optical semiconductor devices such as semiconductor lasers support the development of optical communication technology. In such semiconductor devices, to improve performance such as power consumption reduction,
The mainstream structure is such that the functional portion is processed into a mesa stripe shape and the periphery thereof is buried with a resin such as a semiconductor or polyimide to perform current confinement. For embedding, a method using a semiconductor having a lattice constant close to that of the mesa stripe portion is generally used. For example, FIG. 2 is a cross-sectional view of a structure in which a mesa stripe portion obtained by processing the active layer 20 and the clad layer 30 on the semiconductor substrate 10 is embedded in the semiconductor layer 50. The semiconductor layer 50 can be easily manufactured by using a high-resistance semi-insulating semiconductor, for example.

[0003]

However, embedding with such a semiconductor causes the following problems. For example, to make the semiconductor layer 50 a semi-insulating semiconductor, the semiconductor layer 50 is doped with an element such as Fe (iron) or Ti (titanium). As shown in FIG. 2, the semiconductor layer 50 is in contact with the semiconductor substrate 10 and the cladding layer 30, and the substrate 10 and the cladding layer 30 are usually p-type or n-type semiconductor layers. The conductivity type differs between the active layers 20. When the substrate 10 is p-type, the cladding layer 30 is n-type, and when the substrate 10 is n-type, the cladding layer 30 is p-type. Here, Zn (zinc) is mainly used as the p-type dopant, but this Zn has a drawback that it is easily diffused in a semiconductor. For this reason, Zn diffuses into a portion of the semiconductor layer 50 that is in contact with the p-type semiconductor, causing a problem that the resistivity of the semiconductor layer 50 is reduced and the current confinement effect is reduced.
This problem is particularly remarkable when the semiconductor layer 50 is doped with Fe, and so-called interdiffusion occurs in which Zn diffuses into the semiconductor layer 50 and Fe simultaneously diffuses into the p-type semiconductor layer.

The present invention provides a method for simply forming a diffusion suppressing layer in order to prevent the current confinement effect from being reduced due to the diffusion of a dopant at the time of embedding a mesa stripe, such as the interdiffusion of Zn and Fe. The purpose is to provide.

[0005]

In order to achieve the above object, according to the present invention, when a mesa stripe portion is buried with a semiconductor burying layer, the surface of the mesa stripe portion is immediately placed in a V-group source gas atmosphere immediately before the embedding. By exposure, a diffusion suppressing layer was formed on the surface of the mesa stripe portion.

That is, a method of manufacturing a semiconductor device according to the present invention comprises the steps of preparing a substrate, forming a semiconductor substrate by growing a group III-V compound semiconductor material on the substrate, and forming a semiconductor substrate on the surface of the semiconductor substrate. A step of forming a step, a step of disposing the semiconductor substrate in a gas atmosphere containing a group V element as a main component, and forming a region where the group V element contained in the gas permeates the surface of the semiconductor substrate; III-V on the surface of
Crystal growing a semiconductor layer made of a group III compound semiconductor. As the substrate, either a semiconductor substrate having n-type conductivity or p-type conductivity can be used. For example, an InP substrate may be used as the semiconductor substrate. As group V elements contained in the gas, As
(Arsenic) or P (phosphorus) is desirable. As the semiconductor layer, a high-resistance InP layer doped with Fe (iron) is preferably used.

Further, in the method of manufacturing a semiconductor device according to the present invention, the step of forming a region into which the group V element supplied from the gas has penetrated into the surface of the semiconductor substrate and the step of crystal-growing a semiconductor layer on the surface of the semiconductor substrate are described. May be performed successively in one growth apparatus. At this time, the step of forming a region in which the group V element supplied from the gas has penetrated the surface of the semiconductor substrate includes disposing the semiconductor substrate in a gas atmosphere while heating the semiconductor substrate to a temperature near a temperature at which the semiconductor layer grows. You may.

By manufacturing a semiconductor laser device or an optical integrated device by the above-described manufacturing method, the performance of any device can be improved as compared with the conventional device.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention shown in FIG.
An undoped active layer 2 and Zn-doped p
After growing the InP cladding layer 3, this is processed into a mesa stripe shape. In addition, metal organic chemical vapor deposition (MOV)
A mesa side surface is exposed to a gas containing AsH ₃ at a high temperature of about 600 ° C. immediately before the Fe-doped semi-insulating InP layer 5 is grown by the PE method to bury the mesa side surface.
In this step, the substrate processed into a mesa stripe is MOV
In the step of disposing the mesa stripe in a PE furnace and raising the temperature to about 600 ° C., which is the growth temperature of Fe-doped InP, the mesa stripe may be exposed to a gas containing AsH ₃ gas. AsH
₃ After shutting off the gas, the Fe-doped InP layer 5
Can grow.

[0010] Thus, AsH at a high temperature of about 600 ° C.
Exposure to a gas containing ₃ allows As to permeate the surface of the mesa stripe. As is replaced by P, InP
In the crystal lattice (hereinafter referred to as lattice). By closing the gaps between the lattices, diffusion of the dopant existing between the lattices can be suppressed.

[0011] When doped with Zn, it usually enters gaps between lattices. Therefore, when the Fe-doped InP layer 5 is grown after being exposed to a gas containing AsH ₃ ,
Zn diffusion from InP cladding layer 3 to InP layer 5 and I
Fe diffusion from the nP layer 5 to the cladding layer 3 is suppressed by the As permeation region 6 formed on the exposed surface of the cladding layer 3. Substrate 1 is Zn-doped p-type and cladding layer 3 is n-type
The same effect can be obtained in the case of a mold. That is, since the As-penetrated region 6 is formed on the exposed surface of the substrate 1,
Zn diffusion from the substrate 1 to the InP layer 5 is suppressed. A
P may be permeated instead of s. P is the cladding layer 3
Element, but enters into the interstitial space by excessive penetration.

The element to be penetrated is preferably an element which does not affect the conductivity of the semiconductor to be penetrated. Therefore, for example, Si is not suitable, but Ti (titanium) and Ga (gallium) are effective. However, it is necessary to use a technique such as ion implantation to infiltrate these elements between lattices. In contrast, the group V elements As and P are:
Since it can be easily penetrated using the source gas used for crystal growth, it can be penetrated immediately before the growth in the growth furnace when the buried growth of the mesa side surface is performed.

By forming the diffusion suppressing layer by such a simple method, the diffusion of the dopant is significantly reduced as compared with the conventional structure having no diffusion suppressing layer as shown in FIG. The characteristics of a device manufactured using the buried structure can be greatly improved.

As is apparent from the above description, the essential feature of the present invention is that the semiconductor substrate along the bonding interface between the semiconductor substrate and the semiconductor layer contains V contained in the gas (supplied from the gas). Forming a region containing a group III element. The semiconductor substrate desirably has a crystal structure such as a zinc blende type or a wurtzite type, and may have a structure in which a plurality of semiconductors having different compositions are stacked. In addition, the semiconductor substrate and the semiconductor layer need not be processed into a mesa, that is, a stepped shape.

(Embodiment 1) An embodiment of the present invention will now be described with reference to FIG.
A case of manufacturing an InP-based semiconductor laser will be described with reference to FIGS.

An n-InP layer 11a (thickness: 0.3 μm), an undoped multiple quantum well (MQW) active layer 21, and a p-InP layer 31 are formed on the n-type InP substrate 11 by MOVPE.
(A thickness of 2.0 μm) and ap ⁺ -InGaAs layer 41 (a thickness of 0.2 μm) were grown (FIG. 3A). The growth temperatures were all 600 ° C., and the p-type dopant was Zn. The MQW active layer 21 is formed by sandwiching five InGaAs well layers (thickness: 60 nm) with six InGaAsP barrier layers (thickness: 100 nm, emission wavelength: 1.15 μm). After the growth, a SiO ₂ stripe 91 (thickness 0.5) is formed on the entire surface.
.mu.m, width 1.5 .mu.m) (FIG. 3B). Using this stripe 91 as a mask, the growth layer is formed to a depth of about 3 μm.
To form a mesa stripe structure (FIG. 4A). The etching depth is set for the purpose of etching deeper than the MQW active layer 21. The etching was performed by exciting a mixed gas of methane, hydrogen and oxygen with an RF output of 100 W using a parallel plate type plasma etching apparatus.

Thereafter, the polymer produced during the dry etching is removed by oxygen plasma, and the polymer is further washed with acetone. The exposed surface of the mesa stripe is etched very thinly with sulfuric acid, dried and carried into a MOVPE furnace.
The pressure inside the furnace is reduced to about 70 torr, and the temperature is raised to 600 ° C. while flowing hydrogen and PH ₃ gas. Here, the supply of the PH ₃ gas is temporarily stopped, and instead, AsH ₃ (70%) + PH
₃ Flow the mixed gas (30%) and leave for 3 minutes. Thereafter, the supply of the mixed gas is shut off and the gas line is purged.
After introducing H ₃ gas first, TMIn (trimethylindium), Fe (C ₅ H ₅ ) ₂ (ferrocene) and CH ₃ C
1 (methyl chloride) to introduce Fe-doped semi-insulating In
A P current blocking layer 51 (growth thickness 3.0 μm) was grown (FIG. 4B). Since a compound semiconductor such as InP does not grow on the surface of the SiO ₂ stripe 91, the exposed surface of the mesa stripe is selectively buried by the InP layer 51. However, an amorphous or polycrystalline semiconductor may be deposited on the SiO ₂ stripe 91, but such deposition is suppressed by adding a small amount of CH ₃ Cl as in this embodiment, and the buried surface is flattened. Can be

After completion of the crystal growth, an SiO ₂ stripe 91 is formed.
Is removed with a diluted solution of hydrofluoric acid, a p-type electrode (not shown) is formed on the p ⁺ -InGaAs layer 41, and the n-type InP substrate 11 is thinned by polishing, and an n-type electrode (not shown) is formed on the back surface thereof. It was formed, divided and cleaved to produce a long wavelength band semiconductor laser having an emission wavelength of about 1.55 μm.

According to this embodiment, by exposing the mesa surface to a mixed gas containing As as a main component, an As-penetrated region 61 is formed on the mesa surface as shown in FIG. When the Fe-doped InP layer 51 is grown, the As-penetrated region 61 serves as the p-InP layer 31 and the p ⁺ -InGaAs layer 4.
1 prevents Zn and Fe in 1 from interdiffusion. Therefore, in this embodiment, with the reduction of the mutual diffusion, the manufactured laser was improved in terms of parasitic capacitance, response characteristics, and the like, as compared with the laser manufactured by the conventional method.

In this embodiment, the case where a semiconductor laser is manufactured on the n-InP layer 11 is shown. However, the type of device is not limited to this, and the present invention can be applied to a modulator or the like. The present invention can also be applied to the fabrication of a short wavelength band semiconductor laser on a substrate. The mesa structure may be formed by wet etching using a liquid in addition to the structure shown in this embodiment. Further, the method of infiltrating As is not limited to the present embodiment,
A instead of PH ₃ gas, for example when 600 ° C. MadeNoboru temperature
The sH ₃ gas may be allowed to flow and permeate. Alternatively, by supplying only the PH ₃ gas at a high concentration instead of the mixed gas, a P penetration region may be formed to suppress the interdiffusion. The elements targeted for diffusion suppression are Zn and Fe, and B
e (beryllium) or Se (selenium) may be used. The method of this embodiment can be applied not only to the production of a single element but also to the production of an integrated element, and can also be applied to embedding a circular mesa.

(Embodiment 2) Another embodiment of the present invention is shown in FIG.
A case of manufacturing an InP-based semiconductor laser will be described with reference to FIGS.

The p-InP layer 12a (thickness: 0.3 μm), the undoped multiple quantum well (MQW) active layer 22, and the n-InP layer 32 are formed on the p-type InP substrate 12 by MOVPE.
(A thickness of 1.5 μm) and an n ⁺ -InGaAsP layer 42 (a thickness of 0.2 μm) were grown (FIG. 5A). The growth temperatures were all set at 600 ° C. The MQW active layer 22 is made of InGaAs
A P-well layer (thickness: 40 nm, emission wavelength: 1.35 μm) is sandwiched by six InGaAsP barrier layers (thickness: 100 nm, emission wavelength: 1.15 μm). After the growth is completed, an SiO ₂ stripe 92 (thickness 0.5) is formed on the entire surface.
.mu.m, width 1.0 .mu.m) (FIG. 5B). Using this stripe as a mask, the growth layer is etched to a depth of about 2 μm to form a mesa stripe structure (FIG. 6).
(A)). The etching was performed by dry etching as in Example 1.

Thereafter, the surface of the mesa stripe was cleaned and carried into the MOVPE furnace in the same manner as in Example 1, and a mixed gas of AsH ₃ (90%) + PH ₃ (10%) was supplied at 600 ° C. 62 is formed. Subsequently, a Fe-doped semi-insulating InP current blocking layer 52 (growth thickness: 2.0 μm) was grown in the same manner as in Example 1 (FIG. 6B). After the growth is completed, the SiO ₂ stripes 92 are removed with a hydrofluoric acid diluent,
An n-type electrode (not shown) is formed on the n ⁺ -InGaAsP layer 42, and the p-type InP substrate 12 is thinned by polishing, and then an n-type electrode (not shown) is formed on the back surface of the substrate 12. A long wavelength semiconductor laser having a wavelength of about 1.3 μm was manufactured.

In the present embodiment, the As-penetrated region 62 is effective for suppressing the mutual diffusion between Zn in the p-type InP substrate 12 and the p-InP layer 12a and Fe in the InP current blocking layer 52. Therefore, similarly to the first embodiment, the effect of improving the laser characteristics as compared with the related art can be obtained.

[0025]

As described above, the present invention can suppress unintended diffusion of impurities in a semiconductor by a simple method. Therefore, the characteristics of the semiconductor device can be improved as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view of a conventional semiconductor device.

FIG. 3 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing step of a semiconductor device according to another embodiment of the present invention.

FIG. 5 is a sectional view showing a manufacturing step of a semiconductor device according to another embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing step of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

1, 11 ... n-type InP substrate, 2 ... undoped active layer, 3
... p-InP cladding layer, 5 ... Fe-doped semi-insulating In
P layer, 6, 61, 62 ... As penetration region, 10 ... semiconductor substrate, 11a ... n-InP layer, 12 ... p-type InP substrate, 1
2a p-InP layer, 20 active layer, 21, 22 undoped multiple quantum well (MQW) active layer, 30 cladding layer, 31 p-InP layer, 32 n-InP layer, 41
p ⁺ -InGaAs layer, 42... n ⁺ -InGaAsP
Layers, 50: semiconductor layers, 51, 52: Fe-doped semi-insulating InP current blocking layers, 91, 92: SiO ₂ stripes.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tomonobu Tsuchiya 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Inside the Central Research Laboratory

Claims (12)

[Claims] A step of preparing a semiconductor substrate made of a group III-V compound semiconductor; a step of forming a semiconductor base on which a semiconductor layer made of a group III-V compound semiconductor is crystal-grown on the semiconductor substrate; Forming a step on the surface of the semiconductor substrate; and arranging the semiconductor substrate in a gas atmosphere containing a group V element as a main component to form a region where the group V element permeates the surface of the semiconductor substrate. Crystal growing a semiconductor layer made of a group III-V compound semiconductor on the surface of the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor substrate has n-type conductivity. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor substrate has p-type conductivity. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said group V element is As (arsenic). 5. The method of manufacturing a semiconductor device according to claim 1, wherein said group V element is P (phosphorus). 6. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor substrate is an InP substrate. 7. The semiconductor device according to claim 1, wherein the semiconductor layer formed after forming the region into which the group V element has penetrated is formed of a high-resistance I-doped with Fe (iron).
A method for manufacturing a semiconductor device, wherein the method is an nP layer. 8. The method for manufacturing a semiconductor device according to claim 1, wherein a step of forming a region in which the group V element has penetrated into the surface of the semiconductor substrate, and a group III-V compound formed on the surface of the semiconductor substrate. The step of crystal growing the semiconductor layer includes:
A method for manufacturing a semiconductor device, wherein the method is performed successively in one growth apparatus. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming a region in which the group V element has penetrated into the surface of the semiconductor substrate includes the step of forming the semiconductor substrate later. A method for manufacturing a semiconductor device, comprising: placing a semiconductor layer in a gas atmosphere containing a group V element as a main component while heating the semiconductor layer to a temperature near a temperature at which crystal growth occurs. 10. A method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor device is a semiconductor laser device. 11. A method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor device is a semi-integrated element. 12. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.