JPH10294652A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] For both upward noise and downward noise, it is possible to remove noise with an optimal delay amount, and it is excellent in reliability and also for process variations. Provided is a stable input signal noise elimination circuit for a semiconductor integrated circuit. SOLUTION: A downward noise absorbing circuit and an upward noise absorbing circuit are independently provided, and both are inputted to a waveform shaping circuit. The waveform shaping circuit outputs an output according to the logic when the two logically match, and sets the output to a high impedance when the two logically do not match. When the output has a high impedance, the level is held by the latch circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a method for removing upward noise and downward noise externally applied to an input terminal of a semiconductor integrated circuit so as to prevent the noise from being transmitted to an internal circuit. It relates to a removal circuit.

[0002]

2. Description of the Related Art In some cases, a pulse having a very short width is input from the outside to an input terminal of a semiconductor integrated circuit as noise, causing a malfunction. In order to avoid this problem, a noise elimination circuit is used to prevent a very short pulse applied to the input terminal from being transmitted to the internal circuit.

[0003] This type of noise elimination circuit is provided with a delay element for delaying an input signal, and only when the input signal and the delayed signal logically coincide with each other, a high-level or low-level signal corresponding to the input signal is provided. An output signal is output, the output is set to a high impedance state while the two signals do not match, and the latch circuit holds the previous state. With this configuration, even if a short-time pulse shorter than the delay time of the delay element is input, the output only temporarily goes into the high impedance state, and no level change occurs. Therefore,
The short-time noise pulse on the input signal is not transmitted to the internal circuit, which means that the noise has been removed.

In a conventional noise elimination circuit, there is only one circuit for delaying an input signal.
It has been common practice to remove noise using this one-system delay circuit.

However, a delay circuit for removing upward noise and a delay circuit for removing downward noise may be separately provided. JP-A-6-21
No. 6723 discloses such an example.

Hereinafter, a semiconductor integrated circuit using such a conventional noise removing circuit will be described with reference to FIG. In the figure, A is an external input terminal, 11 is a noise removal circuit,
12 is a latch circuit, and 13 is an internal circuit. Where e,
f, g, h, i, j are internal nodes of the noise elimination circuit 11, IV5 is a CMOS inverter circuit for inverting and transmitting the level of the signal from the input terminal, and P3 is a p-channel MOS to which the internal node e is input. Type transistor, C
Reference numeral 2 denotes a capacitor which is connected in series between the power supply and the internal node e. N3 is an n-channel MOS transistor to which the internal node e is input, and C3 is a capacitor, which is connected in series between the ground power supply and the internal node e and inserted. P4 and P5 are p-channel MOs connected and inserted in series between the power supply and the internal node i.
An S-type transistor, P4 has an internal node g
5, an internal node h is input. N4 and N5 are n-channel MOS transistors connected in series and inserted between the ground power supply and the internal node i. The internal node f is input to N4 and the internal node h is input to N5.
Here, the p-channel MOS transistors P4 and P5 and the n-channel MOS transistors N4 and N5 constitute a waveform shaping circuit. IV6 and IV7 are COMS
An inverter IV7 is a CMOS inverter IV6
Is connected between the output node j and the input node i.

The semiconductor integrated circuit configured as described above will be described with reference to FIGS. 3 and 4.

FIG. 4 shows operation waveforms of main signals in the circuit of FIG. In the period of T1, the internal node e becomes "
In this case, the p-channel MOS transistor P3 is in a non-conductive state, the n-channel MOS transistor N3 is in a conductive state, and the internal node g is at an "L" level. C
2, the internal node f becomes “H” level. On the other hand, the n-channel M input by the internal node f
The OS-type transistor N4 is turned on, and the internal node g
Is input, and the internal node h, which is the output terminal of the CMOS inverter IV5, is at "L" level. Therefore, the p-channel MOS transistor P5 input to the internal node h is conductive. State, n-channel MOS transistor N
5 is in a non-conductive state, the internal node i attains an “H” level and is transmitted to the internal circuit 13.

The period T2 shows the case where the internal node e has transitioned from the "H" level to the "L" level. In this case, the internal node f is lowered to the “L” level due to the capacitive coupling effect of the capacitors C2 and C3. Further, the internal node g is driven to a potential lower than the ground potential.
Although the voltage is excessively boosted for a moment, a current flows from GND through the n-channel MOS transistor N3.
−Vtn (Vtn is the threshold voltage of the n-channel MOS transistor N3). At this time, the n-channel MOS transistor N4 input to the internal node f is turned off, and the p-channel MOS transistor P4 input to the internal node g is turned on. Further, since the potential of the output node h of the CMOS inverter IV5 transits to the “H” level, the p-channel M
Since the OS transistor P4 is turned off and the n-channel MOS transistor N4 is turned on,
Although the output node i enters the high impedance state, the state (“H”) up to that time is held by the latch circuit 12 in the next stage.

If the "L" state of the internal node e continues for a while, the capacitor C2 is charged via the p-channel MOS transistor P3 as indicated by the period T3, so that the potential of the internal node f becomes "H". When the voltage approaches the level and exceeds the threshold voltage of the next-stage n-channel MOS transistor N4, the n-channel MOS transistor N4 is turned on, and the potential of the internal node i becomes "L" level. That is, a signal that changes from “H” to “L” is transmitted to the internal circuit 13 later than the change of the internal node e. At this time, the voltage between the terminals of the capacitor C2 is Vdd-GND, the internal node f keeps the "H" level, and the charge of the capacitor C3 keeps the internal node g at the "L" level.

T4 is "L" → "H" → "internal node e.
A case where a level change of L ”(ie, upward noise) occurs is shown. First, when the level changes from“ L ”to“ H ”, the capacitance coupling effect of the capacitors C2 and C3 causes
Internal node g is raised to "H" level. The internal node f is momentarily boosted to a potential level higher than Vdd, but a current flows out to Vdd via the p-channel MOS transistor P3, so that Vdd + Vtp (p
(Threshold voltage of channel MOS transistor P3)
Becomes At this time, the p-channel MOS transistor P
4 is a non-conductive state, an n-channel MOS transistor N
4 is conductive. Also, since the internal node h becomes “L”, the p-channel MOS transistor P5 becomes conductive, the n-channel MOS transistor N5 becomes non-conductive, and the internal node i becomes high impedance. The previous potential state ("
L ").

At this time, the internal node g approaches the "L" level due to the ON resistance of the n-channel MOS transistor N3 and the time constant of the capacitor C3, and exceeds the threshold voltage of the p-channel MOS transistor P4. The conduction state is established, and the internal node i changes from “L” to “H”. However, if the time constant of the n-channel MOS transistor N3 and the capacitor C3 is set to be longer than the potential change width of the upward noise, the potential of the internal node g causes the p-channel MOS transistor P4 to become conductive before the potential of the internal node g turns on. The upward noise changes from “H” to “L” again, and the internal node i does not change.

When the upward noise changes from "H" to "L", the internal node h changes from "L" to "H". At this time, the voltage between the terminals of the capacitor C2 is about Vtp, and the internal node f approaches the “L” level. As a result, the internal node i becomes a high impedance state again,
The potential of the internal node i can be held at the “L” level by the latch circuit 12.

T5 is a case where the "L" period of the internal node e is sufficiently long. The internal node f is charged via the p-channel MOS transistor P3, and is set at the "H" level (Vd
d), the n-channel MOS transistor N4 to which the internal node f is input becomes conductive, and the internal node g holds the "L" level.
Is input to the p-channel MOS transistor P4
Becomes conductive. Since internal node h is at "H" level, n-channel MOS transistor N5 is conductive, and internal node i is at "L" level.

T6 is a case where the internal node e transitions from "L" to "H". At this time, the capacitors C2 and C
3, the internal node f is boosted to the "H" level (Vdd + Vtp), and the n-channel MOS
Type transistor N4 is conductive, and internal node g is "H".
Level, and the p-channel MOS transistor P4 is turned off. The internal node h is "
Since the signal changes from H "to" L ", the n-channel MOS transistor N5 is turned off, and the p-channel MOS transistor P5 is turned on. 1
2 holds the previous potential state (“L”).

The "H" period of the internal node e is sufficiently long (T
7 period), the n-channel MOS transistor N3
Is in a conducting state, the potential of the internal node g approaches the "L" level due to the time constant, and when the threshold voltage of the p-channel MOS transistor P4 is exceeded, the p-channel MOS transistor P4 Is turned on, and internal node i transitions to "H" level. That is, a signal that changes from “L” to “H” after the transition of the internal node e from “L” to “H” is transmitted to the internal circuit.

T8 changes the internal node e from "H" → "L" → "
This shows a case where a potential change (downward noise) of H occurs. First, when the potential changes from "H" to "L", the internal node f is set to "L" due to the capacitive coupling effect of the capacitors C2 and C3. Reduced to level, n channel M
OS-type transistor N4 is turned off, and internal node g attains an "L" level (GND-Vtn).
The channel MOS transistor P4 is turned on. Further, since the internal node h changes from “L” to “H”, the n-channel MOS transistor N5 is turned on and the p-channel MOS transistor P5 is turned off. As a result, the internal node i enters a high impedance state, and the latch circuit holds the “H” level.

At this time, due to the on-resistance of the p-channel MOS transistor P3 and the time constant of the capacitor C2, the internal node f approaches the "H" level and exceeds the threshold value of the n-channel MOS transistor N4. The conduction state is established, and the internal node i changes from “H” to “L”. However, if the time constants of the p-channel MOS transistor P3 and the capacitor C2 are set to be longer than the potential change width of the downward noise, the potential of the internal node f causes the n-channel MOS transistor N4 to become conductive before the potential changes. The downward noise changes from “L” to “H” again, and the internal node i does not change.

When the downward noise changes from "L" to "H", the internal node h changes from "H" to "L" and the internal node g changes from "L" to "H". Node i again enters the high impedance state, and latch circuit 1
2, the potential of the internal node i can be held at the “H” level.

[0020]

In the case of the example of FIG. 3 described above, the delay amount of the delay circuit for removing upward noise and the delay amount of the delay circuit for removing downward noise are, for example, capacitors. The capacitances of C2 and C3 can be adjusted independently of each other, but the internal node f and the internal node g may each be momentarily over-boosted. Can cause. Further, noise is removed by turning on the transistor inside the waveform shaping circuit by a signal delayed by the ON resistance of the transistor and the time constant of the capacitor, but the waveform shaping circuit is reduced due to the variation in the semiconductor diffusion process. If the threshold voltage of the internal transistor fluctuates, stable noise removal characteristics cannot be obtained.

In a conventional general noise elimination circuit of a semiconductor integrated circuit, a delay circuit for removing upward noise and a delay circuit for removing downward noise are commonly used. Cannot be independently adjusted to the optimum value.

[0022]

According to a first aspect of the present invention, a semiconductor integrated circuit receives a first signal, outputs a first output, and outputs the first signal to the first signal by a first delay element. A first noise absorbing means for absorbing a short-time upward noise pulse riding thereon, and a second output which is input with the first signal and is output on the second signal by a second delay element A second noise absorbing means for absorbing a short-time downward noise pulse; inputting the first output and the second output to output a third output; and outputting the first output and the second output. When the output logically coincides with the output of the second logic, a high-level output or a low-level output according to the logic of the coincidence is output as the third output, and the first output and the second output are logically identical. , The waveform shaping means for setting the third output to high impedance When the third output of the time of high impedance, characterized in that a holding means for holding the third level of the output of.

The invention described in claim 2 is the same as that in claim 1.
Wherein the first noise absorbing means is connected to a first logical delay element for delaying a first signal, and the first signal is connected to a first input terminal; A first output terminal connected to an output of the logic delay element connected to the second input terminal;
, A second noise absorbing means comprising: an inverter for generating a second signal from the first signal;
A second logic delay element for delaying the second signal, the second signal connected to a third input terminal, and an output of the second logic delay element connected to a fourth input terminal A second NAND circuit.

[0024] The invention described in claim 3 is the first invention.
Wherein the waveform shaping means includes a first p-channel MOS transistor and a second p-channel MOS transistor connected in series between a power supply and a third output.
An S transistor, a first n-channel MOS transistor and a second n-channel MOS transistor connected between a third output and a reference potential, wherein the first p-channel MOS transistor and the first A first output is input to a gate of the n-channel MOS transistor, and a second output is input to gates of the second p-channel MOS transistor and the second n-channel MOS transistor.

The invention described in claim 4 is the first invention.
Wherein the delay amount of the first delay element is adjusted to an optimal delay amount for removing upward noise,
The delay amount of the second delay element is adjusted to an optimal delay amount for removing upward noise.

The invention described in claim 5 is the first invention.
Wherein the first signal is supplied from an external input terminal via a buffer.

With the above arrangement, according to the first to fifth aspects of the present invention, the downward noise absorbing circuit and the upward noise absorbing circuit are independently provided, and both are connected to the waveform shaping circuit to reduce upward noise. On the other hand, the optimum delay amount for removing the noise can be set independently for the downward noise.

In particular, according to the second aspect of the present invention, the first signal or the second signal and the delayed signal need only differ in the time during which the signal changes, so that the delay in the noise absorbing means is reduced. A normal logic delay can be used as an element. Therefore, there is no over-boost node, high reliability, and even if the semiconductor diffusion process varies,
Stable noise removal characteristics can be obtained. Furthermore, by using a normal logic delay element, it is not necessary to connect a delay capacitor directly to the input of the noise elimination circuit, so that the input capacitance of the noise elimination circuit is reduced.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram of a noise removing circuit according to the present embodiment. In the figure, 1 is a downward noise absorbing circuit, 2 is an upward noise absorbing circuit, and 10 is an internal circuit. 3, 4, 5, 6, 7, 11, 12, and 13 are internal nodes. Although not shown, a signal input from an external input terminal is coupled to internal node 7 via an input buffer. 1a, 1b, 1d, 2a, 2b, and 2d
Is a CMOS inverter circuit, 1c and 2c are capacitors, and 1e and 2e are NAND circuits. The CMOS inverters 1b and 1d and the capacitor 1c and the CMOS inverters 2b and 2d and the capacitor 2c are respectively
A logic delay element using a normal logic delay is configured. Q1 and Q2 are p-channel MOS transistors inserted in series between the power supply and the internal node 5, and Q3 and Q4 are n-channel transistors inserted in series between the ground power supply and the internal node 5. It is a MOS transistor and constitutes a waveform shaping circuit. 8 and 9 are CM
It is an OS inverter and constitutes a latch circuit. The internal node 3, which is the output terminal of the downward noise elimination circuit 1, has p-channel MOS transistors Q1 and n
The internal node 4 which is input to the gate of the channel MOS transistor Q3 and is the output terminal of the upward noise elimination circuit 2 is connected to the p-channel MOS transistors Q2 and n
The signal is input to the gate of the channel MOS transistor Q4.

The operation of the semiconductor device configured as described above will be described with reference to FIG. FIG. 2 is an operation waveform diagram of a main signal in the embodiment of the present invention.

The period T1 shows a case where the internal node 7 is at "H" level. Internal node 11 is at the "L" level because it is the output of CMOS inverter circuit 1a.
Similarly, the internal node 12 has a CM
Since the OS inverter circuits 1b and 1d are connected in series, the level is "L" level, and the internal node 3 which is the output of the NAND circuit 1e becomes "H" level. The internal node 13 is at “H” level because the CMOS inverter circuits 2 b and 2 d are connected in series with the internal node 7, and the internal node 4 is set to “H” by the NAND circuit 2 e and the CMOS inverter circuit 2 a. "Level. At this time, the p-channel MOS transistor Q
1 and Q2 are non-conductive and n-channel MOS transistors Q3 and Q4 are conductive, so that internal node 5 is at "L" level and CMOS inverter circuit 8 causes internal node 6 to be at "H" level. Becomes

T2 indicates a case where the internal node 7 has transitioned from "H" to "L". At this time, the internal node 11 changes from "L" to "H" by the CMOS inverter 1a. Here, the internal node 12 changes from "L" to "H" later than the internal node 11 due to a logical delay caused by the CMOS inverter circuits 1b and 1d and the capacitor 1c. "
When the H level overlaps, the level changes from "H" to "L." Also, since the internal node 13 is logically delayed by the CMOS inverter circuits 2b and 2d and the capacitor 2c, it is delayed from the internal node 7 by "H". However, the internal node 4 changes from “H” almost simultaneously with the internal node 7 because the internal node 4 changes when the internal nodes 7 and 13 no longer overlap at the “H” level. "L"
Has already changed to As a result, the internal node 3
At the time of the L level, the p-channel MOS transistors Q1 and Q2 are turned on.
The internal node 5 changes from "L" to "H",
Of the internal node 6 inverted by the MOS inverter 8
The change from H ”to“ L ”is signaled to the internal circuit 10.

At T3, an upward noise pulse is input from an external input terminal, and a short-time upward noise pulse overlaps the signal of the internal node 7, and its voltage level changes from "L" to "L".
This shows a case where the voltage changes from H ”to“ L ”in a short time, and the voltage changes“ H ”,“ L ”, and“ H ”that are logically inverted by the CMOS inverter 1a are transferred to the internal node 11. The internal node 12 has the same polarity as the internal node 11,
A logically delayed voltage change occurs. Where internal node 3
Becomes "L" level only when the internal nodes 11 and 12 overlap at "H" level. That is, the internal node 11
After the voltage changes from “H” to “L”, the internal node 12
The internal node 3 can be at the “H” level until the signal changes from “L” to “H”.

Next, at this time, the upward noise absorbing circuit 2
Will be described. The internal node 13 has an internal node 7
A voltage change of “L” → “H” → “L” is transmitted later than that. If this delay time is sufficient, the internal node 7
And 13 have no period in which the “H” level overlaps,
Internal node 4 holds "L" level. in this way,
The delay amount of the logic delay element including the inverters 2a and 2b and the capacitor 2c can be adjusted according to the pulse width of the upward noise pulse to be removed, and an optimum value can be selected.

The internal nodes 3 and 4 are input to a waveform shaping circuit including p-channel MOS transistors Q1, Q2 and n-channel MOS transistors Q3, Q4. In the waveform shaping circuit, the internal nodes 3 and 4
"L" is output when they match at the "H" level, "H" is output when the internal nodes 3 and 4 match at the "L" level, and output when the levels of the internal nodes 3 and 4 are different. Are configured to be in a high impedance state.

When an upward noise pulse is input from the external input terminal and the internal node 7 changes from "L" to "H" to "L" in a short time, the internal node 7 changes from "L" to "H". The voltage changes, and at about the same time the internal node 3 changes from "L" to "L".
Even when the voltage changes to "H", the internal node 4 maintains the "L" level by the function of the upward noise absorbing circuit, at this time, the p-channel MOS transistor Q1 is turned off, and the p-channel MOS transistor Q2 Is conducting, n-channel MOS transistor Q3 is conducting, n-channel MOS transistor Q4 is non-conducting, internal node 5 is in a high impedance state, and the voltage state ("H") up to that time by the latch circuit.
Is held. Internal node 6 input to internal circuit 10
Is also maintained and does not change, which means that the upward noise generated at the internal node 7 has been removed.

At T4, the internal node 7 changes from "L" to "H".
The case where the voltage changes to is shown. At this time, the voltage of the internal node 11 changes from “H” to “L”. The voltage of the internal node 12 changes from "H" to "L" with a delay, but the voltage of the internal node 3 changes from "L" to "H" almost simultaneously with the voltage change of the internal node 7. MO
S-type transistor Q3 is rendered conductive. Further, the internal node 13 is delayed from “L” with respect to the internal node 7 by “L”.
The voltage changes to "H", the internal node 4 changes from "L" to "H" almost simultaneously with the delayed voltage change of the internal node 13, and the n-channel MOS transistor Q4 becomes conductive. , Internal node 5 attains an "L" level.

Next, a downward noise pulse is inputted from the external input terminal, and a short-time downward noise pulse overlaps with the signal of the internal node 7, and its voltage level changes from "H" to "L".
T5 indicates a case where the state changes to "H" in a short time. First, the operation of the downward noise absorbing circuit 1 will be described. Internal node 1
1, a voltage change of “L” → “H” → “L” is transmitted, and a delayed voltage change having the same polarity is transmitted to the internal node 12. At this time, if the delay amount is appropriate, there is no period in which the internal nodes 11 and 12 overlap the “H” level, and the internal node 3 holds the “H” level. As described above, the delay amount of the logic delay element including the inverters 1a and 1b and the capacitor 1c can be adjusted according to the pulse width of the downward noise pulse to be removed, and an optimum value can be selected.

At this time, the internal node 13 is
Since the voltage change from “H” → “L” → “H” is transmitted later than the internal node 4, the internal node 7
After the internal node 13 changes from “H” to “L”,
The internal node 4 may be at the "L" level until it changes from "L" to "H." When the internal node 4 goes to the "L" level, the p-channel MOS transistor Q1 is output by the waveform shaping circuit.
Is non-conductive, p-channel MOS transistor Q2
Is conductive, n-channel MOS transistor Q3 is conductive, n-channel MOS transistor Q4 is non-conductive, and internal node 5 is in a high impedance state. At this time, the state (“L”)
Level) is retained. Since the voltage of the internal node 6 input to the internal circuit 10 is also maintained and does not change, the downward noise of the internal node 7 has been removed.

As can be seen from the above description, according to the present embodiment, the delay amount of the logic delay element in the upward noise absorbing circuit is reduced for the upward noise input from the external input terminal to the internal node 7. By adjusting, an optimum delay amount can be set in relation to the pulse width of the noise pulse to be removed. For the downward noise input from the external input terminal to the internal node 7, by adjusting the delay amount of the logic delay element in the downward noise absorption circuit, the optimum delay amount can be set independently of the upward noise. Can be set.

[0042]

As described above, according to the present invention, the downward noise absorbing circuit and the upward noise absorbing circuit are independently provided, and both are connected to the waveform shaping circuit. , An optimum delay amount for noise removal can be set independently of each other.

Further, a normal logic delay can be used as a delay element in the noise absorbing means. Therefore, there is no over-boost node, high reliability, and stable even if the semiconductor diffusion process varies. Noise reduction characteristics can be obtained. Furthermore, by using a normal logic delay element, it is not necessary to connect a delay capacitor directly to the input of the noise elimination circuit, so that the input capacitance of the noise elimination circuit is reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform chart showing operation waveforms of main signals in FIG.

FIG. 3 is a circuit diagram showing an example of a conventional noise removal circuit.

FIG. 4 is a waveform chart showing operation waveforms of main signals in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Downward noise absorption circuit 1a, 1b, 1d Inverter 1c Capacitor 1e NAND circuit 2 Upward noise absorption circuit 2a, 2b, 2d Inverter 2c Capacitor 2e NAND circuit 3, 4, 5, 6, 7 Internal node Q1, Q2 P channel MOS transistor Q3, Q4 n-channel MOS transistor 8, 9 inverter 10 internal circuit

Claims (5)

[Claims] 1. A first noise absorbing means for receiving a first signal, outputting a first output, and absorbing a short upward noise pulse on the first signal by a first delay element. And inputting the first signal to output a second output;
A second noise absorbing means for absorbing a short-time downward noise pulse riding on the second signal by a second delay element, and inputting the first output and the second output to generate a third noise;
And when the first output and the second output logically match, outputs a high-level or low-level output according to the matched logic as the third output. A waveform shaping unit that sets the third output to a high impedance when the first output and the second output do not logically match each other; Holding means for holding the output level of the semiconductor integrated circuit. 2. A first noise absorbing means comprising: a first logic delay element for delaying a first signal; and a first logic delay element for delaying the first signal.
And a first NAND circuit connected to an input terminal of the first logic delay element and an output of the first logic delay element connected to a second input terminal. 2, an inverter for generating the second signal, a second logical delay element for delaying the second signal, and the second signal connected to a third input terminal, and an output of the second logical delay element 2. The semiconductor integrated circuit according to claim 1, further comprising: a second NAND circuit connected to the fourth input terminal. 3. The waveform shaping means includes: a first p-channel MOS transistor and a second p-channel MOS transistor connected in series between a power supply and a third output;
A first n-channel MOS transistor and a second n-channel M connected between a third output and a reference potential;
An OS transistor, wherein the first p-channel M
OS transistor and the first n-channel MOS
2. The device according to claim 1, wherein a first output is input to a gate of the transistor, and a second output is input to gates of the second p-channel MOS transistor and the second n-channel MOS transistor. Semiconductor integrated circuit. 4. The method according to claim 1, wherein the delay amount of the first delay element is adjusted to an optimal delay amount for removing upward noise, and the delay amount of the second delay element is adjusted to an optimal delay amount for removing upward noise. 2. The semiconductor integrated circuit according to claim 1, wherein: 5. The semiconductor integrated circuit according to claim 1, wherein the first signal is supplied from an external input terminal via a buffer.