JPH10294884A - Digitized ESPO interference jamming cancellation circuit - Google Patents

Abstract

[PROBLEMS] To reduce the size of a circuit, realize real-time signal processing, and reduce the operation speed, thereby making it easy to integrate the entire circuit into an LSI. Interference cancellation can be performed. SOLUTION: A frequency conversion / clock generation circuit 3 captures an IF signal of a specified frequency output from a TV tuner 2 receiving a broadcast wave to generate a digital IF signal, a digital local signal, and a clock signal. The digital IF signal and the digital local signal are processed by the digitized E-spot interference interference removal circuit 4 to remove the E-spot interference component contained in the digital IF signal, and the NTSC digital signal obtained by this is obtained. The video signal is D / A converted to generate a video signal in an analog signal format.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for removing ESP interference used in a television receiver or the like.
In particular, the present invention relates to a digitized ESPO interference canceling circuit for improving ESPO interference caused by interference with television broadcast waves by digital technology.

[Summary of the Invention] [0002] The present invention relates to an E-spot which improves so-called E-spot obstruction, in which foreign radio waves (mainly FM broadcast waves) arriving by reflection at the sporadic E layer cause interference in television broadcast reception. The present invention relates to an interference rejection apparatus, in which an ESPO interference rejection circuit constituting the ESP interference rejection apparatus is constituted by a logic circuit to digitize signal processing.

Accordingly, the carrier frequency of the received VSB (vestigial sideband) -AM television signal is
Inputting an IF signal converted to a frequency twice as high as the color subcarrier frequency (f _sc ), realizing a hardware configuration and a signal processing format for performing all signal processing after A / D conversion by digital signal processing. In addition to realizing excellent temperature stability and high-accuracy cancellation characteristics, which were difficult to achieve with the analog method, LSI integration was facilitated, mass production was possible, and the cost was reduced. Enable integration.

[0004]

2. Description of the Related Art At present, various methods have been developed as methods for removing E-spo interference by analog processing, such as a method using a notch filter, a method using FM feedback, and a method using orthogonal transform and Hilbert transform. Among these methods, there is a track record as an analog device, and as a method that is highly effective in principle and suitable for digitization, an E-spo interference cancellation circuit using a method based on orthogonal transform and Hilbert transform is used. Often used.

FIG. 17 is a block diagram showing an example of a basic configuration of an E-spo interference canceling circuit using a system based on such orthogonal transform and Hilbert transform.

[0006] The E-spo interference canceller 15 shown in FIG.
0 has a carrier reproduction circuit 151 and a hybrid circuit 152, and outputs a frequency-converted IF signal (f) output from a TV tuner receiving a television signal.
_v = 58.75 MHz) or an IF signal converted to a lower frequency is taken in to reproduce a carrier signal. Based on this carrier signal, a 0 degree signal and 90
, A step Nyquist filter circuit 154 that takes in an IF signal and performs preprocessing to give Nyquist characteristics, two multiplication circuits 155 and 156, and two LPF circuits 157 and 157.
58, and 0 output from the local signal circuit 153.
A quadrature synchronous detection circuit that performs quadrature synchronous detection (demodulation) on the IF signal output from the step Nyquist filter circuit 154 based on the degree signal and the 90 degree signal, and generates an in-phase output baseband signal and a quadrature output baseband signal. 159
Delay circuit 160, Hilbert transform circuit 161,
Adaptive filter circuit 162 and adder circuit 163
And a cancel circuit 164 that cancels an interference wave component and reproduces a video signal based on the in-phase output baseband signal and the quadrature output baseband signal output from the quadrature synchronous detection circuit 159.

[0007] Then, the received television signal is T
IF signal (f _v) obtained by frequency conversion with a V tuner
= 58.75 MHz), or when an IF signal converted to a lower frequency is input,
And the local signal of the 90-degree signal is reproduced, and the IF signal obtained by pre-processing the IF signal is subjected to quadrature synchronous detection (demodulation) to obtain an in-phase output baseband signal and a quadrature output baseband signal. Is generated, the quadrature output baseband signal is subjected to a Hilbert transform process and an adaptive filtering process to extract a disturbing wave component having the same amplitude and a phase difference of 180 degrees, and adding this to the in-phase output baseband signal, A video signal is generated in which the interference wave component included in the in-phase output baseband signal is canceled.

In this case, in the quadrature synchronous detection circuit 159,
As shown in FIG. 18A, when an IF signal including only the VSB-AM signal is input and preprocessed by the step Nyquist filter circuit 154 to generate the IF signal shown in FIG. 18 (c) is output from the LPF circuit 157 of the quadrature synchronous detection circuit 159.
The quadrature output baseband signal shown in FIG. 18D is output from the LPF circuit 158 of FIG.

As can be seen by comparing these waveforms, the VSB-AM signal has a DSB (double-sideband) region and an SSB (single-sideband) region. Quadrature output baseband signal (Q-axis signal)
On the side, there is a feature that the component of the DSB area does not come out.

On the other hand, as shown in FIG.
When an IF signal including only the FM signal is input and preprocessed by a step Nyquist filter circuit 154 to generate an IF signal shown in FIG. 19B, the LPF circuit 157 of the quadrature synchronous detection circuit 159 outputs FIG. 19 (c)
19 (d) is output from the LPF circuit 158 of the quadrature synchronous detection circuit 159.
Are output.

As a result, as shown in FIG. 20A, an IF signal including a VSB-AM signal and an FM signal is input, and the signal is input to a step Nyquist filter circuit 154.
When this is pre-processed and the IF signal shown in FIG. 20B is generated, the LPF circuit 1
57 outputs the in-phase output baseband signal shown in FIG.
Since the quadrature output baseband signal shown in FIG. 20D is output from 58, the component of the FM signal included in the quadrature output baseband signal is extracted, and this is extracted with equal amplitude.
Just by adding to the in-phase output baseband signal with the phase of 180 degrees, it is possible to reproduce the video signal from which the interference wave component contained in the in-phase output baseband signal has been removed.

At this time, an in-phase output baseband signal;
The quadrature output baseband signal has a phase difference of 90 degrees,
Since the difference between the phase of the interference component included in the in-phase output baseband signal and the phase of the interference component included in the quadrature output baseband signal is 90 degrees, the phase can be shifted by 90 degrees over a wide band. Using a possible Hilbert transformer 161, the phase of the interference wave component included in the quadrature output baseband signal is further shifted by 90 degrees and added to the in-phase output baseband signal.

As described above, in the E-spo interference removal circuit 150, the characteristic of the VSB-AM signal is utilized, and even if the FM signal serving as the interference signal is superimposed on the VSB-AM signal, the interference signal is eliminated. The components are separated, and the interference wave component is canceled with the interference wave component included in the in-phase output baseband signal, thereby reproducing a video signal which is not affected by the interference wave.

[0014]

In the above-described interference removal by the cancellation method, the interference wave component included in the in-phase output baseband signal and the interference wave component extracted from the quadrature output baseband signal are made equal in amplitude. Condition and the condition of reverse phase are satisfied at the same time,
The interference wave component can be completely canceled.

However, it is difficult to realize the Hilbert transform circuit 161 having good characteristics over a wide band with the conventional analog E-spo interference removal circuit 150 in the conventional analog system. Due to the temperature characteristics, there is a problem that it is difficult to realize the cancel condition with high accuracy in a wide temperature range.

For this reason, as the above-mentioned E-spot interference interference elimination circuit 150, only a professional circuit for a broadcast relay station is used.
There has been a strong demand for the development of an ESPO interference rejection circuit that has not been put to practical use and that can be incorporated into a home-use receiver.

In order to realize an E-spot interference rejection circuit that can be incorporated in a home receiver, E
It is necessary to make the SP interference canceller circuit 150 inexpensive and have a high performance, and it is essential to digitize the above-described ESPO interference canceller circuit 150 to achieve an LSI capable of mass production.

However, there is no example in which the above-mentioned E-spo interference canceller 150 is digitized, and simply digitizing a circuit realized by an analog circuit in the past is not sufficient in terms of circuit scale and operating speed. LS at the limit
The development of a method and a configuration method that can not greatly reduce the size and simplify the circuit scale is strongly desired.

According to the present invention, in view of the above circumstances, the circuit scale can be reduced, and real-time signal processing can be realized.
It is an object of the present invention to provide a digitized E-spot interference canceller which can easily perform SI and removes E-spot interference even in a home-use receiver.

[0020]

In order to achieve the above object, a digitized E-spot interference rejection circuit according to the present invention operates with a clock signal having a frequency eight times the color subcarrier frequency. Nyquist filter circuit that pre-processes a digital IF signal output from an A / D conversion circuit that performs a quadrature synchronous detection on a pre-processed digital IF signal that is output from the step Nyquist filter circuit and outputs an in-phase output baseband A quadrature synchronous detection circuit for generating a signal and a quadrature output baseband signal; an in-phase output baseband signal and a quadrature output baseband signal output from the quadrature synchronous detection circuit; , A down-sampling circuit for generating a quadrature output signal, and an output from the down-sampling circuit. Frequency / phase shift detection that corrects the frequency shift and phase shift of the in-phase output signal and the quadrature output signal to generate an I-axis output signal and a Q-axis output signal completely separated into an I-axis and a Q-axis. A Hilbert transform process and an adaptive filtering process are performed on the Q-axis side output signal output from the correction circuit and the frequency / phase shift detection correction circuit to extract an interference wave component, and using the interference wave component,
And a cancel circuit for canceling an interference wave component of the I-axis side output signal output from the frequency / phase shift detection and correction circuit.

According to a second aspect of the present invention, in the digitized E-spot interference rejection circuit of the first aspect, the carrier frequency of the digital IF signal input to the step Nyquist filter circuit is set to the color subcarrier frequency f _sc of two.
The frequency of the clock signal is eight times the frequency of the color subcarrier frequency _fsc , and the digital IF signal and the clock signal are synchronized.

According to a third aspect of the present invention, there is provided the digitized E-spot interference canceller according to the first aspect, wherein the carrier frequency of the digital IF signal and the frequency of the clock signal are set in a one-to-four relationship, and the quadrature synchronous detection is performed. The synchronous detection operation of the circuit is regarded as multiplication by a sequence of {1, 0, -1, 0} and a sequence of {0, -1, 0, 1}, and a switch circuit is driven by each of the sequences to generate the digital IF. It is characterized in that signals are subjected to quadrature synchronous detection.

According to a fourth aspect of the present invention, in the digitized E-spot interference rejection circuit according to the first aspect, the input local signal is subjected to a Hilbert transform process and a band-pass filtering process to obtain a quadrature local signal. And the local signal is delayed by a delay time corresponding to the delay amount in the Hilbert transform process and the delay amount in the band-pass filtering process to generate an in-phase local signal, and these are synchronized with the quadrature synchronization. A local signal circuit for supplying a detection circuit is provided.

According to a fifth aspect of the present invention, in the digitized E-spot interference canceller according to the first aspect, the frequency / phase shift detection and correction circuit includes an input in-phase output baseband signal and a quadrature output baseband signal. A frequency / phase shift detection circuit for performing band-limiting processing, complex limiter processing, and narrow-band processing to generate an I-axis side correction signal and a Q-axis side correction signal, and the in-phase output baseband signal and the quadrature output baseband. The signal is subjected to delay processing, phase rotation processing using the I-axis side correction signal, and the Q-axis side correction signal,
A frequency / phase shift correction circuit for generating an I-axis output signal and a Q-axis output signal in which the frequency shift and the phase shift have been corrected is provided.

According to a sixth aspect of the present invention, in the digitized E-spot interference canceller according to the fifth aspect, the complex limiter circuit for performing the complex limiter processing includes a band-limited in-phase output baseband signal and a band-limited. An absolute value circuit for obtaining an absolute value of the quadrature output baseband signal, a comparing circuit for comparing each absolute value output from the absolute value circuit,
A function generating circuit that generates a function signal corresponding to each absolute value based on a comparison result of the comparing circuit, and a function signal output from the function generating circuit is used to divide a larger one of the absolute values. A dividing circuit for obtaining a coefficient for keeping the vector length of the sum of squares of the two orthogonal signals constant; and a coefficient obtained by the dividing circuit, the in-phase output baseband signal, and the quadrature output baseband signal. And a multiplication circuit for multiplying to obtain an I-axis side correction signal and a Q-axis side correction signal.

According to a seventh aspect of the present invention, in the digitized E-spot interference cancellation circuit, a TV tuner is used as an analog circuit for synchronizing a video carrier of an input IF signal with the clock signal. A reference signal reproducing circuit for retrieving a reference frequency signal by taking in the output signal of the reference signal, a clock PLL circuit for generating a clock signal based on the reference frequency signal output from the reference signal reproducing circuit, and a clock signal output from the clock PLL circuit. And a synchronizing frequency conversion circuit for converting the frequency of the IF signal in synchronization with the clock signal.

According to an eighth aspect of the present invention, in the digitized E-spot interference canceller according to the seventh aspect, the reference signal reproducing circuit detects an envelope (envelope) of the video carrier of the IF signal and performs baseband detection. An envelope detection circuit for generating a signal, and a baseband signal output from the envelope detection circuit are subjected to a low-pass filtering process with a cut-off frequency of about 200 kHz, a sync separation process, and an equivalent pulse removal process to remove a television signal. A color subcarrier band-pass filtering process and a burst lock PLL process are performed on the baseband signal output from the horizontal frequency signal reproduction circuit for reproducing the horizontal frequency (f _h ) and the envelope detection circuit to obtain the color subcarrier frequency. (F _sc ) reproduction color subcarrier circumference A wave number signal reproducing circuit, and supplies either the horizontal frequency signal obtained by the horizontal frequency signal reproducing circuit or the color subcarrier frequency signal obtained by the color subcarrier frequency signal reproducing circuit to the clock PLL circuit. It is characterized by:

According to a ninth aspect of the present invention, in the digitized E-spot interference canceller according to the seventh aspect, the synchronization frequency conversion circuit converts the output signal of the TV tuner to
A carrier reproducing circuit for performing a narrow band band-pass filtering process, a comparator process, and a band-pass filtering process to generate a carrier signal; a carrier signal output from the carrier reproducing circuit and a color subcarrier output from the clock PLL circuit; Frequency f of frequency signal
_A mixed signal is generated by mixing a local signal having twice the frequency with the _sc as a reference, and a band-pass filtering process is performed on the mixed signal to extract a sum frequency component, and the mixed signal has a required frequency. A synchronization signal converting main circuit for generating a local signal, converting the frequency of the output signal of the TV tuner using the local signal, and obtaining a VSB-AM modulated wave of a video carrier having a desired frequency. Features.

According to a tenth aspect of the present invention, in the digitized E-spot interference canceller according to the first aspect, the frequency / phase shift detection and correction circuit includes an input in-phase output baseband signal and a quadrature output baseband signal. On the other hand, a down-sampling circuit is provided between a band-limiting filter circuit that performs band-limiting processing and a complex limiter circuit that performs complex-limiter processing, and the in-phase output baseband signal and the quadrature output baseband signal subjected to the band-limiting processing are provided. Down-sampled and supplied to the complex limiter circuit, and after the narrow-band filter circuit that performs narrow-band filtering on the I-axis correction signal and the Q-axis correction signal output from the complex limiter circuit, Providing a sample circuit, the I-axis side correction signal narrow band by the narrow band filter circuit,
It is characterized in that the clock frequency of the Q-axis side correction signal is restored.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION

<< Explanation of Design Criteria >> In order to realize the digital signal processing unit that constitutes the E-spot interference canceller,
First, design criteria for stable operation and real-time signal processing are determined, and then design criteria for further simplification of the circuit and downsizing of the circuit are determined and assumed. The entire circuit can now be incorporated into a 300,000 gate class LSI.

<First Design Criteria> First, regarding a frequency relationship, since a modulated signal having a bandwidth of about 6 MHz is handled, an interval between the baseband signal and a band which does not cause an overlap does not occur.
Set to F frequency.

The frequency of a clock signal required for digital signal processing is set to a frequency that falls within the operating frequency of an A / D converter used.

The circuit configuration is simple and the performance is good,
In addition, the circuit scale is reduced.

[0034] New image quality degradation due to digital signal processing is reduced.

The relationship that simultaneously satisfies these four conditions is that the video carrier frequency (f _v ) of the IF signal is twice the color subcarrier frequency (f _sc ), and the frequency of the clock signal required for digital signal processing. (F _ck ) is made eight times the color subcarrier frequency (f _sc ).

<Second Design Criteria> Also, by using a clock signal satisfying the frequency relationship of the first design criterion and an IF signal, the in-phase local: 1, 0 is used as a local signal of the quadrature synchronous detection circuit. , -1, 0 Quadrature local: A method using a switch operation of multiplying a sequence of 0, -1, 0, 1 by a method capable of ensuring orthogonality of synchronous detection in principle.

<Third Design Criteria> In order to make the cancellation condition of the cancellation circuit closer to the ideal state, a frequency / phase shift detection and correction circuit is provided, and the in-phase output baseband signal output from the quadrature synchronous detection circuit and the quadrature output are output. A frequency shift and a phase shift are detected based on the baseband signal, and the amount of the shift obtained by these detection operations is directly added as a correction amount to a phase rotation circuit (complex conjugate resolver), and the shift amount is calculated. Is eliminated by signal processing. The amplitude is designed so that the amplitude deviation characteristic of the adaptive filter circuit with the Hilbert transform characteristic is suppressed to 0.01 dB or less.

<Fourth Design Criteria> Further, by providing a complex limiter circuit in the frequency / phase shift detection and correction circuit, the envelope of the complex vector is made constant based on the in-phase output baseband signal and the quadrature output baseband signal. A method and configuration for accurately detecting the amount of frequency shift or phase shift by removing the modulation component and realizing a further reduction in circuit scale are realized.

<Fifth Design Criteria> In addition, a synchronization frequency conversion circuit for generating an IF signal having a synchronization relationship with a clock signal is provided at a stage preceding the A / D conversion processing, and a frequency conversion circuit is provided for converting a frequency from an output signal of the TV tuner. as a method of generating use local signals, a color sub-carrier signal from an output signal reproduced by envelope detection of the tuner (f _sc) or to the horizontal frequency (f _h) is generated as a reference signal 8f
A 1/4 frequency-divided signal obtained by dividing a clock signal having a frequency of _sc and a carrier signal of a video carrier frequency (f _v = 58.75 MHZ) reproduced from an output signal of the tuner are mixed and extracted. The method of generating as a local signal is adopted, the frequency of the tuner output signal is converted,
A VSB-AM signal having a video carrier frequency of 2 _fsc is used.

<Sixth Design Criteria> In order to make the circuit for digital signal processing a circuit that can be realized as a one-chip LSI, downsampling (decimation) is performed after the output of the quadrature synchronous detection circuit in the main line system. It is configured to operate with a 4 _fsc clock signal. Further, a frequency / phase shift detection and correction circuit, and further down-sampled, in a clock signal of f _sc, the complex limiter circuit to operate the next narrowband LPF circuit, an output signal obtained by these processes A configuration is adopted in which the sampling frequency is up-sampled and returned to the original clock frequency, thereby achieving an operation speed at which the complex limiter circuit can respond, and also realizes high stability and good filter characteristics.

<Seventh Design Criteria> A CPU, such as a DSP (Digital Signal Processor) serving as an interference wave detection filter coefficient control circuit, provided in an LSI is provided in the cancellation circuit, and an I-axis input to the cancellation circuit is provided. The frequency and level of the interfering wave and the polarity of the interfering wave (the phase in the baseband is 180 degrees depending on whether the frequency is higher or lower than the carrier wave) by FFT processing (fast Fourier transform processing) from the side output signal and the Q-axis side output signal. The frequency of the interfering wave to be canceled is selected (for example, the top eight waves having a high degree of interference) are determined by the weighting determination in consideration of the detection limit characteristic. By changing the filter coefficient of the adaptive filter circuit so as to realize the filter characteristic that becomes the pass characteristic, the removal characteristic with high improvement effect is realized. .

Then, the entire circuit of the E-spot interference canceller was redesigned so as to satisfy these first to seventh design criteria, and a digitized E-spot interference canceller was designed.

Hereinafter, an embodiment of a digitized E-spot interference canceling circuit according to the present invention, which satisfies each of the above design criteria, will be described in detail with reference to the drawings.

<< Description of Circuits Corresponding to Claims 1, 2 and 7 >><Description of Overall Configuration> FIG.
FIG. 2 is a block diagram illustrating an example of the overall configuration of an E-spot interference canceller using a sport interference removal circuit. In this figure, in order to simplify the explanation, the IF signal (f _v = 58.
75 MHz) only was processed, the processing of the audio system, it is assumed that the audio-modulated wave component (f _a = 54.25MHz) has already been separated.

The E-spot interference canceller 1 shown in FIG.
Captures an IF signal of a specified frequency output from the TV tuner 2, performs analog processing, and obtains a digital IF signal, a digital local signal,
And a frequency conversion / clock generation circuit 3 for generating a clock signal, a digital IF signal, a digital local signal output from the frequency conversion / clock generation circuit 3,
And a clock signal, and digitized Espo interference removal circuit 4 for removing Espo interference waves by digital processing, and digitized Espo interference removal circuit 4
Digital video signal (digital video signal of NTSC system) output from
A D / A conversion circuit 5 for generating an analog video signal (video signal in analog signal format).

The frequency conversion / clock generation circuit 3
The specified frequency (f _v = 5) output from the TV tuner 2
8.75MHz) IF signal is envelope detected,
A color subcarrier frequency signal having a color subcarrier frequency f _sc (about 3.58 MHz) and a horizontal frequency f
_h (approximately 15.734 kHz), a reference signal reproducing circuit 6 for reproducing a horizontal frequency signal, and a color subcarrier frequency signal based on the color subcarrier frequency signal or the horizontal frequency signal output from the reference signal reproducing circuit 6. 8 times the frequency f _ck (where f _ck = 8f _sc ),
Using a clock PLL circuit 7 for generating a clock signal for digital signal processing and a local signal having a frequency 2 _fsc twice the frequency of the color subcarrier frequency signal, and a local signal output from the clock PLL circuit 7,
A synchronizing frequency conversion circuit 8 for converting an IF signal output from the TV tuner 2 into an IF signal having a frequency twice the color subcarrier frequency and synchronized with a clock signal;
An A / D conversion circuit 9 that A / D converts a local signal output from the clock PLL circuit 7 based on a clock signal output from the clock PLL circuit 7 to generate a digital local signal; The IF signal output from the synchronization frequency conversion circuit 8 is A / D-converted based on the output clock signal to obtain a digital IF signal.
An A / D conversion circuit 10 for generating a signal.

The frequency conversion / clock generation circuit 3 outputs the I / O signal of the specified frequency output from the TV tuner 2.
The F signal is envelope-detected to reproduce a color subcarrier frequency signal and a horizontal frequency signal. Based on the color subcarrier frequency signal and the horizontal frequency signal, the frequency f is eight times the color subcarrier frequency _{fsc. ck}
Clock signal with color subcarrier frequency f _sc
And a local signal having a frequency twice as high as the local signal, and supplies the clock signal to the digitized Espo interference canceller 4. In parallel with this operation, based on the local signal, the IF signal is converted into an IF signal synchronized with the clock signal and having a frequency twice the color subcarrier frequency, and based on the clock signal, A / D converting each of the local signals and a digital IF signal,
A digital local signal is generated, and these are supplied to the digitized ESPO interference canceller circuit 4.

The above-mentioned digitized E-spot interference interference removal circuit 4
Is a local signal that generates a 0-degree signal and a 90-degree signal necessary for quadrature synchronous detection of a digital IF signal based on a digital local signal output from the A / D conversion circuit 9 of the frequency conversion / clock generation circuit 3. A signal circuit 11, a step Nyquist filter circuit 12 for performing pre-processing necessary for digital processing on a digital IF signal output from the A / D conversion circuit 10 of the frequency conversion / clock generation circuit 3, and a local signal circuit A quadrature synchronous detection of the digital IF signal output from the step Nyquist filter circuit 12 based on the 0-degree signal and the 90-degree signal output from the signal generator 11 to generate an in-phase output baseband signal and a quadrature output baseband signal. A synchronous detection circuit 13 and an in-phase output baseband signal output from the quadrature synchronous detection circuit 13 And each sampled and force baseband signal, a down sampling circuit 14 for generating a half-phase output signal and the quadrature output signal and the clock frequency 4f _sc, and the in-phase output signal output from the downsampling circuit 14 quadrature Frequency / phase shift detection correction for compensating for a frequency shift and a phase shift included in the output signal and generating an I-axis output signal and a Q-axis output signal separated into an I-axis component and a Q-axis component. The circuit 15 and the Q-axis side output signal output from the frequency / phase shift detection / correction circuit 15 are subjected to Hilbert transform processing and adaptive filter processing to obtain an interference wave component (I
180 for the interference component contained in the shaft side output signal.
Interference phase component whose phase is shifted by degrees)
A cancel circuit for adding an I-axis output signal and an interference wave component output from the frequency / phase shift detection and correction circuit to cancel an interference wave component included in the I-axis output signal; I have.

In this case, the cancel circuit 16 performs an FFT process on the I-axis output signal and the Q-axis output signal output from the frequency / phase shift detection and correction circuit 15 to obtain an interference wave frequency band, level, and polarity. , And performs a comparison taking into account the visual weighting of the NTSC signal with respect to the entire detected interference frequency band or the beat interference. An interference wave detection filter coefficient control circuit 17 for obtaining a filter tap coefficient required to realize a filter characteristic for passing a band, and a frequency / phase shift detection correction circuit 15
Performs a Hilbert transform process on the Q-axis-side output signal output from the A / D converter to shift the phase of the Q-axis-side output signal by 90 degrees over a wide band, and outputs a filter output from the interference wave detection filter coefficient control circuit 17. A Hilbert transform / adaptive filter circuit for passing an interfering wave component included in the Q-axis side output signal whose phase is shifted by 90 degrees by a Hilbert transform process by switching filter tap coefficients based on the tap coefficient signal; /
The delay / correction circuit 15 has a delay time corresponding to the processing delay time of the adaptive filter circuit 18.
A delay circuit 19 for receiving and delaying the I-axis side output signal output from the delay circuit 19, and outputting the delayed I-axis side output signal output from the delay circuit 19 and the Hilbert transform / adaptive filter circuit 18 , And the interfering wave component whose phase is shifted by 180 degrees,
An adder circuit for canceling an interference wave component included in the shaft-side output signal and generating an NTSC digital video signal;

The digitized E-spo interference canceller 4 fetches the digital IF signal output from the frequency converter / clock generator 3 based on the clock signal output from the frequency converter / clock generator 3. A pre-process is performed so that the digital IF signal satisfies the Nyquist characteristic, and a digital local signal output from the frequency conversion / clock generation circuit 3 is converted based on the clock signal output from the frequency conversion / clock generation circuit 3. To generate a 0-degree signal and a 90-degree signal, and based on the 0-degree signal and the 90-degree signal, perform quadrature synchronous detection on the preprocessed digital IF signal, and output an in-phase output baseband signal; And a quadrature output baseband signal. Next, the in-phase output baseband signal and the quadrature output baseband signal are down-sampled to generate an in-phase output signal and a quadrature output signal whose clock frequency is reduced by half, and these in-phase output signals,
A frequency shift and a phase shift of the quadrature output signal are compensated to generate an I-axis output signal and a Q-axis output signal. further,
Based on the I-axis output signal and the Q-axis output signal,
A filter tap coefficient for realizing a filter characteristic required to pass the frequency band of the interfering wave is obtained, and while the filter tap coefficient of the Hilbert transform / adaptive filter circuit 18 is switched, a phase of 1 is output from the Q-axis side output signal.
An interference wave component shifted by 80 degrees is extracted, and this interference wave component and the I-axis side output signal are added to generate an NTSC digital video signal in which the interference wave component is canceled, and this is D / A It is supplied to the conversion circuit 5.

As described above, in the E-spo interference removal apparatus 1, the frequency conversion / clock generation circuit 3 fetches the IF signal of the specified frequency output from the TV tuner 2 receiving the broadcast wave, and An IF signal, a digital local signal, and a clock signal are generated, and the digital IF signal and the digital local signal are processed by the digitized E-spo interference removal circuit 4, and the E-spo interference component included in the digital IF signal is processed. , And the resulting digital video signal of the NTSC system is D / A converted to generate a video signal in an analog signal format. For this reason, the circuit size of the digitized E-spot interference interference elimination circuit 4 can be reduced, and stable operation can be performed. As a result, the digitized E-spot interference interference elimination circuit 4 can be integrated into an LSI, and the improvement effect can be obtained. , It is possible to implement the Espo interference jamming and elimination device 1 with high cost at low cost.

<Description of a Basic Circuit in which the Digitized E-Spot Interference Elimination Circuit 4 is Integrated into an LSI> FIG. Among the basic circuits, the number of taps of the frequency / phase shift detection / correction circuit 15, the cancellation circuit 16 and the like is increased to increase the accuracy, and an A / D conversion circuit and a D / A conversion circuit are provided as input / output interface circuits. FIG. 3 is a block diagram showing an example of a digitized E-spot interference interference removal basic circuit in which the number of terminals of an LSI chip is reduced.

The digitized E-spot interference interference removal basic circuit 4a shown in FIG. 1 includes an A / D conversion circuit 9, a local signal circuit 11, an A / D conversion circuit 10, a step Nyquist filter circuit 12, a quadrature synchronization circuit. Detection circuit 13, frequency / phase shift detection and correction circuit 15, cancellation circuit 16
And a D / A conversion circuit 5, which takes in an IF signal output from the synchronization frequency conversion circuit 8 of the frequency conversion / clock generation circuit 3 and performs preprocessing so as to satisfy Nyquist characteristics. To generate a digital IF signal, and fetch a local signal output from the clock PLL circuit 7 of the frequency conversion / clock generation circuit 3 or an external local signal output from an external carrier reproduction circuit, and Quadrature synchronous detection is performed to generate an in-phase output baseband signal and a quadrature output baseband signal. Next, an I-axis output signal and a Q-axis output signal are generated by compensating for a frequency shift and a phase shift of the in-phase output baseband signal and the quadrature output baseband signal. , A Q-axis side output signal, and generates an NTSC digital video signal from which an interference wave component has been removed, and D / A converts the digital video signal into
It outputs a video signal in TSC analog signal format.

Next, the local signal circuit 11 constituting the above-described digitized E-spot interference interference removal basic circuit 4a
The quadrature synchronous detection circuit 13, frequency / phase shift detection and correction circuit 15, and external carrier reproduction circuit will be described in detail.

<Description of External Carrier Reproduction Circuit> FIG.
FIG. 3 is a block diagram showing an example of an external carrier reproducing circuit for supplying a local signal to the A / D conversion circuit 9 shown in FIG. 2;

As shown in FIG. 4 (a), the carrier reproducing circuit 21 shown in FIG. 4 generates a VSB-AM signal having a carrier component and a DSB region including only an amplitude modulation component and not including a phase modulation component. When it is input, it is subjected to narrow-band bandpass filtering to extract only the vicinity of the carrier component shown in FIG.
Is compared with the narrowed VSB-AM signal output from the narrow band BPF circuit 22 and a preset threshold value, thereby eliminating the amplitude change and changing the modulated wave component near the carrier. Suppress, as shown in FIG.
A comparator circuit for reproducing a substantially unmodulated rectangular carrier signal; and a band-pass filtering performed on the rectangular carrier signal output from the rectangular carrier signal output from the comparator circuit to obtain a signal other than the carrier signal. As shown in FIG. 4D, the BPF circuit 24 generates a sine wave signal indicating the carrier of the VSB-AM signal.

When a VSB-AM signal having only a carrier component and a DSB region including only an amplitude modulation component and not including a phase modulation component is input to the carrier reproduction circuit 21, the VSB-AM signal On the other hand, a narrow band band-pass filtering process, a comparator process, and a band-pass filtering process are sequentially performed to generate a VSB-
A sine wave signal indicating the carrier of the AM signal is generated, supplied to the A / D conversion circuit 9, A / D converted, and the digital local signal obtained by this is supplied to the local signal circuit 11.

<< Description of Circuit Corresponding to Claim 4 >><Description of Local Signal Circuit 11> FIG. 5 is a block diagram showing a detailed circuit configuration example of the local signal circuit 11 shown in FIGS.

The local signal circuit 11 shown in FIG.
The digital local signal output from the / D conversion circuit 9 is captured, and the digital local signal is
Perform a Hilbert transform to set the phase to 90 over a wide band.
Hilbert transform circuit 25 that shifts the signal by a degree and a BPF circuit that performs a band-pass filtering process on the digital local signal that has been phase-shifted and output from the Hilbert transform circuit 25 to remove unnecessary harmonics and generate a 90-degree signal. 26, and a delay time corresponding to the delay amount of the BPF circuit 26 and the Hilbert transform circuit 25.
A delay circuit 27 for delaying the digital local signal output from the A / D conversion circuit 9 to generate a 0-degree signal.

The local signal circuit 11 is output from the external carrier reproducing circuit 21 shown in FIG.
When the digital local signal subjected to A / D conversion by the / D conversion circuit 9 is input, or output from the frequency conversion / clock generation circuit 3 shown in FIG. 1, the A / D conversion is performed by the A / D conversion circuit 9. When a digital local signal is input,
A Hilbert transform process and a band pass filtering process are sequentially performed to generate a 90-degree signal, which is supplied to the quadrature synchronous detection circuit 13, and a digital local signal is subjected to a delay process to generate a 0-degree signal. Are supplied to a quadrature synchronous detection circuit 13.

<Description of First Example of Quadrature Synchronous Detection Circuit 13>
FIG. 6 is a block diagram showing a detailed circuit configuration example of the quadrature synchronous detection circuit 13 shown in FIGS.

The quadrature synchronous detection circuit 13 shown in this figure is composed of the digital IF signal output from the step Nyquist filter circuit 12 and the delay circuit 2 of the local signal circuit 11.
A multiplication circuit 28 for generating an in-phase output baseband signal by multiplying the 0-degree signal outputted from
LPF circuit 2 that performs low-pass filtering on the in-phase output baseband signal output from 8 and removes extra components
9, the digital IF signal output from the step Nyquist filter circuit 12 and the BPF of the local signal circuit 11.
A multiplication circuit 30 for multiplying the 90-degree signal output from the circuit 26 to generate a quadrature output baseband signal; and a low-pass filtering of the quadrature output baseband signal output from the multiplication circuit 30 to remove extra components LP
An F circuit 31 is provided.

The quadrature synchronous detection circuit 13 uses the 0-degree signal and the 90-degree signal output from the local signal circuit 11 to generate the step Nyquist filter circuit 1.
The digital IF signal output from 2 is subjected to quadrature synchronous detection to generate an in-phase output baseband signal and a quadrature output baseband signal.

<< Description of Circuit Corresponding to Claim 3 >><Description of Second Example of Quadrature Synchronous Detector 13> The orthogonal synchronous detector 13 shown in FIG.
Alternatively, a quadrature synchronous detection circuit using the method described below may be used.

[0065] First, when the frequency f _ck of the clock signal is four times the frequency of the local signal, as shown in FIG. 7 (a), a local signal frequency f becomes "f = 2f _sc" is input Then, when this is shifted by 90 degrees, a waveform shifted by 90 degrees from the original local signal is obtained as shown in FIG. 7B.

At this time, as shown in FIG. 7C, if the frequency f _{ck of the} clock signal is set to “f _ck = 8f _sc ”, the sampling points must correspond to every 90 degrees of the local signal. Therefore, as shown in FIG. 7D, the in-phase component “cos θ” of the local signal is changed to “1, 0, −1, 0”.
And the orthogonal component “sin θ” is represented by “0, −1, 0,
1 ".

When such a property is used, the input signal is passed as it is when "1" is set without using the multiplication circuits 28 and 30 as in the above-described quadrature synchronous detection circuit 13. When “0” is set,
A simple switch circuit that outputs zero data and inverts the input signal when “−1” is set, performs quadrature synchronous detection on the digital IF signal, and outputs the in-phase output baseband signal and , And quadrature output baseband signals.

FIG. 8 is a block diagram showing another example of the quadrature synchronous detection circuit 13 utilizing such properties.

The quadrature synchronous detection circuit 13 shown in FIG. 2 is a synchronous frequency detector which synchronizes with a clock signal of a frequency f _ck (f _ck = 8f _sc ) output from the frequency conversion / clock generation circuit 3 or the like, and A zero data circuit 32 that outputs data (zero signal) indicating the following, a latch circuit 33 that fetches a digital IF signal output from the step Nyquist filter circuit 12 in synchronization with the clock signal, and latches the digital IF signal. Nyquist filter circuit 12
And a sign inverting circuit 34 for inverting the sign, and a sign-inverted digital IF signal outputted from the sign inverting circuit 34 in synchronization with the clock signal. A latch circuit 35 for latching, and a sequence "1, 0,..."
-1, 0 "and the sequence" 0,
And a switching control circuit 36 for generating “−1, 0, 1”.

Further, the quadrature synchronous detection circuit 13 performs a latch circuit 3 based on a sequence of in-phase components “1, 0, −1, 0” of the local signal output from the switching control circuit 36.
Digital IF signal output from 3 and zero data circuit 3
A switching circuit 37 for selecting one of the zero signal output from the second circuit 2 and the digital IF signal whose sign has been inverted output from the latch circuit 35 to generate an in-phase output baseband signal; The digital IF output from the latch circuit 33 is based on the sequence of orthogonal components “0, −1, 0, 1” of the local signal output from the
A switch circuit 38 that selects one of a signal, a zero signal output from the zero data circuit 32, and a sign-inverted digital IF signal output from the latch circuit 35 to generate a quadrature output baseband signal; It has.

This quadrature synchronous detection circuit 13 synchronizes with the clock signal of the frequency f _ck (f _ck = 8f _sc ) output from the frequency conversion / clock generation circuit 3 and the like, and outputs the output from the step Nyquist filter circuit 12. The digital IF signal obtained is taken in, and a digital IF signal whose sign is not inverted and a digital IF signal whose sign is inverted are generated, and based on the clock signal, become the in-phase component “cos θ” of the local signal. "1, 0,-
1, 0 ”and the orthogonal component“ sin ”of the local signal.
A sequence of “0, −1, 0, 1” that becomes θ ”is generated, and a sequence of the in-phase component“ 1, 0, −1, 0 ”of these local signals and the quadrature component“ 0 ”of the local signal are generated. , -1, 0,
Based on the sequence of "1", a digital IF signal whose sign is not inverted, a zero signal indicating zero data, or a digital IF signal whose sign is inverted is selected, and an in-phase output baseband signal and a quadrature output baseband are selected. Generate a signal and
After removing unnecessary components by the LPF circuit, they are supplied to the frequency / phase shift detection / correction circuit 15.

Thus, the quadrature synchronous detection circuit 13
Uses a clock signal of a frequency f _ck (f _ck = 8f _sc ) output from the frequency conversion / clock generation circuit 3 or the like, that is, a clock signal synchronized with an IF signal output from the frequency conversion / clock generation circuit 3 or the like. Then, it is a simple circuit that only switches each switch circuit 37, 38,
In principle, there is no phase shift, and synchronous detection with good orthogonality can be performed.

Further, by using the quadrature synchronous detection circuit 13, the in-phase component of the local signal can be obtained from the clock signal of the frequency f _ck (f _ck = 8f _sc ) output from the frequency conversion / clock generation circuit 3 or the like. "1, 0, -1,
0 ”and the orthogonal component“ 0, −1,
A sequence of "0, 1" is generated, and an in-phase output baseband signal and a quadrature output baseband signal are generated from the digital IF signal output from the step Nyquist filter circuit 12. 2, the local signal circuit 11 and the A / D conversion circuit 9 for the local signal can be eliminated, and the circuit can be simplified.

<< Description of Circuit Corresponding to Claim 5 >><Description of First Example of Frequency / Phase Deviation Detection and Correction Circuit 15>
FIG. 9 is a block diagram showing a detailed circuit configuration example of the frequency / phase shift detection and correction circuit 15 shown in FIGS.

The frequency / phase shift detection / correction circuit 15 shown in FIG. 3 receives the in-phase output baseband signal output from the quadrature synchronous detection circuit 13 and extracts only the low-frequency component of the in-phase output baseband signal. A limiting filter circuit 39, a band limiting filter circuit 40 that takes in the quadrature output baseband signal output from the quadrature synchronous detection circuit 13, and extracts only the low frequency component of the quadrature output baseband signal, Circuit 3
The complex phase information is generated by making the vector lengths of the band-limited in-phase output baseband signal and the band-limited quadrature output baseband signal output from 9 and 40 constant.
A complex limiter circuit 41 that generates an axis-side correction signal and a Q-axis side correction signal; and a harmonic filter other than a necessary complex phase information component by performing narrow band filtering on the I-axis side correction signal output from the complex limiter circuit 41. A narrow band filter circuit 42 for removing a wave component, and a narrow band filter circuit for performing a narrow band filtering on the Q-axis side correction signal output from the complex limiter circuit 41 to remove a harmonic component other than a necessary complex phase information component. 43.

Further, the frequency / phase shift detection / correction circuit 15 includes these band limiting filter circuits 39 and 40, a complex limiter circuit 41, and a narrow band filter circuit 42.
A delay circuit 44 having a delay time corresponding to the delay amount 43 and delaying the in-phase output baseband signal output from the quadrature synchronous detection circuit 13;
9, a delay circuit 45 having a delay time corresponding to the delay amount of the complex limiter circuit 41 and the narrow band filter circuits 42 and 43, and delaying the quadrature output baseband signal output from the quadrature synchronous detection circuit 13, An in-phase output baseband signal output from each of the delay circuits 44 and 45 based on the band-limited I-axis correction signal and the band-limited Q-axis correction signal output from each of the narrow band filter circuits 42 and 43. A phase rotation circuit 46 that corrects the frequency shift and the phase shift of the quadrature output baseband signal, converts the vector rotation into a stationary vector with a reverse rotation component, and separates the vector rotation into an I-axis component and a Q-axis component. I have.

The frequency / phase shift detection / correction circuit 15 takes in the in-phase output baseband signal and the quadrature output baseband signal output from the quadrature synchronous detection circuit 13 and performs two band limiting filter circuits 39, 40,
Complex limiter circuit 41, two narrow band filter circuits 4
A frequency / phase shift detection circuit 47 constituted by 2 and 43 detects whether there is a frequency shift, a phase shift or the like between the in-phase output baseband signal and the quadrature output baseband signal and the local signal. An I-axis side correction signal and a Q-axis side correction signal are generated, and based on the I-axis side correction signal and the Q-axis side correction signal, two delay circuits 44 and 45 and one phase rotation circuit 46 are used. The in-phase output baseband signal and the quadrature output baseband signal output from the quadrature synchronous detection circuit 13 are frequency-shift-corrected and phase-shift-corrected by the configured frequency / phase-shift correcting circuit 48 to obtain the I-axis component and , Q-axis-side component, and an I-axis-side output signal that is completely separated from the Q-axis-side component.

Thus, there is a frequency shift or a phase shift between the in-phase output baseband signal and the quadrature output baseband signal output from the quadrature synchronous detection circuit 13 and the local signal, and even if the vector is rotated. And I
Even if the axis component and the Q axis component are mixed, the frequency / phase shift detection correction circuit 48 corrects this, and completely separates the I axis side component and the Q axis side component into the I axis side component. The output signal and the Q-axis output signal can be supplied to the cancel circuit 16.

<< Description of Circuit Corresponding to Claim 10 >><Description of Second Example of Frequency / Phase Deviation Detection and Correction Circuit 15>
FIG. 10 shows the frequency / phase shift detection and correction circuit 1 shown in FIG.
FIG. 9 is a block diagram illustrating a circuit configuration example other than 5;

The frequency / phase shift detection and correction circuit 15 shown in FIG.
5 is that a down-sampling circuit 4 is provided between the complex limiter circuit 41 and each of the band-limiting filter circuits 39 and 40.
9 for downsampling the band-limited in-phase output baseband signal and the band-limited quadrature output baseband signal output from each of the band-limiting filter circuits 39 and 40, lowering the clock frequency, and then setting the complex limiter. Supply to the circuit 41 and each narrow-band filter circuit 4
Two narrow band LPs with reduced number of taps instead of 2, 43
F circuits 50 and 51 are used, and these narrow band LPFs are used.
An up-sampling circuit 52 is provided at a stage subsequent to the circuits 50 and 51, and the up-sampling circuit 52 allows each narrow band L
That is, the narrowed I-axis correction signal and the narrowed Q-axis correction signal output from the PF circuits 50 and 51 are up-sampled to return to the original clock frequency.

In this case, the down-sampling circuit 49 thins out the band-limited in-phase output baseband signal output from the band-limiting filter circuit 39 and lowers the clock frequency to _fsc. The clock frequency is set to f by thinning out the band-limited quadrature output baseband signal output from the filter circuit 40.
and a sample rate conversion circuit 54 for reducing the frequency to _sc. An in-phase output baseband signal having a frequency of f _sc and a quadrature output baseband signal are generated and supplied to the complex limiter circuit 41.

The up-sampling circuit 52 performs zero interpolation on the narrowed band I-axis side correction signal output from the narrow band LPF circuit 50 to reduce the frequency until the clock frequency becomes 4 _fsc. , An interpolation filter circuit 56 for interpolating the characteristics of the up-sampled I-axis side correction signal output from the sample rate conversion circuit 55, and an output from the narrow band LPF circuit 51. A zero-interpolation process is performed on the Q-band correction signal having been subjected to the band narrowing to increase the clock frequency to 4 _fsc , and an up-sampled Q output from the sample rate conversion circuit 57 And an interpolation filter circuit 58 for interpolating the characteristics of the axis-side correction signal. And narrowing already I axis side correction signal, the narrowband LPF circuit 51 and a narrowing already Q axis side correction signal upsampled output from the I axis side correction signal clock frequency 4f _sc , And a Q-axis side correction signal, and then interpolates the characteristics of the up-sampling processing and supplies the result to the phase rotation circuit 46.

As described above, in the frequency / phase shift detection and correction circuit 15, the clock frequencies of the in-phase output baseband signal and the quadrature output baseband signal supplied to the complex limiter circuit 41 are reduced to _fsc , and the complex limiter After being processed by the circuit 41 and the narrow band LPF circuits 50 and 51,
The up-sampling circuit 52 returns the original clock frequency to 4 _fsc again, and supplies the I-axis side correction signal and the Q-axis side correction signal thus obtained to the phase rotation circuit 46. The operation speed of the route calculation, function generation division, and the like performed by the limiter circuit 46 can be reduced, and the operation of the complex limiter circuit 46 can be stabilized.

For each required characteristic, each narrow band LPF
The operating speed of the circuits 50 and 51 can be reduced, the number of taps of each of the narrow band LPF circuits 50 and 51 can be reduced, the margin for oscillation can be increased, and the operation can be stabilized.

<< Description of Circuit Corresponding to Claim 6 >><Description of First Example of Complex Limiter Circuit 41> FIG. 11 shows a complex circuit used in each frequency / phase shift detection circuit 47 shown in FIGS. FIG. 3 is a block diagram illustrating a detailed circuit configuration example of a limiter circuit 41.

A complex limiter circuit 41 shown in FIG.
Circuit 65 for squaring the band-limited in-phase output baseband signal output from
A multiplier circuit 66 for squaring the quadrature output baseband signal output from the zero or down-sampling circuit 49 and having the band limited, an in-phase output baseband square signal output from each of these multipliers 65 and 66, and a quadrature output Baseband 2
An addition circuit 67 for adding the multiplication signal;
Has a delay time equal to the processing delay time of the root calculation circuit 68 for generating the envelope signal by square rooting the square sum signal output from the A delay circuit 69 that delays the band-limited in-phase output baseband signal output from the filter circuit 39 or the down-sampling circuit 49 and an envelope signal output from the route operation circuit 68 are used to output the delay signal from the delay circuit 69. Divides the delayed in-phase output baseband signal to generate an I-axis side correction signal (complex output signal) having a constant amplitude vector, a multiplication circuit 66, and an addition circuit 6.
7, and a delay circuit 71 having the same delay time as the processing delay time of the route operation circuit 68 and delaying the band-limited quadrature output baseband signal output from the band-limiting filter circuit 40 or the down-sampling circuit 49;
Using the envelope signal output from the route calculation circuit 68, the delayed quadrature output baseband signal output from the delay circuit 71 is divided to obtain a Q-axis side correction signal (complex output signal) having a constant amplitude vector. ) Is generated.

The complex limiter circuit 41 squares each of the band-limited in-phase output baseband signal and the quadrature output baseband signal output from each of the band-limiting filter circuits 39 and 40 or the down-sampling circuit 49. After generating an in-phase output baseband squared signal and a quadrature output baseband squared signal, the in-phase output baseband squared signal and the quadrature output baseband squared signal are added to obtain a squared signal. After finding the sum signal, square it out,
An envelope signal having an amplitude (vector length) when the in-phase output baseband signal and the quadrature output baseband signal are vectors is obtained. In parallel with this operation, the in-phase output baseband signal is divided by the amplitude to generate an I-axis side correction signal having a constant amplitude vector.
While supplying the signal to the circuit 50, the quadrature output baseband signal is divided by the amplitude to generate a Q-axis-side correction signal having a constant amplitude vector, which is sent to the narrow band filter circuit 43 or the narrow band LPF circuit 51. Supply.

<Description of Second Example of Complex Limiter Circuit 41>
FIG. 12 is a block diagram showing another example of the circuit configuration of the complex limiter circuit 41 used in each of the frequency / phase shift detection circuits 47 shown in FIGS.

A complex limiter circuit 41 shown in FIG.
, An absolute value circuit 73 for calculating the absolute value of the band-limited in-phase output baseband signal output from the band-pass filter, and the absolute value of the band-limited quadrature output baseband signal output from the band-limiting filter circuit 40 or the down-sampler 49 , And the absolute value circuits 73,
A comparison circuit 75 that compares the in-phase absolute value signal and the quadrature-side absolute value signal output from 74 to generate a switching signal indicating the larger absolute value, and a switch that selects the in-phase side from the comparison circuit 75 When a signal is output, the absolute value circuit 7
3 is output as the a-side signal, and when the switching signal for selecting the quadrature side is output from the comparison circuit 75, the switch is switched and output from the absolute value circuit 73. When the switch circuit 76 for outputting the in-phase absolute value signal as the b-side signal and the switching signal for selecting the quadrature side are output from the comparison circuit 75, the switches are switched and the quadrature side output from the absolute value circuit 74 is output. The absolute value signal is output as an a-side signal.
When the switching signal to select the in-phase side is output from
A switch circuit 77 for outputting the orthogonal-side absolute value signal output from the absolute value circuit 74 as a b-side signal.

Further, the complex limiter circuit 41 looks up a table based on the ratio (b / a) of the a-side signal and the b-side signal output from each of the switch circuits 76 and 77, and A function generating circuit 78 for generating a function signal (amplitude coefficient signal) having a value L shown in the equation (1), and an a-side signal output from one of the switch circuits 76 and 77. A division circuit 79 for dividing the output function signal and outputting the division result K (K = L / a) as a multiplication coefficient signal; a multiplication coefficient signal output from the division circuit 79 and a band limiting filter A multiplication circuit 8 that multiplies with the band-limited in-phase output baseband signal output from the circuit 39 or the down-sampling circuit 49 to generate an I-axis side correction signal (complex output signal) having a constant amplitude vector. Is multiplied by the multiplication coefficient signal output from the division circuit 79 and the band-limited quadrature output baseband signal output from the band-limiting filter circuit 40 or the down-sampling circuit 49 to form a vector having a constant amplitude. A multiplying circuit 81 for generating a Q-axis side correction signal (complex output signal).

[0091]

L = 1 / √ (1+ (b / a) ² ) (1) Then, the band-limited in-phase output baseband signal output from each band-limiting filter circuit 39, 40 or down-sampling circuit 49. And the absolute value of the quadrature output baseband signal are determined, and the one with the larger absolute value
The side signal having the smaller absolute value is set as the b-side signal, and a function signal having the value L shown in the equation (1) is generated, and the function signal is divided by the a-side signal to generate a multiplication coefficient signal. Next, the multiplication coefficient signal is multiplied by the band-limited in-phase output baseband signal output from the band-limiting filter circuit 39 or the down-sampling circuit 49 to obtain an I-axis side correction signal having a constant amplitude vector. The signal is generated and supplied to the narrow band filter circuit 42 or the narrow band LPF circuit 50, and the multiplication coefficient signal and the band-limited quadrature output baseband signal output from the band-limiting filter circuit 40 or the down-sampling circuit 49 are generated. Multiply by
Generate a Q-axis side correction signal with a constant amplitude vector,
This is supplied to the narrow band filter circuit 43 or the narrow band LPF circuit 51.

Thus, the complex limiter circuit 41
In this case, the same function as the above-described complex limiter circuit 41 can be achieved while reducing the circuit scale and increasing the accuracy as compared with the complex limiter circuit 41 shown in FIG.

<Description of Phase Rotation Circuit 46> FIG. 13 is a block diagram showing a detailed circuit configuration example of the phase rotation circuit 46 used in each frequency / phase shift correction circuit 48 shown in FIGS. .

The phase rotation circuit 46 shown in the figure includes an I-axis side correction signal output from the frequency / phase shift detection circuit 47, an in-phase output baseband signal output from each of the delay circuits 44 and 45, and a quadrature output baseband. Two multiplication circuits 59 and 60 for multiplying the respective signals, a Q-axis side correction signal output from the frequency / phase shift detection circuit 47, an in-phase output baseband signal output from each of the delay circuits 44 and 45, and a quadrature output Two multiplication circuits 61 and 62 for multiplying the baseband signal by each of the multipliers, and the multiplied in-phase output baseband signals and the multiplied quadrature output baseband signals output from the respective multiplication circuits 59 and 62 are added, An adding circuit 63 for generating an I-axis side output signal;
Calculating a difference between the multiplied in-phase output baseband signal output from 1 and the multiplied quadrature output baseband signal,
An adder circuit 64 for generating a Q-axis output signal.

The phase rotation circuit 46 controls each delay circuit 44 based on the I-axis correction signal and the Q-axis correction signal output from the frequency / phase shift detection circuit 47.
The vector rotation or the phase shift of the in-phase output baseband signal and the quadrature output baseband signal output from 45 is rotated or phase-shifted in the opposite direction, and the I-axis output signal without vector rotation and phase shift, and the Q-axis side An output signal is generated and supplied to the cancel circuit 16.

<Other Description of Digitized Espo Interference Interference Basic Circuit 4a> In the above-described digitized Espo interference interference removal basic circuit 4a, the frequency f _ck (f _ck = 8)
_f.sub.sc ), two A / D converter circuits 9 and 10 and a step Nyquist filter circuit 12 which constitute the digitized E-spot interference canceling basic circuit 4a.
, A local signal circuit 11 and a quadrature synchronous detection circuit 13
, The frequency / phase shift detection and correction circuit 15, the cancellation circuit 16, and the D / A conversion circuit 5 are operated. As shown in FIG. 14, the digitized E-spot interference interference removal basic circuit 4a Quadrature synchronous detection circuit 13 constituting
A down-sampling circuit 14 may be provided between the circuit and the frequency / phase shift detection and correction circuit 15.

In this case, the down-sampling circuit 14 adjusts the clock frequency output from the quadrature synchronous detection circuit 13 to 8
thinning out phase output baseband signal f _sc, and sample rate conversion circuit 82 the clock frequency to produce an in-phase output baseband signal 4f _sc, quadrature synchronous detection circuit 13
And a sample rate conversion circuit 83 for thinning out a quadrature output baseband signal having a clock frequency of 8 _{fsc and generating} a quadrature output baseband signal having a clock frequency of 4 _fsc. The in-phase output baseband signal having a clock frequency of 8 _fsc is thinned to generate an in-phase output baseband signal having a clock frequency of 4 _fsc. Circuit 1
A quadrature output baseband signal having a clock frequency of 8 _fsc output from 3 is decimated to generate a quadrature output baseband signal having a clock frequency of 4 _fsc .

Thus, in the digitized E-spot interference interference removal basic circuit 4a, the frequency / phase shift detection correction circuit 15, the cancellation circuit 16, and the D / A conversion circuit 5 operate at a clock frequency of 4 _fsc and operate reasonably. Can be performed, and the number of taps of each filter can be reduced to reduce the circuit scale.

<< Explanation 1 of Circuit Corresponding to Claims 7, 8 and 9 >><Example of Frequency Conversion / Clock Generation Circuit 3> FIG.
FIG. 2 is a block diagram illustrating a detailed circuit configuration example of a frequency conversion / clock generation circuit 3 illustrated in FIG. 1.

The frequency conversion / clock generation circuit 3 shown in FIG.
_v = 58.75 MHz) is subjected to envelope detection to obtain a color subcarrier frequency f _sc (about 3.58 MHz).
z) and a reference signal reproducing circuit 6 for reproducing a horizontal frequency signal having a horizontal frequency f _h (about 15.734 kHz), and a color subcarrier frequency output from the reference signal reproducing circuit 6 A clock signal for digital signal processing having a frequency f _ck (f _ck = 8f _sc ) eight times that of the color subcarrier frequency signal based on the signal or the horizontal frequency signal, and a frequency 2f twice the color subcarrier frequency signal _Using a clock PLL circuit 7 having a _sc and generating a local signal, and a local signal output from the clock PLL circuit 7,
A synchronizing frequency conversion circuit 8 for converting an IF signal output from the TV tuner 2 into an IF signal having a carrier of twice the color subcarrier frequency and synchronized with a clock signal, and an output from a clock PLL circuit 7 A / D conversion is performed on the local signal output from the clock PLL circuit 7 based on the clock signal to generate a digital local signal, and based on the clock signal output from the clock PLL circuit 7, An A / D conversion circuit 10 that A / D converts an IF signal output from the synchronization frequency conversion circuit 8 to generate a digital IF signal.

In this case, based on the color subcarrier frequency signal or the horizontal frequency signal output from the reference signal reproducing circuit 6, the clock PLL circuit 7 has a frequency f _ck (f _ck = 8f) that is eight times the color sub carrier frequency signal. _sc ), a clock PLL main circuit 84 for generating a clock signal for digital signal processing and a frequency-divided signal having a frequency 2 _fsc twice as high as the color subcarrier frequency signal, and an output from the clock PLL main circuit 84. And a BPF circuit 85 that generates a sine-wave local signal by band-pass filtering the frequency-divided signal, and generates a clock signal based on the color subcarrier frequency signal or the horizontal frequency signal output from the reference signal reproducing circuit 6. A signal and a local signal are generated, and the clock signal is supplied to each of the A / D conversion circuits 9, 10, Tal of E sports interference interference elimination circuit 4, and supplies such as digitized E sports interference disturbance removal basic circuit 4a, also a local signal and A / D conversion circuit 9 is supplied to a synchronizing frequency conversion circuit 8.

The synchronizing frequency conversion circuit 8 is a carrier signal (a signal having a frequency of 58.75 MHz + ΔMHz) in which the modulated wave component of the IF signal (video carrier component) of the specified frequency f _v output from the TV tuner 2 is suppressed. And a carrier reproducing circuit 86 for reproducing the carrier.
Carrier signal output from 6 and clock PLL circuit 7
A mixer circuit 87 that mixes the local signal (2f _sc ) output from the mixer circuit to generate a mixed signal, a band-pass filtering of the mixed signal output from the mixer circuit 87, and a sum included in the mixed signal. BPF circuit 88 which component (frequency signal 58.75MHz + ΔMHz + 2f _sc) is extracted, and outputs it as a local signal
And a mixer circuit 89 for mixing the local signal output from the BPF circuit 88 with an IF signal (video carrier component) having a specified frequency f _v output from the TV tuner 2 to convert the IF signal into an IF beat signal. , This mixer circuit 8
And a BPF circuit 90 that extracts a difference frequency component included in the IF beat signal output from the IF 9 and generates an IF signal having a carrier having a frequency twice as high as the color subcarrier frequency in synchronization with the clock signal. ing. The mixer circuit 87, the BPF circuit 88, the mixer circuit 89, and the BP
The synchronizing frequency conversion main circuit according to the ninth aspect is constituted by the F circuit 90.

The synchronization frequency conversion circuit 8
A carrier signal (signal having a frequency of 58.75 MHz + Δ MHz) in which the modulation wave component of the IF signal (video carrier component) of the specified frequency f _v output from the TV tuner 2 is suppressed is reproduced, and this carrier signal and the clock PLL circuit 7 Is mixed with the local signal (2f _sc ) output from the controller to generate a mixed signal, and a local signal obtained by band-pass filtering the mixed signal and I
Mixing with the F signal to generate an IF beat signal,
Further, a difference component included in the IF beat signal is extracted, and an IF signal having a carrier having a frequency twice as high as the color subcarrier frequency is generated in synchronization with the clock signal, and supplied to the A / D conversion circuit 10. I do.

Thus, the frequency conversion / clock generation circuit 3 envelope-detects the IF signal of the specified frequency output from the TV tuner 2 to reproduce a color subcarrier frequency signal and a horizontal frequency signal. color based on the sub-carrier frequency signal and a horizontal frequency signal, having a clock signal having eight times the frequency of the color subcarrier frequency f _sc of the color subcarrier frequency signal, a frequency twice the color subcarrier frequency f _sc A local signal is generated, and the clock signal is supplied to the digitized E-spot interference rejection circuit 4 (or the digitized E-spot interference rejection basic circuit 4a). IF signal with frequency twice as high as color subcarrier frequency, synchronized with clock signal Converts, based on clock signals, and the IF signal, and each A / D conversion and a local signal, and the digital IF signal to generate a digital local signals, these digitized E sports interference disturbance removal circuit 4
To supply.

At this time, I output from TV tuner 2
Even if the frequency of the F signal changes, the difference frequency of the IF beat signal output from the mixer circuit 89 does not change, so that even if the frequency of the IF signal output from the TV tuner 2 changes, Color subcarrier frequency f
_It has a frequency 2f _sc twice as high as _sc (about 3.58 MHz).
A digital IF signal can be generated.

In the frequency conversion / clock generation circuit 3, BPF circuits such as the BPF circuits 85 and 88 are arranged at appropriate positions to prevent a loop from occurring in frequency. It is possible to prevent the occurrence of interference that often occurs due to signal wraparound and the like.

<< Explanation 2 of Circuit Corresponding to Claims 7, 8 and 9 >><Another Example of Frequency Conversion / Clock Generation Circuit 3> FIG.
FIG. 16 is a block diagram showing a detailed circuit configuration example of the frequency conversion / clock generation circuit 3 shown in FIG.

The frequency conversion / clock generation circuit 3 shown in FIG.
What is different from the reference signal reproducing circuit 6 and the clock PLL
The circuit 7 and the synchronization frequency conversion circuit 8 are embodied to facilitate the circuit design.

In this case, the reference signal reproducing circuit 6 outputs the specified frequency (f _v = 58.75) output from the TV tuner 2.
MHz), and an envelope detection circuit 91 for reproducing a baseband signal by envelope detection of an IF signal of low frequency (MHz). LPF circuit 92 for eliminating E-spo disturbing wave components within the band frequency band, and this LPF circuit 92
A synchronization separation circuit 93 for separating a horizontal synchronization signal included in the band-limited baseband signal output from
The equivalent pulse included in the horizontal synchronization signal output from the synchronization separation circuit 93 is removed, and the horizontal frequency f _h (about 1
(5.734 kHz).

[0110] Further, the reference signal reproducing circuit 6, the baseband signal output from the envelope detection circuit 91 and band-pass filtering, and f _sc for BPF circuit 95 for extracting a component near the color subcarrier frequency,
A burst lock that oscillates and generates a color subcarrier frequency signal having a color subcarrier frequency f _sc (about 3.58 MHz) based on the component signal in the vicinity of the color sub carrier output from the BPF circuit 95 for f _sc It operates in conjunction with the PLL circuit 96 and the switch circuit 97 provided in the clock PLL circuit 7, and outputs the color subcarrier frequency signal output from the burst lock PLL circuit 96 or the horizontal signal output from the equivalent pulse removal circuit 94. A switching circuit 98 for selecting one of the frequency signals.

Then, the reference signal reproducing circuit 6
Specified frequency output from tuner 2 (f _v = 58.7)
5 MHz) is detected by envelope detection, and a color subcarrier frequency signal having a color subcarrier frequency f _sc (about 3.58 MHz) and a horizontal frequency f _h (about 1
5.734 kHz) with a horizontal frequency signal,
One of the color subcarrier frequency signal and the horizontal frequency signal is selected and supplied to the clock PLL main circuit 84 of the clock PLL circuit 7.

The clock PLL main circuit 84 compares the phase of the color subcarrier frequency signal output from the reference signal reproducing circuit 6 (or the phase of the horizontal frequency signal) with the phase of the feedback signal, and determines the phase difference between these. Phase comparison circuit 99 for generating a comparison signal corresponding to
Filter circuit 100 that cuts the high frequency component of the comparison signal output from the filter and passes only the low frequency component
And a clock signal having a frequency of 8 _fsc with reference to the frequency of the color subcarrier frequency signal (or horizontal frequency signal) oscillating at an oscillation frequency corresponding to the value of the comparison signal output from the loop filter circuit 100. , A buffer circuit 102 for buffering and outputting a clock signal output from the VCXO circuit 101, and a く for thinning the frequency of the clock signal output from the VCXO circuit 101 to １ ／. And a frequency dividing circuit 103.

Further, the clock PLL main circuit 84
A buffer circuit 104 for buffering the frequency-divided signal output from the １ ／ frequency divider 103 and outputting the buffered signal;
A 1/2 frequency divider 105 for reducing the frequency of the frequency divided signal output from the 1/2 frequency divider 103 to 1/2, and buffering the frequency divided signal output from the 1/2 frequency divider 105 by buffering , A buffer circuit 106 for output, a 分 frequency divider 107 for thinning out the frequency of the frequency-divided signal output from the 分 frequency divider 105 to １ ／, and an output from the 分 frequency divider 105. Decreasing the frequency of the frequency-divided signal to 1/455
The 455 frequency dividing circuit 108 operates in conjunction with the switch circuit 98 of the reference signal reproducing circuit 6, and outputs the frequency-divided signal output from the 1/2 frequency dividing circuit 107 or the 1/455 frequency dividing circuit 108.
And a switch circuit 97 that selects one of the frequency-divided signals output from the comparator and supplies the selected signal as a feedback signal to the phase comparison circuit 99.

The clock PLL main circuit 84
When the color subcarrier frequency signal is output from the switch circuit 98 of the reference signal reproduction circuit 6, the switch circuit 97 selects the frequency-divided signal output from the 1/2 frequency divider 107, and outputs the frequency-divided signal to the feedback signal. Is supplied to the phase comparison circuit 99, and the frequency 8 which is eight times the frequency f _sc of the color subcarrier frequency signal is supplied from the VCXO circuit 101.
output a clock signal having the frequency f _sc
2 and outputs the same from the buffer circuit 106.
To output the divided signal having a frequency 2f _sc from.

When the horizontal frequency signal is being output from the switch circuit 98 of the reference signal reproducing circuit 6, the switch circuit 97 selects the frequency-divided signal output from the 1/455 frequency divider circuit 108 and feeds it back. As a signal,
The frequency is supplied to the phase comparison circuit 99, and from the VCXO circuit 101, a frequency of 455 × 2 × 2 times the frequency of the horizontal frequency signal, that is, 8 of the frequency f _sc of the color subcarrier frequency signal.
A clock signal having a double frequency of 8 _fsc is output and output from the buffer circuit 102, and a frequency-divided signal having a frequency of 2 _fsc is output from the buffer circuit 106 and supplied to the BPF circuit 85.

The synchronization frequency conversion circuit 8 is a carrier signal (a signal having a frequency of 58.75 MHz + ΔMHz) in which the modulated wave component of the IF signal (video carrier component) of the specified frequency f _v output from the TV tuner 2 is suppressed. And a carrier reproducing circuit 86 for reproducing the carrier.
A mixer circuit 87 for mixing the carrier signal output from the BPF 6 with the local signal (2f _sc ) output from the BPF circuit 85 to generate a mixed signal; and the mixer circuit 8
7 is subjected to band-pass filtering, and the sum component (with a frequency of 58.
Extracts a signal) of 75MHz + ΔMHz + 2f _sc, a BPF circuit 109 to output as a local signal, an amplifier circuit 110 for amplifying the local signal output from the BPF circuit 109, a local signal output from the amplifier circuit 110 BPF circuit 1 for removing harmonic components
11, a mixer circuit 89 that mixes a local signal output from the BPF circuit 111 with an IF signal (video carrier component) having a specified frequency f _v output from the TV tuner 2 to generate an IF beat signal. A BPF circuit 90 that extracts a difference frequency component included in the IF beat signal output from the mixer circuit 89 and generates a carrier IF signal having a frequency twice as high as the color subcarrier frequency in synchronization with the clock signal; Have. The above mixer circuit 87
, A BPF circuit 109, an amplifying circuit 110, a BPF circuit 111, a mixer circuit 89, and a BPF circuit 90.

In this case, the carrier reproducing circuit 86
A narrow-band BPF circuit 112 for extracting a frequency component near a video carrier of an IF signal (video carrier component) having a specified frequency f _v output from the tuner 2, and a narrow-band BPF circuit 112 output from the narrow-band BPF circuit 112 A comparator that compares the frequency component near the video carrier with a preset threshold value, thereby eliminating the amplitude change, suppressing the modulated wave component near the carrier, and reproducing a substantially unmodulated rectangular wave carrier signal. The circuit 113 and a rectangular wave-like carrier signal output from the comparator circuit 113 are subjected to band-pass filtering to remove unnecessary harmonic components other than the carrier signal and to output a sine wave signal (indicating a carrier of the IF signal). BPF for generating carrier signal)
And a circuit 114.

The synchronization frequency conversion circuit 8
When an IF signal (video carrier component) of a specified frequency f _v output from the TV tuner 2 is input, the IF signal is sequentially subjected to a narrow-band band-pass filtering process, a comparator process, and a band-pass filtering process. , A sine wave signal (carrier signal) indicating the carrier of the IF signal, and supplies this to the mixer circuit 87.

Thus, in the frequency conversion / clock generation circuit 3, the IF output from the TV tuner 2 is provided in the same manner as the frequency conversion / clock generation circuit 3 shown in FIG.
Even if the frequency of the signal changes, the difference frequency of the IF beat signal output from the mixer circuit 89 does not change, so that the color subcarrier frequency f _sc (about 3.58 MHz)
It is possible to generate a digital IF signal having a frequency 2f _sc twice as large as that of z).

In the frequency conversion / clock generation circuit 3 as well, a BPF circuit is arranged at an appropriate position to prevent a loop from occurring. Or interference can be prevented.

[0121]

As described above, according to the present invention, the circuit scale can be reduced, real-time signal processing can be realized, and the operation speed can be reduced by introducing down sampling. As a result, the entire circuit can be easily made into an LSI, and even in a home-use receiver, E
It is possible to perform the interference cancellation of the sport.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of the entire configuration of an E-spot interference canceller using a digitized E-spot interference canceller according to the present invention.

FIG. 2 shows a digitized E-spot interference interference elimination circuit 4 shown in FIG. 1 which is integrated into an LSI to increase the number of taps of a frequency / phase shift detection / correction circuit, a cancellation circuit, etc. A / D conversion circuit, D /
FIG. 3 is a block diagram showing an example of a digitized E-spot interference interference removal basic circuit having an A conversion circuit and reducing the number of terminals of an LSI chip.

FIG. 3 is a block diagram illustrating an example of an external carrier reproduction circuit that supplies a local signal to the A / D conversion circuit illustrated in FIG. 2;

FIG. 4 is a schematic diagram for explaining an operation of the external carrier reproducing circuit shown in FIG. 3;

FIG. 5 is a block diagram illustrating a detailed circuit configuration example of a local signal circuit illustrated in FIGS. 1 and 2;

FIG. 6 is a block diagram illustrating a detailed circuit configuration example of the quadrature synchronous detection circuit illustrated in FIGS. 1 and 2;

FIG. 7 is a schematic diagram showing the principle of quadrature synchronous detection used in the second example of the quadrature synchronous detection circuit shown in FIGS. 1 and 2;

8 is a block diagram showing a detailed circuit configuration example of a quadrature synchronous detection circuit using the principle of quadrature synchronous detection shown in FIG. 7;

FIG. 9 is a block diagram showing a detailed circuit configuration example of the frequency / phase shift detection and correction circuit shown in FIGS. 1 and 2;

FIG. 10 is a block diagram showing another example of the circuit configuration of the frequency / phase shift detection and correction circuit shown in FIGS. 1 and 2;

11 is a block diagram showing a detailed circuit configuration example of a complex limiter circuit used in each of the frequency / phase shift detection circuits shown in FIGS. 9 and 10. FIG.

12 is a block diagram showing another example of the circuit configuration of the complex limiter circuit used in each of the frequency / phase shift detection circuits shown in FIGS. 9 and 10. FIG.

FIG. 13 is a block diagram showing a detailed circuit configuration example of a phase rotation circuit used in each frequency / phase shift correction circuit shown in FIGS. 9 and 10;

FIG. 14 is a block diagram showing another example of the digitized E-spot interference rejection basic circuit used in the present invention.

FIG. 15 is a block diagram illustrating a detailed circuit configuration example of the frequency conversion / clock generation circuit illustrated in FIG. 1;

16 is a block diagram showing a detailed circuit configuration example of the frequency conversion / clock generation circuit shown in FIG.

FIG. 17 is a block diagram showing a basic configuration example of a conventional E-spot interference canceller using a method based on quadrature synchronous detection and Hilbert transform.

18 is a schematic diagram showing an operation example of the quadrature synchronous detection circuit shown in FIG.

19 is a schematic diagram showing an operation example of the quadrature synchronous detection circuit shown in FIG.

20 is a schematic diagram showing an operation example of the quadrature synchronous detection circuit shown in FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 ESPO interference interference removal device 2 TV tuner 3 Frequency conversion / clock generation circuit 4 Digitized ESPO interference interference removal circuit 4 a Digitized ESPO interference interference removal basic circuit 5 D / A conversion circuit 6 Reference signal reproduction circuit 7 Clock PLL Circuit 8 Synchronization frequency conversion circuit 9, 10 A / D conversion circuit 11 Local signal circuit 12 Step Nyquist filter circuit 13 Quadrature synchronization detection circuit 14, 49 Down sampling circuit 15 Frequency / phase shift detection correction circuit 16 Cancel circuit 17 Interference wave detection Filter coefficient control circuit 18 Hilbert transform / adaptive filter circuit 19, 27, 44, 45, 69, 71 Delay circuit 20, 63, 64, 67 Addition circuit 21 Carrier reproduction circuit, 22, 112 Narrow band BPF circuit 23, 113 Comparator circuit 24, 26, 85, 114 BPF circuit 25 Hilbert conversion circuit 28, 30, 59, 60, 61, 62, 65, 66, 8
0, 81 Multiplication circuit 29, 31 LPF circuit 32 Zero data circuit 33, 35 Latch circuit 34 Sign inversion circuit 36 Switching control circuit 37, 38, 76, 77, 97, 98 Switch circuit 39, 40 Band limiting filter circuit 41 Complex limiter Circuits 42, 43 Narrow band filter circuit 46 Phase rotation circuit 47 Frequency / phase shift detection circuit 48 Frequency / phase shift correction circuit 50, 51 Narrow band LPF circuit 52 Up sample circuit 53, 54, 55, 57, 82, 83 Sample rate Conversion circuits 56, 58 Interpolation filter circuits 68 Route calculation circuits 70, 72, 79 Division circuits 73, 74 Absolute value circuits 75 Comparison circuits 78 Function generation circuits 84 Clock PLL main circuit circuits 86 Carrier reproduction circuits 87, 89 Mixer circuits (synchronization) Frequency conversion main circuit) 88, 90, 10 , 111 BPF circuit (synchronization frequency conversion main body circuit) 91 envelope detection circuit 92 LPF circuit (horizontal frequency signal reproduction circuit) 93 synchronization separation circuit (horizontal frequency signal reproduction circuit) 94 equivalent pulse removal circuit (horizontal frequency signal reproduction circuit) 95 BPF circuit for f _sc (color subcarrier frequency signal reproduction circuit) 96 Burst lock PLL circuit (color subcarrier frequency signal reproduction circuit) 99 Phase comparator circuit 100 Loop filter circuit 101 VCXO circuit 102, 104, 106 Buffer circuits 103, 105, 107 1/2 frequency dividing circuit 108 1/455 frequency dividing circuit 110 Amplifier circuit (Synchronization frequency conversion main circuit)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yutaka Orihara 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Japan Broadcasting Corporation Research Institute (72) Inventor Hide Takechi 1-10-11 Kinuta, Setagaya-ku, Tokyo No. Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Naohiko Iosa 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Research Institute (72) Inventor Hiroyuki Hamazumi Kinutaichi Setagaya-ku, Tokyo Chome 10-11, Japan Broadcasting Corporation Research Institute (72) Inventor Yoshimichi Otsuka 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Research Institute

Claims (10)

[Claims] 1. A step Nyquist filter circuit for pre-processing a digital IF signal output from an A / D conversion circuit operating with a clock signal having a frequency eight times the color subcarrier frequency, and an output from the step Nyquist filter circuit Quadrature synchronous detection circuit that performs quadrature synchronous detection on the preprocessed digital IF signal to be generated to generate an in-phase output baseband signal and a quadrature output baseband signal; and an in-phase output baseband output from the quadrature synchronous detection circuit. A down-sampling circuit that down-samples the signal and the quadrature output baseband signal to lower the clock frequency to generate an in-phase output signal and a quadrature output signal; and an in-phase output signal output from the down sampling circuit.
A frequency / phase shift detection / correction circuit for correcting a frequency shift and a phase shift of the quadrature output signal to generate an I-axis output signal and a Q-axis output signal completely separated into an I-axis and a Q-axis; A Q-axis side output signal output from the frequency / phase shift detection and correction circuit is subjected to Hilbert transform processing and adaptive filtering to extract an interference wave component, and the frequency / phase shift detection correction is performed using the interference wave component. A cancellation circuit for canceling an interference wave component of an I-axis side output signal output from the circuit. 2. The digitized E-spot interference rejection circuit according to claim 1, wherein the carrier frequency of the digital IF signal input to the step Nyquist filter circuit is twice the color subcarrier frequency f _sc , A digital E-spo interference canceller circuit, wherein the frequency of a clock signal is eight times the color subcarrier frequency f _{sc and} the digital IF signal and the clock signal are synchronized. 3. The digitalized E-spot interference canceller according to claim 1, wherein the carrier frequency of the digital IF signal and the frequency of the clock signal are in a one-to-four relationship, and synchronization of the quadrature synchronous detector is performed. The detection operation is represented by a sequence of {1, 0, -1, 0} and {0,
A digitized E-spo interference canceller, characterized in that the digital IF signal is subjected to quadrature synchronous detection by driving a switch circuit in each of the sequences, assuming multiplication by a sequence of −1, 0, 1}. 4. The digitized E-spot interference canceller according to claim 1, wherein the input local signal is subjected to a Hilbert transform process.
Performing a band-pass filtering process to generate an orthogonal local signal, and delaying the local signal by a delay amount according to the delay amount in the Hilbert transform process and the delay amount in the band-pass filtering process,
A digitized E-spot interference canceller, comprising: a local signal circuit for generating an in-phase local signal and supplying the same to the quadrature synchronous detection circuit. 5. The digitized E-spot interference cancellation circuit according to claim 1, wherein the frequency / phase shift detection and correction circuit limits a band of the input in-phase output baseband signal and quadrature output baseband signal. Processing, complex limiter processing,
A frequency / phase shift detection circuit for performing I-axis side correction signal and Q-axis side correction signal by performing narrow band processing; delay processing for the in-phase output baseband signal and the quadrature output baseband signal; A frequency / phase shift correction circuit for performing a phase rotation process using the correction signal and the Q axis side correction signal to generate an I axis output signal and a Q axis output signal in which the frequency shift and the phase shift are corrected. A digitized E-spot interference canceller circuit. 6. The digitized E-spot interference canceller according to claim 5, wherein the complex limiter circuit for performing the complex limiter processing comprises: a band-limited in-phase output baseband signal; and a band-limited quadrature output baseband. An absolute value circuit for obtaining an absolute value of a signal; a comparison circuit for comparing each absolute value output from the absolute value circuit; and a function signal corresponding to each of the absolute values based on a comparison result of the comparison circuit. A function generating circuit and a function signal output from the function generating circuit are used to divide the larger one of the absolute values to obtain two orthogonal signals of 2
A dividing circuit for obtaining a coefficient for keeping the vector length of the sum of the products constant, and a coefficient obtained by the dividing circuit multiplied by each of the in-phase output baseband signal and the quadrature output baseband signal to obtain an I-axis side correction signal And a multiplication circuit for obtaining a Q-axis side correction signal. 7. The digitalized E-spot interference canceller according to claim 1, wherein an output signal of a TV tuner is taken in as an analog circuit for synchronizing a video carrier of an input IF signal with the clock signal. A reference signal reproduction circuit for reproducing a reference frequency signal, a clock PLL circuit for generating a clock signal based on the reference frequency signal output from the reference signal reproduction circuit, and a clock signal output from the clock PLL circuit. And a synchronizing frequency conversion circuit for converting the frequency of the IF signal. 8. The digitized E-spo interference removal circuit according to claim 7, wherein the reference signal reproducing circuit detects an image carrier of the IF signal by an envelope to generate a baseband signal. A low-pass filtering process with a cutoff frequency of about 200 kHz, a sync separation process, and an equivalent pulse removal process are performed on the baseband signal output from the detection circuit and the envelope detection circuit, and the horizontal frequency (f _h ) And a baseband signal output from the envelope detection circuit are subjected to a color subcarrier bandpass filtering process and a burst lock PLL process to obtain a color subcarrier frequency (f _sc ). Color subcarrier frequency signal reproduction circuit for reproduction And supplying either the horizontal frequency signal obtained by the horizontal frequency signal reproduction circuit or the color subcarrier frequency signal obtained by the color subcarrier frequency signal reproduction circuit to the clock PLL circuit. Digitized Espo interference jamming elimination circuit. 9. The digitized E-spo interference removal circuit according to claim 7, wherein the synchronization frequency conversion circuit performs a narrow-band band-pass filtering process, a comparator process, and a band-pass filter on an output signal of a TV tuner. Performing a process to generate a carrier signal; and a carrier signal output from the carrier reproduction circuit and a frequency f _sc of a color subcarrier frequency signal output from the clock PLL circuit. A local signal having a required frequency is mixed with a local signal having a frequency to generate a mixed signal, and the mixed signal is subjected to band-pass filtering for extracting a sum frequency component to generate a local signal having a required frequency. The frequency of the output signal of the TV tuner is converted by using the Digitizing E sports interference interference rejection circuit comprising the a synchronization frequency converter body circuit to obtain a VSB-AM modulated wave of the picture carrier with wavenumber. 10. The digitized E-spot interference canceller according to claim 1, wherein the frequency / phase shift detection and correction circuit limits a band of the input in-phase output baseband signal and quadrature output baseband signal. Provide a down-sampling circuit between the band-limiting filter circuit that performs the processing and the complex limiter circuit that performs the complex limiter processing, down-samples the band-limited in-phase output baseband signal and the quadrature output baseband signal, An I-axis side correction signal supplied to the complex limiter circuit and output from the complex limiter circuit;
An up-sampling circuit is provided after a narrow band filter circuit that performs narrow band filtering on the Q axis side correction signal, and the I axis side correction signal narrowed by the narrow band filter circuit, the Q axis A digitized E-spot interference canceller, wherein the clock frequency of the side correction signal is restored.