JPH10301851A - Method and system for speculatively supplying cache memory data inside data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide improved method and system for sharing cache memory data by reading requested data from a cache memory inside a processor before composite responses are returned from all the processors inside a data processing system to the processor. SOLUTION: The data processing system is provided with at least one CPU 11a-11n and provided with at least one each of primary cache 12a 12n and secondary cache 13a-13n and one high performance I/O device 16a-16n. In response to the request of the data by the high performance I/O device 16a-16n inside the data processing system, an intervention response is issued from the CPU 11a-11n provided with the requested data inside the data processing system. Then, the requested data are read from the secondary cache 13a-13n inside the CPU 11a-11n before the composite response is returned from all the CPUs 11a-11n inside the data processing system to the CPU 11a-11n.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a method and system for sharing cache memory data, and more particularly to a method and system for sharing cache memory data between a processing unit and an I / O device in a data processing system. And, more particularly, to a method and system for speculatively supplying cache memory data from a processing device in a data processing system to an intelligent (intelligent) I / O device.

[0002]

2. Description of the Related Art A data processing system includes at least one processing unit, system memory, and various I / O devices. The processing unit may include a plurality of registers for executing program instructions and an execution unit. The processing device generally has a primary cache (also referred to as a level 1 cache or an L1 cache) such as an instruction cache or a data cache realized by using a high-speed memory. Further, the processing unit may include a secondary cache (also called a level 2 cache or L2 cache) to support the primary cache as described above.

[0003] Normally, transferring data from one processing unit to another processing unit or I / O device on a system bus without going through system memory is called intervention.
The intervention protocol is based on the processing unit or I / O in the system.
Read request or scheduled change read (R
WITM) Improves system performance by reducing the number of times system memory must be accessed to satisfy a request.

[0004] Generally, pending read /
When there is an RWITM request, another processing unit connected to the system bus and holding the requested data in its cache can supply the data to the requesting I / O device. In a conventional intervention protocol, a processing unit whose data is in its cache, before issuing a data bus request to supply data from that cache,
Wait for a "composite" response from all processors in the system.

At the same time, the traditional intervention protocol is "retry"
Any read / RWITM request that is compatible with the mechanism and is satisfied by the intervention can be interrupted by a "retry" from any processing unit on the system bus. If one processor responds with an intervention and the other responds with a "retry", the retry response automatically overrides the intervention response. As a result, if a retry request by a processor on the system bus is pending, the processor containing the data will not issue a data bus request.

[0006] From the processing unit in the data processing system,
It would be desirable to provide an improved provisioning mechanism where intervention data is provided to the requesting I / O device in a manner that is less affected by "retry".

[0007]

It is an object of the present invention to provide an improved method and system for sharing cache memory data.

It is another object of the present invention to provide an improved method and system for sharing cache memory data between a processing unit and an I / O device in a data processing system.

It is another object of the present invention to provide an improved method and system for speculatively providing cache memory data from a processing unit in a data processing system to a sophisticated I / O device.

[0010]

In accordance with the method and system of the present invention, a data processing system includes at least one processing unit, each processing unit having at least one cache memory and at least one sophisticated I / O unit. Have. In response to a request for data by a sophisticated I / O device in the data processing system, an intervention response is issued from the processing device having the requested data in the data processing system. The requested data is then read from the cache memory in the processing device before the composite response from all the processing devices in the data processing system returns to the processing device.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention can be realized in a data processing system having at least one cache memory. It will also be appreciated that the present invention is applicable to various multiprocessor data processing systems where each processor has a primary cache and a secondary cache.

Reference is made to the figures, in particular to FIG. FIG. 1 shows a block diagram of a data processing system 10 to which the present invention can be applied. The data processing system 10 includes a plurality of central processing units (C
PU) 11a to 11n;
n each include a primary (L1) cache. As shown in the figure, the CPU 11a stores the primary cache 12a in the CPU 1
1n includes the primary cache 12n. Primary cache 1
Each of 2a to 12n may be a sectorized cache.

The CPUs 11a to 11n are connected to secondary (L2) caches 13a to 13n, respectively. 2
Each of the next caches 13a to 13n may be a sectorized cache. CPUs 11a to 11n, primary caches 12a to 12n, and secondary cache 13a
13n are connected to each other and to the system memory 14 via an interconnect 15. The interconnect 15 is a bus or a switch. The high-performance I / O devices 16a to 16n are also connected to the interconnection unit 15. These advanced I / O devices 16a to 16n have a function of starting data transfer with the system memory 14. Various adapters used for communication with other data processing systems via a network such as an intranet or the Internet can be added to the high-performance I / O devices 16a to 16n.

As a preferred embodiment of the present invention, a CPU,
The secondary cache and the secondary cache, for example, the CPU 11a, the primary cache 12a, and the secondary cache 13a shown in FIG. 1 can be collectively referred to as a processing device. A preferred embodiment of the data processing system is shown in FIG.
It is understood that the present invention can be implemented in various system configurations. For example, the CPUs 11a to 11n may have three or more levels of cache memories.

Please refer to Table 1. A set coherency response from a processing unit according to a prior art intervention protocol is shown. After an I / O device in a multiprocessor data processing system issues a read request or a read-to-change (RWITM) request on the system bus, the processing unit in the system, after a snoop, responds to one of the responses according to Table 1. Can be issued.

[Table 1]

As shown in Table 1, the coherency response takes the form of a 3-bit snoop response signal, where each coherency response is defined as described herein. These signals are encoded and the snoop result is shown after the address holding time. Each response also has a priority value associated with it,
This allows system logic to determine which coherency response has priority when formulating one snoop response signal to return to all processing units and all I / O devices on the system bus. For example, if one processor responds with a shared intervention response (priority 3) and another responds with a retry response (priority 1), the system logic may send a retry coherency response to the requesting processor and To return to all other processing units connected to the system bus,
The processing unit of the retry response is given priority. This system logic can reside in various components in the system, such as a system controller or memory controller.

[0017] Several well-known mechanisms may be employed to ascertain which cache (of the processing unit) the requested data "owner" is and thus is eligible to supply the data. In the conventional MESI protocol, if the cache holds the requested data in a "modified" or "exclusive" state, this is the only cache in the system that contains a valid copy of the data. ,, obviously means the owner. However, if the cache holds the requested data in a "shared" state, this means that the data should also be held in at least one other cache in the system. Thus, potentially, any of the two or more caches can supply data. In such cases, several options are available to determine which cache is the source.

Referring to FIG. A block diagram of a typical data processing system is shown to illustrate a prior art supply mechanism. For example, the advanced I / O device 24 issues a read request or an RWITM request on the system bus 23, and stores the I / O request in the L2 cache of the processing device 21.
It is assumed that there is data requested by the / O device 24.
Further, it is assumed that the L2 cache in the processing device 20 is in the "invalid" state, the L2 cache in the processing device 21 is in the "changed" state, and the L2 cache in the processing device 22 does not have the requested data. The subsequent sequence of processing is handled by the L2 cache controller of each processing unit to perform source intervention as described in the prior art.

Read / RWIT issued by I / O device 24
The M request is sent from the system bus 23 to the processing device 2
1, "Snoop" by the processing unit 22 and the processing unit 23. A lookup of the L2 cache directory is performed on each of the processing units 21 to 23 to determine whether the requested data exists in the L2 cache. Since the requested data exists in the processing unit 21, an intervention response is issued by the processing unit 21, and the finite state machine in the processing unit 21 is dispatched to control the subsequent processing. When the data in the L2 cache of the processing device 21 is in the “changed” state, the processing device 21 issues a change intervention coherency response. Data in the L2 cache of the processing device 21 is “shared” or “exclusive”
, The processing unit 21 issues a shared intervention coherency response. Processors 20 and 22 each send a null coherency response because the L2 cache in processor 20 is in an "invalid" state and there is no requested data in the L2 cache in processor 22.

After issuing the intervention response, the processor 21 prepares for the composite response. The composite response basically includes, in this example, a coherency response from itself and a coherency response from the processing units 20, 22 and the I / O device 24. If the returned composite response is a change intervention coherency response, the processing unit 21 can start supplying the requested data from its L2 cache. Processing device 20 or processing device 22
If, for any reason, a retry is requested, under the established intervention protocol, the retry request takes precedence (ie, the provisioning sequence does not proceed). For example, processor 22 may be in a snoop queue busy state and issue a retry request.

Whether the data in the L2 cache of the processing unit 21 has been changed since the start of the snoop operation,
Or, if not present in the L1 cache (ie, not L1 inclusive), the processing unit 21 can initiate a system bus request to the system bus arbiter (usually, the requested data is initiated by the system bus request). Must be read into the buffer by the L2 cache controller before it can be executed). Otherwise, the L1 cache of the processing unit 21 is flushed and invalidated before the system bus request is issued (that is, the changed data of the L1 cache is written back to the L2 cache, and the copy of the L1 cache is invalidated). Do). However, the L1 cache of the processing unit 21 is "shared"
If so, all that is required before invalidating the data bus request is to invalidate the L1 cache.

Next, the processor 21 waits for the right to use the system bus to return. The actual supply of data to the I / O device 24 begins after the use of the data bus has been granted. When the supply is completed, the L2 cache of the processing unit 21 changes from the "changed" state to the "shared" state for a read request and the "invalid" state for an RWITM request. The state of the L2 cache of the processing devices 20 and 22 does not change.

Referring to FIG. A flowchart of high-level logic for speculatively providing cache memory data from a processing unit in a data processing system to an I / O device in accordance with a preferred embodiment of the present invention is shown. Beginning at block 30, a read / RWITM request is snooped from the system bus by all processing units in the system (block 31). A lookup of the L2 cache directory is performed and a check is made by each processing unit whether the requested data is present in the L2 cache (block 32). A null coherency response is issued by all processors (such as processors 20 and 22 of FIG. 2) that do not hold the requested data (block 33) and the process proceeds to block 99.
Ends with On the other hand, a processing device (such as the processing device 21 in FIG. 2) holding the requested data issues an intervention coherency response (block 34).

After issuing the intervention coherency response, the intervening processing unit must perform certain cache management tasks (block 35). These tasks are L1
The operation of flushing and invalidating the data copy of the L1 cache of the intervening processing unit if the data copy of the cache has been changed, or simply the intervening processing unit if the data copy of the L1 cache has not been changed. Invalidating the L1 cache data copy.

Thereafter, the requested data is read from the L2 cache of the intervening processing unit, preferably into a buffer, and a request for a system data bus is issued to the system bus arbiter (block 36). A check is made as to whether use of the system data bus is authorized (block 37). If not,
A check is made to see if a composite coherency response has returned (block 38). If no combination coherency response has been returned, the process returns to block 37.

However, if the use of the system data bus is permitted, the supply of the requested data can be initiated from the intervening processing unit by driving the requested data to the system data bus ( Block 3
9). It is also checked at this point if a composite coherency response has already been returned (block 40).
If the composite coherency response has not yet returned, the process continues to wait for the composite coherency response to return while the requested data continues to be supplied to the system bus.

After returning the composite coherency response, a check is made as to whether it is a "retry" (block 4).
1). If the composite coherency response is a retry, the system
If the use of the data bus has not yet been granted, the system data bus request is canceled or the requested data supply is immediately aborted (block 42). If the feed has already been completed at this point, the result will be discarded due to the retry coherency response. If the composite coherency response is not a retry, if the supply of the requested data has not been completed, it continues until it is completed. Finally, the status of the intervening processing unit's L2 cache is updated (block 43) and the process ends at block 99.

As noted above, the present invention provides a method for speculatively providing cache memory data from a processing unit in a data processing system to a sophisticated I / O device. Specifically, in the disclosure of the present invention, the data requested before the composite coherency response returns is transmitted to the L
2 describes an example of a new intervention read from the cache.

The present invention has distinct advantages in performance over the prior art. Read / RWI on system bus
This is because the delay between the TM request and the sampling of the composite response is several clock cycles of the system bus. Thus, by requiring the requested data to be read from the L2 cache of the intervening processor before the composite coherency response is received, the intervention latency is significantly reduced and the overall system performance is greatly improved. .

In summary, the following matters are disclosed regarding the configuration of the present invention.

(1) I / O from a processing unit in a data processing system including at least one cache memory
A method of speculatively providing cache memory data to a device, the method comprising: in response to a request for data by the I / O device, issuing an intervention response by a processing device having the requested data; Reading the requested data from a cache memory in the processing device before the composite response from all the processing devices in the data processing system returns to the processing device. (2) The method according to (1), wherein the reading step includes reading the requested data from a cache memory in the processing device into a buffer. (3) The method according to (1), wherein the request includes a read request or a read request to be changed. (4) The method according to (1), further comprising the step of stopping the reading step if the returned composite response is a retry. 5. The method of claim 1, further comprising requesting a system bus to provide the requested data by the processing device before the composite response returns. (6) The method of (5), comprising providing the requested data by the processing device before the composite response returns. (7) A processing device having a cache memory capable of speculatively supplying data to an I / O device in the data processing system, wherein the processing device has a cache memory in response to a request for data by the I / O device. Means for issuing an intervention response from a processing unit having the requested data of
Means for reading the requested data from a cache memory in the processing device before the composite response from all processing devices returns to the processing device. (8) The processing device according to (7), wherein the reading unit includes a unit that reads the requested data from a cache memory in the processing device to a buffer. (9) The processing device according to (7), wherein the request includes a read request or a read request to be changed. (10) The processing device according to (7), wherein the processing device includes means for stopping reading by the reading means when the returned composite response is a retry. (11) The processing device according to (7), wherein the processing device includes means for requesting a system bus to supply the requested data by the processing device before returning the composite response. (12) The processing device according to (11), wherein the processing device includes means for supplying the requested data by the processing device before the composite response returns.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data processing system to which the present invention can be applied.

FIG. 2 is a block diagram of an exemplary data processing system showing a supply mechanism according to the prior art.

FIG. 3 is a high level logic flowchart illustrating a method for speculatively providing cache memory data from a processing unit in a data processing system to an I / O device in accordance with a preferred embodiment of the present invention. It is.

[Explanation of symbols]

10 Data processing system 11a, 11b, 11c, 11d, 11e, 11f, 1
1g, 11h, 11i, 11j, 11k, 11l, 11
m, 11n Central processing unit (CPU) 12a, 12b, 12c, 12d, 12e, 12f, 1
2g, 12h, 12i, 12j, 12k, 121, 12
m, 12n Primary cache 13a, 13b, 13c, 13d, 13e, 13f, 1
3g, 13h, 13i, 13j, 13k, 131, 13
m, 13n Secondary cache 14 System memory 15 Interconnections 16a, 16b, 16c, 16d, 16e, 16f, 1
6g, 16h, 16i, 16j, 16k, 16l, 16
m, 16n, 24 Advanced I / O device 20, 21, 22 Processing device 23 System bus

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor John Stephen Dodson 78660 USA, Bell Rock Circle, Ferragerville, Texas 1205 (72) Inventor Jerry Don Luis United States 78681, Round Rock, Texas , Arrowhead Circle 3409

Claims (12)

[Claims] 1. A method for speculatively supplying cache memory data to an I / O device from a processing device including at least one cache memory in a data processing system, the method comprising: Issuing an intervention response by the processing device having the requested data in response to the request for the data processing system, and before the combined response from all the processing devices in the data processing system returns to the processing device, Reading the read data from a cache memory in the processing unit. 2. The method of claim 1, wherein said reading step comprises reading said requested data from a cache memory in said processing unit to a buffer. 3. The method of claim 1, wherein the request comprises a read request or a read to change request. 4. The method of claim 1, further comprising the step of stopping said reading step if the returned composite response is a retry. 5. The system of claim 1 wherein said requested data is provided by said processing unit before said composite response returns.
The method of claim 1, comprising requesting a bus. 6. Providing the requested data by the processing device before the composite response returns.
The method of claim 5. 7. A processing device having a cache memory capable of speculatively supplying data to an I / O device in a data processing system, wherein the data processing device responds to a request for data by the I / O device. Means for issuing an intervention response from the processing device having the requested data in the system; and a cache memory in the processing device before the combined response from all the processing devices returns to the processing device. Means for reading from a processing device. 8. The processing apparatus according to claim 7, wherein said reading means includes means for reading said requested data from a cache memory in said processing apparatus into a buffer. 9. The processing device according to claim 7, wherein said request includes a read request or a read request to be changed. 10. The processing apparatus according to claim 7, wherein said processing apparatus includes means for stopping reading by said reading means when the returned composite response is a retry. 11. The processing unit of claim 7, wherein said processing unit includes means for requesting a system bus to provide said requested data by said processing unit before said composite response returns. 12. The processing device according to claim 11, wherein said processing device includes means for supplying said requested data by said processing device before said composite response returns.