JPH10303367A - Semiconductor integrated circuit device and clock signal supplying method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily reduce clock skew without requiring any complicated production process. SOLUTION: Clock signals are transmitted from a clock signal source provided above a semiconductor chip 100 by radio waves, and the transmitted clock signals are respectively received by a plurality of reception antennas 120 and reception circuits 121, which are provided on the semiconductor chip 100, and reproduced into clock signals. The reproduced clock signals are respectively supplied to an internal circuit on the semiconductor chip 100 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and a clock signal supply method for supplying a clock signal to a circuit on a semiconductor chip.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a configuration of a conventional semiconductor chip. In the example of FIG. 6, the semiconductor chip 10
0, four circuit blocks 101 are provided, and a bonding pad 10 is provided at one end of the semiconductor chip 100.
7. An input buffer 108 is provided. A clock buffer 102 is provided at an input of each circuit block 101, and four clock buffers 103 to 106 are connected to an output of the clock buffer 102.

[0005] A clock supplied from the outside is input from a bonding pad 107 to an input buffer 108, and is supplied from the input buffer 108 to each circuit block 101 through wiring branched in a tree shape. Further, the clock supplied to each circuit block 101 is supplied from the input buffer 102 to a plurality of clock buffers 103 to 106 through wiring distributed in a tree shape. By supplying a clock to each circuit block in this way,
The four circuit blocks 101 operate in synchronization with the supplied clocks.

In the semiconductor integrated circuit device shown in FIG. 6, a clock supplied from the outside is distributed from an input buffer 108 to each circuit block 101 through a tree-like wiring, and a clock buffer of each circuit block 101 is provided. Since the clock signal is supplied from the input buffer 108 to the plurality of clock buffers 103 to 106 through the tree-shaped wiring, the wiring length from the input buffer 108 to each of the circuit blocks 101 is different, and the supplied clock signal has a time difference (clock skew). ). This clock skew contributes to limiting the maximum operating clock frequency of the semiconductor integrated circuit device. Therefore, in order to operate a large-scale semiconductor integrated circuit device in synchronization with a high-speed clock signal, it is important to reduce clock skew.

Therefore, as shown in FIG.
In some cases, a main clock buffer 109 is provided at a substantially central portion of the 00, and a clock is supplied from the main clock buffer 109 to each circuit block 101 through an equal-length wiring. Further, in FIG. 7, the clock is supplied from the clock buffer 102 in each circuit block 101 to the plurality of clock buffers 103 to 106 through wires having the same length.

In the semiconductor integrated circuit device of FIG. 7, since the wiring lengths from the main clock buffer 109 to the respective circuit blocks 101 are substantially equal, the clock skew can be greatly reduced as compared with that of FIG. . However, in the configuration of FIG. 7, all wiring lengths must be adjusted to the longest wiring length, and this redundant wiring increases the total wiring length required for clock distribution.

This causes a problem that the power consumption is increased especially in a CMOS circuit in which the power consumption increases in proportion to the product of the clock frequency and the load capacitance value. Further, in order to make all the wiring lengths uniform, a special wiring layer and a wiring channel region are required, which is disadvantageous in terms of manufacturing cost.

As a method of reducing clock skew, there is known a method of supplying a clock signal as an optical signal by blinking a light emitting element, as proposed in Japanese Patent Application Laid-Open No. Hei 4-313269. FIG. 8 shows a clock supply method described in the publication. In the figure, reference numeral 110 denotes a light emitting element serving as a clock supply source, and 111 denotes a printed board. A plurality of semiconductor chips 112 are provided on the printed board 111, and a light receiving element for receiving an optical signal from the light emitting element 110 is provided on each semiconductor chip 112. The optical signal received by the light receiving element is supplied to an internal circuit of the semiconductor chip 112 as a clock signal.

[0009]

Problems to be Solved by the Invention Japanese Patent Laid-Open No. 4-31326
In the clock supply method proposed in Japanese Patent Application Laid-Open No. 9, since a clock is supplied to an internal circuit on each semiconductor chip by an optical signal, clock skew between semiconductor chips can be reduced. However, the method described in the publication requires a light receiving element for receiving an optical signal transmitted from a clock signal source and converting the optical signal into an electric signal.

In general, it is possible to form a light receiving element monolithically on a compound semiconductor substrate, but for that purpose, a special process must be added. It is generally difficult to form an efficient light receiving element on a silicon substrate. Therefore, in this case, the light receiving element based on the compound semiconductor technology must be mixedly mounted on the silicon substrate by any method. In any case, the manufacturing process is complicated in order to form the light receiving element on the semiconductor chip. In addition, there is a problem that the manufacturing cost increases.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor integrated circuit device and a clock signal supply method capable of easily reducing clock skew without requiring any complicated manufacturing steps. I do.

[0012]

In order to achieve the above object, the present invention provides a receiving antenna for receiving a clock signal transmitted by radio waves from a clock signal source on a semiconductor chip. A plurality of receiving circuits for amplifying a signal received by a receiving antenna and reproducing the signal as a clock signal are provided.

According to the present invention, a clock signal is transmitted by radio waves from a clock signal source provided above a semiconductor chip, and the transmitted clock signal is transmitted to a plurality of receiving antennas and receiving circuits provided on the semiconductor chip. And reproduces the received clock signal, and supplies the reproduced clock signal to an internal circuit on the semiconductor chip.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
It is a figure showing an embodiment. In FIG. 1, the same parts as those of the conventional apparatus of FIGS. 6 and 7 are denoted by the same reference numerals. In FIG. 1, first, four circuit blocks 101 are provided on a semiconductor chip 100. In the vicinity of the center of each circuit block 101, the receiving antenna 1
20 is provided, and is configured to receive a clock signal transmitted by radio waves from a clock signal source provided above the semiconductor chip 100 as described later in detail.

Further, the weak signals (analog signals) received by the respective receiving antennas 120 are amplified by the receiving circuits 121 provided close to the respective receiving antennas 120, and are reproduced as clock signals having digital waveforms. The clock signal reproduced by each receiving circuit 121 is supplied to each circuit block via clock buffers 103 to 106.

FIG. 2 shows how a clock signal is transmitted from a clock signal source to each circuit block. In FIG. 2, the clock signal source 123 is provided above the semiconductor chip 100 (for example, on the back surface of the package lid).
The clock signal is transmitted by radio waves. In this case, by arranging the clock signal source 123 so that the linear distance between the clock signal source 123 and the receiving antenna 120 of each circuit block 101 is equal, the clock skew between each circuit block 101 is extremely reduced. It is possible.

FIG. 3 shows a specific example of the receiving circuit 121. In the example of FIG. 3, the multi-stage limiter amplifier 124
a to 124d are used. By using a multi-stage limiter amplifier in this manner, a signal captured by a receiving antenna can be easily amplified with a simple configuration and with low power consumption, and reproduced as a digital waveform clock signal. It should be noted that the limiter amplifier does not need to have multiple stages, and may be a single stage.

In this embodiment, since the clock signal is supplied from the clock signal source 123 to each circuit block by radio waves, not only the light receiving element is not required on the semiconductor chip but also the above-described clock skew is reduced. It is also possible to eliminate the need for equal-length wiring using redundant wiring for the purpose. In particular, this has the effect of reducing power consumption in CMOS circuits. Also, no special wiring layer or wiring channel for equal length wiring is required,
It is also possible to manufacture a semiconductor integrated circuit device at low cost.

FIG. 4 is a diagram showing a second embodiment of the present invention. In FIG. 4, a frequency divider (divide by N) 125 is provided at the output of the receiving circuit 121 of each circuit block 101. The clock signal obtained by each receiving circuit 121 is frequency-divided by N by a frequency dividing circuit 125, and then the clock signal is supplied to each circuit block 1 via clock buffers 103 to 106.
01 is supplied.

In this embodiment, the clock signal source 1
23, the frequency of the clock signal transmitted by radio waves is set to an integral multiple (N times) of the frequency of the clock signal used in each circuit block 101, and the frequency of the clock signal received by the receiving circuit 121 using the frequency dividing circuit 125 is set to N. Since the frequency is divided, the wavelength of the radio wave transmitted from the clock signal source 123 is 1 / N, and the size of the receiving antenna 120 can be reduced. However, in the present embodiment, a plurality of frequency dividing circuits 12
Although it is necessary to synchronize between the five, as shown in FIG. 4, a reset terminal 126 is provided in each of the frequency dividing circuits 125, and a common reset signal is supplied to the reset terminal 126 once when the system is started up. Semiconductor chip 100
The whole can be synchronized.

FIG. 5 is a diagram showing the configuration of the third embodiment of the present invention. In the first and second embodiments, since the clock signal is transmitted by radio waves from the clock signal source 123 above the semiconductor chip 100, the semiconductor chip 10
It is conceivable that this radio wave may cause electromagnetic interference to the circuit operation of 0.

Therefore, in the present embodiment, as shown in FIG. 5, the shield 127 is formed over almost the entire surface of the semiconductor chip 100 except for the area of the receiving antenna 120. As the shield 127, the uppermost wiring layer of the semiconductor chip 100 is used, and by using a ground pattern connected to a fixed potential of the uppermost wiring layer as a shield member, it is possible to avoid the above-described interference by radio waves. Can be. In this case, the shield member need not be the uppermost wiring layer, and another wiring layer may be used.

[0023]

As described above, the present invention has the following effects. (1) A clock signal is transmitted by radio waves from a clock signal source, and the transmitted clock signal is reproduced into a clock signal by a plurality of receiving antennas and receiving circuits on the semiconductor chip, and the reproduced clock signals are respectively reproduced on the semiconductor chip. Since the clock signal is supplied to the internal circuit, the clock skew can be easily and effectively reduced without the need for the redundant wiring as in the related art. Thus, a large-scale integrated circuit can be operated with a higher-speed clock signal. (2) Since no light receiving element is required on the semiconductor chip,
A special manufacturing process for forming the light receiving element on the chip can be eliminated. Therefore, the manufacturing process is not complicated, and it can be manufactured at low cost. (3) Since there is no increase in the total wiring length required for clock distribution due to redundant wiring, power consumption can be reduced, particularly in CMOS circuits. (4) Since no special wiring layer or wiring channel region is required to make all the wiring lengths uniform, the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a perspective view showing a state where a clock signal is transmitted by radio waves from the clock signal source of the embodiment of FIG. 1 to a circuit block on a semiconductor chip.

FIG. 3 is a diagram illustrating a specific example of a receiving circuit used in the embodiment of FIG. 1;

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram showing an example of a conventional semiconductor integrated circuit device.

FIG. 7 is a diagram showing another example of a conventional semiconductor integrated circuit device.

FIG. 8 is a diagram showing still another example of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor chip 101 circuit block 102 to 106 clock buffer 120 receiving antenna 121 receiving circuit 123 clock signal source 124 a to 124 d limiter amplifier 125 frequency divider 126 reset terminal 127 shield

Claims (9)

[Claims] 1. A receiving antenna for receiving a clock signal transmitted by radio waves from a clock signal source on a semiconductor chip, and a receiving circuit for amplifying a signal received by the receiving antenna and reproducing the signal as a clock signal. A plurality of semiconductor integrated circuit devices. 2. The semiconductor integrated circuit device according to claim 1, wherein the receiving antenna and the receiving circuit are arranged for each circuit block on the semiconductor chip. 3. The semiconductor integrated circuit device according to claim 2, wherein said receiving antenna is provided at a substantially central portion of a circuit block on said semiconductor chip. 4. The semiconductor integrated circuit device according to claim 1, wherein said receiving circuit is a limiter amplifier. 5. The clock signal source transmits a clock signal having a frequency N times the frequency of a clock signal used in a circuit on the semiconductor chip, and a reproduced clock signal is output to an output of the receiving circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein a frequency dividing circuit for dividing N by N is connected. 6. The semiconductor integrated circuit device according to claim 1, wherein a region other than the receiving antenna on the semiconductor chip is shielded by a shield member. 7. The semiconductor integrated circuit device according to claim 6, wherein said shield member is an uppermost wiring layer of said semiconductor chip. 8. A clock signal is transmitted by radio waves from a clock signal source provided above the semiconductor chip, and the transmitted clock signal is received by a plurality of receiving antennas and receiving circuits provided on the semiconductor chip. A clock signal supplied to the internal circuit on the semiconductor chip. 9. The clock signal supply method according to claim 8, wherein a linear distance between the clock signal source and the plurality of receiving antennas is set to be substantially equal.