JPH10312308A - Microcomputer and emulation device - Google Patents

Abstract

(57) [Problem] To provide the same function as in normal operation without increasing the circuit scale by an external circuit during emulation.
Provided are a microcomputer (microcomputer) that can easily realize the same operation, and an emulation device using the microcomputer. A microcomputer (2) includes a bus extension mode for enabling input / output of internal bus signals such as addresses, data, and control signals from a part of an external terminal (TGi) for a general-purpose IO port, and an external terminal different from the bus extension mode. It is configured to be able to set to an IO extension mode in which internal bus signals can be input / output via TGi. The two microcomputers 2a and 2b are
One is set to the bus expansion mode and the other is set to the IO expansion mode, and the internal bus signals input and output by the two microcomputers 2a and 2b are connected to each other, thereby eliminating the need for an external circuit such as discrete components. An emulation device 50 having the same function as the microcomputer 2 in the normal mode can be easily configured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a CPU, a memory, and a port group for inputting and outputting signals via external terminals, which are interconnected via an internal bus for transmitting addresses, data, and various control signals. A single-chip microcomputer and an emulation device configured by the microcomputer.

[0002]

2. Description of the Related Art Conventionally, in a single-chip microcomputer (hereinafter referred to as a microcomputer) having built-in peripheral circuits such as a CPU, a ROM, a RAM, and a timer, the size of a package is determined by the number of external terminals for inputting and outputting signals. Therefore, in order to reduce the size of the package, an external terminal for a control signal line (hereinafter, collectively referred to as an internal bus) for a data bus, an address bus, a read / write signal or the like is not assigned. .

In general, in a system configured using a CPU, for example, Japanese Patent Application Laid-Open No.
As described in Japanese Patent Application Laid-Open Publication No. H10-207, software development and hardware debugging are performed by emulating a CPU.

The emulation of the CPU is performed by a well-known in-circuit emulator (ICE) or the like.
Since this is performed using the data bus, address bus, and various control signal lines (that is, internal buses in the above-mentioned microcomputer) connected to U, these microcomputers, which are not assigned to external terminals, can be used for any purpose. An external terminal assigned as a general purpose IO port is configured to be switchable so as to be able to input and output either a signal as a general purpose IO port or a signal of an internal bus required for emulation, and this external terminal is used when emulation is performed. , So that signals from the internal bus are input and output.

An external circuit having a function equivalent to that of a general-purpose IO port lost for inputting / outputting an internal bus signal is prepared in advance by using discrete components or the like. Instead of replacing the lost general purpose IO port.

[0006]

However, in recent years, it has been practiced to add a function such as an edge detection function or a digital filter to a general-purpose IO port to enhance the function. If the general-purpose IO port is to be realized by external discrete components, the number of components is large, the circuit scale is large, and there is a problem that it takes time to manufacture the external circuit.

[0007] Even if such an external circuit is manufactured with a great deal of time, there is a difference in drive capability between the elements on the semiconductor chip and the discrete parts and the circuit configuration is different. The same function and the same operation as those built in
There was a problem that emulation with high reliability could not be performed.

The present invention has been made in order to solve the above problems.
It is an object of the present invention to provide a microcomputer capable of easily realizing the same function and the same operation as during normal operation without increasing the circuit scale by an external circuit during emulation, and an emulation device using the microcomputer. .

[0009]

According to the microcomputer of the present invention made to achieve the above object, when the normal mode is set by the mode setting means, all the original functions of the microcomputer become possible. , C
The PU, the memory, and the port group are connected to the internal bus, and signals of the port group are input and output from external terminals.

When the bus setting mode is set by the mode setting means, the first switching means prohibits the input / output of a signal through an external terminal by the first port group which is a part of the port group, and also controls the external port. Enables input / output of internal bus signals from terminals. That is, the setting is the same as that of the conventional microcomputer.

On the other hand, when the IO expansion mode is set by the mode setting means, the CPU disconnecting means and the memory disconnecting means disconnect the CPU and the memory from the internal bus, respectively, and the second switching means establishes a connection with the first port group. The input / output of a signal through an external terminal by a second port group, which is a part of a different port group, is prohibited, and a signal of an internal bus can be input / output from the external terminal. At this time, the first port group operates according to the internal bus signal input / output via the external terminal by the second switching means.

That is, in the IO expansion mode, the first port group, which cannot input / output signals via the external terminals due to the setting of the bus expansion mode, receives signals from the internal bus input / output via the external terminals. It is controllable. Therefore, according to the microcomputer of the present invention,
Using two of the microcomputers, one is set to the bus extension mode and the other is set to the IO extension mode, and the first switching means and the second switching means enable input / output via an external terminal. By connecting the external terminals so that the signals of the internal bus are input / output between the two microcomputers, the microcomputer set to the bus expansion mode loses the first signal.
The port group can be supplemented by the first port group of the microcomputer set to the IO expansion mode, and the emulation device that realizes the same function and the same operation as the normal mode can be easily formed without manufacturing an external circuit. Can be configured.

Here, the port (group) includes not only a port having input / output but also a port having only an input or only an output. A port which is normally used only for input or only for output includes an internal bus. When switching to input and output signals, both input and output may be enabled.

As one of the internal bus signals which can be input / output via the external terminal by the first switching means and the second switching means, the first switching means is used when executing control on the port group. Outputs an IO selection signal used to select the port group, and the second switching means
An O selection signal may be input.

The IO selection signal is generated by decoding an upper address in order to identify a port group from a memory or other peripheral circuits. In the IO extension mode, the IO selection signal is output via an external terminal. , There is no need to input the upper address, so that the number of internal bus signals input / output via external terminals can be reduced.

By the way, when a program is developed by emulation, the contents of the program are not fixed and the program is frequently changed. Therefore, the internal memory of the microcomputer, which is difficult to rewrite the program, is used. Instead, it is desirable to be able to use an external memory that can be easily rewritten.

In view of this, the mode setting means may be configured so as to be able to set an external memory mode in which the memory disconnecting means is also enabled when the bus extension mode is set. In the microcomputer of the present invention thus configured,
When the external memory mode is set by the mode setting means,
Since the memory connected to the internal bus is disconnected, an external memory controlled by a signal on the internal bus can be provided when configuring the emulation device.

When the external memory mode is provided as described above, the first switching means outputs one of the signals of the internal bus that can be input / output via the external terminal when the control of the memory is executed. May be configured to output a memory selection signal that is used to select.

In this case, it is not necessary to create a memory selection signal by decoding the upper address, and the external memory can be used only by connecting the signal lines.
The emulation device can be configured more easily.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a schematic internal configuration of a single-chip microcomputer (microcomputer) according to the present embodiment.

As shown in FIG. 1, the microcomputer 2 of this embodiment
Are external terminals TS1 to TSn for dedicated ports prepared in advance for specific use in order to input and output signals,
It has external terminals TG1 to TG64 for general-purpose IO ports that can be used by the user for any purpose, and external terminals TM0 and TM1 for setting a mode for setting an operation mode described later.

The microcomputer 2 includes a well-known CPU 4 that operates according to a program, a ROM 6 that stores programs and data necessary for operating the CPU 4,
RAM for temporarily storing the calculation result and the like of CPU 4
8 and a timer, an AD converter, etc., which are provided to realize a specific function, and are provided with external terminals TS1 to TS1 for dedicated ports.
A peripheral circuit 10 for inputting / outputting signals via TSn, an IO circuit 12 for inputting / outputting signals via external terminals TG1 to TG64 for general-purpose IO ports, an address bus 14 for interconnecting these components, Data bus 16 and CP
The read signal RD and the write signal WR output from U4 and the address signal A0 input via the address bus 14
To A15, a decoder 18 for generating various selection signals for specifying a control target, and a mode signal generation circuit 20 for generating a mode selection signal to be described later according to the setting of the mode setting external terminals TM0 and TM1. And built-in.

The CPU 4 operates on the address bus 1 via a buffer circuit BF1 which can switch between passing and non-passing of signals.
The CPU 4, the ROM 6, the RAM 8, and the peripheral circuit 10 are similarly connected to the data bus 16 via buffer circuits BF2 to BF5.

Here, the mode signal generation circuit 20 sets T.sub.0 in accordance with the settings of the mode setting external terminals TM0 and TM1.
When both M0 and TM1 are at the low level (00), the normal mode is set. When TM0 is at the low level, TM1 is at the high level (01), the IO expansion mode is set. When TM0 is at the high level (1X), the bus expansion mode is set. When the bus extension mode and TM1 are at the high level (11) is the external bus mode, the mode selection signal Mb for the bus extension mode and the mode selection signals Mi and I for the IO extension mode.
It is configured to generate the mode selection signal Me in the case of the O extension mode or the external bus mode.

The decoder 18 is also provided with chip select signals CSROM, CSRAM, CSIO and the like for ROM 6, RAM 8, IO circuit 12 and the like, based on upper addresses A5 to A15, as a selection signal for specifying a control target. Chip select signals CSXX, CSY
Y, CSZZ, and a ROM based on the chip select signal, the read signal RD, and the write signal WR.
6 read signal RDro, RAM8 read signal RDr
a, write signal WRra, read signal R of peripheral circuit 10
Dph, a write signal WRph, etc. are generated.

The buffer circuit BF1 is composed of a tri-state buffer having the mode selection signal Mi as a control input. When the mode selection signal Mi is at the high level (IO extension mode), the passage of the signal is inhibited, and the CPU 4 is addressed. It is configured to be disconnected from the bus 14. Each of the buffer circuits BF2 and BF5 includes a bidirectional tri-state buffer that receives a mode selection signal Mi as a control input and allows signals to pass in both directions according to read signals RD and RDph and write signals WR and WRph. When the selection signal Mi is at the high level (IO extension mode), the passage of the signal is prohibited and the CPU 4 and the peripheral circuit 10 are separated from the data bus 16.

On the other hand, the buffer circuit BF3 receives the mode selection signal Me as a control input and reads the read signal RDr of the ROM 6.
o, the buffer circuit BF4 includes a mode selection signal M
e is a control input, and is a tri-state buffer that allows signals to pass in both directions according to the read signal RDra and the write signal WRra of the RAM 8, and in each case, the mode selection signal Me has a high level (IO extension mode or external memory mode). Sometimes the passage of signals is prohibited, and ROM6 and RA
M8 is configured to be disconnected from the data bus 16.

Next, the IO circuit 12 is connected to the external terminals TG1 to TG1.
Individual circuit Ci provided for each TG 64 (i = 1 to 64)
And the individual circuits Ci to be controlled (especially, general-purpose IO ports)
And a selection signal generation unit 12a that generates a port selection signal CSPi for specifying

Among them, the selection signal generation unit 12a
As shown in the figure, the IO circuit 1 generated by the decoder 18
In accordance with the mode selection signal Mi, one of a chip select signal (hereinafter, referred to as an IO selection signal) CSIO for selecting the signal No. 2 and an IO selection signal CSIOin (described later) input via the external terminal TGi is selected. A multiplexer (MUX) 22 and a decoder 24 that generates a port selection signal CSPi for specifying a general-purpose IO port provided for each individual circuit Ci based on the signal selected by the MUX 22 and the lower address signals A0 to A4. And

In the MUX 22, the mode selection signal M
When i is at the High level (IO extension mode), an external IO selection signal CSIOin is selected and the mode selection signal M
When i is at the low level (other than the IO extension mode), the IO selection signal CSIO from the decoder 18 is selected. When the mode selection signal Mi is at the high level, the lower address A supplied from the address bus 14 will be described later.
0 to A4 are also signals input from outside via the external terminal TGi.

On the other hand, the individual circuit Ci is configured so that the external terminal TGi can be switched between the general-purpose IO ports P00 to P63 and the input / output of the internal bus signal. , Input-only, or output-only, the configuration is slightly different.

First, an external terminal T is used instead of the general-purpose IO port.
As shown in FIG. 3, the individual circuit Ci in which the internal bus signal S1 input / output via Gi is used for input / output,
An output buffer circuit 30 including a field effect transistor L1 that turns on when a w level is applied and a field effect transistor L2 that turns on when a High level is applied to a gate, a NAND circuit L3, a NOR circuit L4, and an inversion circuit L5. I have. In the output buffer circuit 30, the field effect transistors L1 and L2 are connected in series between the power supply and the ground, and the connection point of the two transistors L1 and L2 is connected as an output terminal to the external terminal TGi.
When the control line a directly connected to the circuit L3 and connected to the NOR circuit L4 via the inverting circuit L5 is at the high level, N
According to the signal level of the data line b directly connected to both the AND circuit L3 and the NOR circuit L4, both transistors L1, L2
When one of L2 is turned on, the data line b
The above signal is output via the external terminal TGi and the signal line a
Is low level, both transistors L1, L2
Are turned off, the external terminal TGi goes high.
It is configured to be held at the impedance.

Further, when the external terminal TGi is used as a general-purpose IO port, the individual circuit Ci includes a DR setting register 32 for setting whether the external terminal TGi is used as an input port or an output port. When an output and a control signal S3 to be described later are at a high level, an OR circuit L6 for setting the control line a of the output buffer circuit 30 to a high level and an output data when the external terminal TGi is used as an output port are set. An output setting register 34 for outputting the internal bus signal S1 to the data line b of the output buffer circuit 30 when the control signal S3 is at the low level, and an MUX 36 for outputting the internal bus signal S1 to the data line b when the control signal S3 is at the high level. When using TGi as an input port, a signal from the external terminal TGi was taken into the data bus 16. Tristate buffer 3
8, an MUX 40 for supplying the signal of the external terminal TGi to the tri-state buffer 38 when the output of the DR setting register 32 is at the low level, and the MUX 40 for supplying the output of the output setting register 34 to the tri-state buffer 38 when the output of the DR setting register 32 is at the high level. The signal from the external terminal TGi at the time of
Tristate buffer 4 for taking in to one signal line
2 is provided.

The DR setting register 32 and the output setting register 34 latch the value of a predetermined bit of the data bus when the port selection signal CSPi and the write signal WR are input, and are cleared when the reset signal RST is input. The tri-state buffer 38 is configured such that, when the port selection signal CSPi and the read signal WR are input when the control signal S2 to be described later is at the low level, data is fetched into predetermined bits of the data bus 16. It is configured as follows.

In the individual circuit Ci configured as described above,
In order to use the external terminal TGi as an output port, the signal on the data signal line b must be output to the external terminal TGi.
The output of the R setting register 32 may be set to the high level, and the control signal S3 may be set to the low level so that the output of the output setting register 34 is output to the data signal line b. In order to use the external terminal TGi as an input port, the output of the output buffer circuit 30 is held at high impedance, and the signal of the external terminal TGi is
The output of the DR setting register 32 may be set to a low level so that the output is supplied to the tri-state buffer 38 via 0. When the individual circuit Ci is used as a general-purpose input / output port, it is necessary to set the control signal S4 to a low level so that the signal of the external terminal TGi is not taken into the signal line of the internal bus signal S1. is there. Also,
When the external terminal TGi is used as an output port, data set in the output setting register 34 can be read through the MUX 40 and the tri-state buffer 38.

On the other hand, the external terminal TGi is connected to the internal bus signal S1.
Internal bus signal S1 is used for output of
X36, the signal is output to the data signal line b, and the signal of the data signal line b is output to the external terminal TGi.
What is necessary is just to set the control signal S3 to High level. To use the external terminal TGi for inputting the internal bus signal S1, the control signal S3 is set to a low level so that the output of the output buffer circuit 30 is maintained at a high impedance, and the tri-state buffer 42 is set to a low level. External terminal T
The control signal S4 may be set to the high level so that the signal from Gi is taken into the signal line of the internal bus signal S1.

Next, the individual circuit Ci in which the internal bus signal S1 input / output via the external terminal TGi is exclusively used for output instead of the general-purpose IO port is connected to the tri-state buffer 42 in the individual circuit Ci shown in FIG. Unless omitted,
The configuration is exactly the same as that of the individual circuit Ci of FIG. 3, and the operation is the same except that the external terminal TGi is not used for inputting the internal bus signal S1. .

Next, the individual circuit Ci in which the internal bus signal S1 input / output via the external terminal TGi is used exclusively for input instead of the general-purpose IO port, as shown in FIG.
3 except that the MUX 36 is deleted and the output of the output setting register 34 is directly connected to the data signal line b in the individual circuit Ci shown in FIG. , The external terminal TGi is not used for outputting the internal bus signal S1.
Other operations are exactly the same.

The internal bus signal S1 and the control signal S
3 to S4 are as shown in Table 1.

[0040]

[Table 1]

That is, general-purpose IO ports P00-P15, P48-
External terminals TG1 to TG16, TG used as P55
For the circuits 49 to TG56, the individual circuits Ci shown in FIG.
(Excluding the tri-state buffer 42), and the addresses A0 to A are used as the internal bus signal S1.
15 and various control signals CSIOout, CSROM, CS
RAM, RDout, WRout, CSXX, CSYY, C
SZZ is used, and as the control signals S2 and S3, the mode selection signal M which is at the high level in the bus extension mode is used.
b is used.

For external terminals TG17 to TG32 used as general-purpose IO ports P16 to P31, FIG.
, The input / output data D0 to D15 are used as the internal bus signal S1, and the bus expansion mode in the bus extension mode is used as the control signal S2. The mode selection signal Mb, the external output selection signal CSO, and the control signal S
4, the mode selection signal Mb and the external input selection signal C
SI is used.

Here, the external output selection signal CSO is a signal generated when an external device of the microcomputer 2 is accessed and data is output, and the external input selection signal CSI is the same as the external input selection signal CSI. This signal is generated when an external device is accessed and data is input. Note that the case of accessing a device external to the microcomputer 2 includes, specifically, the IO selection signal CSIOout and the chip select signals CSXX, CSYY, and CSZZ (when the external bus mode is set, CSROM, CSROM
RAM) becomes active.

Next, as for the external terminals TG33 to TG48 used as the general-purpose IO ports P32 to P47, the individual circuits Ci shown in FIG. And the data D0 as the internal bus signal S1.
To D15, and as the control signal S2, the mode selection signals Mi,
The mode selection signal Mi and the external input selection signal CSI are used as the control signal S3, and the mode selection signal Mi and the external input selection signal CSI are used as the control signal S4.

Further, for external terminals TG57 to TG64 used as general-purpose IO ports P56 to P63, FIG.
Are provided, selection signals CSIOin, RDin, WRin, addresses A0 to A4 are used as internal bus signals S1, and control signals S2, S4
As S3 and S4, the mode selection signal Mi which is set to the high level in the IO extension mode is used.

It should be noted that IO selection signal CS fetched via tristate buffer 42 in the IO extension mode.
The internal bus signal S1 other than IOin (see FIG. 2) is handled in the microcomputer 2 in exactly the same manner as the signal of the same name generated inside the microcomputer 2 in the normal mode or the bus expansion mode.

In the microcomputer 2 of the present embodiment configured as described above, as shown in FIG. 5, the operation mode is set to the normal mode by the mode setting external terminals TM0 and TM1 (both the mode selection signals Mb and Mi are both set). (Low level), all of the external terminals TG1 to TG64 are
Used for O ports P00 to P63. When the bus expansion mode (mode selection signal Mb is at the high level) is set, the external terminals TG1 to TG16 are connected to the address signals A0 to A0.
A15 for output, external terminals TG17 to TG32 for input / output of data signals D0 to D15, and TG49 to TG55 for various control signals CSIOout, RDout, WRout, CSR
OM, CSRAM, CSXX, CSYY, CSZZ output, remaining external terminals TG33 to TG48, TG57 to
The TG 64 is used for general-purpose IO ports P32 to P47 and P56 to P63. Further, the IO extension mode (when the mode selection signal Mi is Hi
gh level), the external terminals TG33 to
TG48 is for input / output of data signals D0-D15, and external terminals TG57-TG64 are various control signals CSIOin, RD.
in, WRin, and other external terminals TG1 to TG32, TG49 to TG56 for inputting lower addresses A0 to A4.
Are for general-purpose IO ports P00 to P31 and P48 to P55.

That is, in the bus extension mode and the IO extension mode, the external terminal TGi to which the internal bus signal S1 is input / output instead of the general-purpose IO port is configured to be different from each other. Next, an emulation device 50 used when emulating the microcomputer 2 in a system configured using the microcomputer 2 of the present embodiment will be described. The emulation device 50
Is used by connecting to the connector provided for the microcomputer 2 in the system instead of the microcomputer 2.

As shown in FIG. 6, the emulation device 50 is provided outside the microcomputers 2a and 2b, with a pair of microcomputers 2a and 2b having one set to the bus expansion mode and the other set to the IO expansion mode. External ROM 52
And a RAM 54 and a connector 56 connected to the connector for the microcomputer 2.

The external terminals TG17 to TG32 of the microcomputer 2a and the external terminals TG33 to TG48 of the microcomputer 2b are connected so that the data D0 to D15 are mutually input and output between the microcomputers 2a and 2b. The external terminals TG1 to TG5 and TG49, TG50, TG51 of the microcomputer 2a are connected so that the lower addresses A0 to A4 and the IO selection signal CSIO, the read signal RD, and the write signal WR output by the microcomputer 2a are input to the microcomputer 2b. External terminals TG60 to TG64 and TG of the microcomputer 2b
57, TG58 and TG59 are connected respectively.

The external terminals TG1 to TG16 of the microcomputer 2a are so arranged that data can be read from the ROM 52.
(Addresses A0 to A15), TG17 to TG32 (data D0 to D15), TG50 (read signal RD), TG
52 (ROM selection signal CSROM) is connected to the ROM 52, and external terminals TG1 to 16 (addresses A0 to A15) and TG17 to TG32 (data D) of the microcomputer 2a so that data can be read / written from / to the RAM 54.
0 to D15), TG50 (read signal RD), TG51
(Write signal WR), TG53 (RAM selection signal CSR)
AM) is connected to the RAM 54.

Further, external terminals TG33 to TG48, TG5 of the microcomputer 2a used as general-purpose IO ports
7 to TG64 and the external terminals TG1 to T of the microcomputer 2b.
G32, TG49 to TG56 are connected to the connector 56. Although not shown, the connector 56 has an external terminal TG1 for a general-purpose IO port in the microcomputer 2a.
To TG64 and mode selection external terminals TM0 and TM
External terminals other than 1 (for example, an external terminal TS for a dedicated port)
1 to TSn) are all connected.

Here, FIG. 7A shows the external terminals TG1 to TG64 of the microcomputer 2 set to the normal mode and the general-purpose I / O.
It is an explanatory view showing a correspondence relationship with O ports P00 to P63,
FIG. 7B illustrates the correspondence between the external terminals TG1 to TG64 of the microcomputers 2a and 2b set in the bus expansion mode or the IO expansion mode configuring the emulation device 50 and the general-purpose IO ports P00 to P63. FIG.

As shown in FIG. 7, in the emulation device 50, the microcomputer 2 set to the bus extension mode
In a, the general-purpose IO ports P00 to P31 and P48 to P55 are used to output internal bus signals necessary for emulation.
(External terminals TG1 to TG32, TG49 to TG56) are lost, but the microcomputer 2b set to the IO extension mode
However, these lost general-purpose IO ports P00-P31, P48-P
55, the emulation device 50 is, as far as the signals input and output via the connector 56 look,
It can be considered that the microcomputer 2 has the same function as the microcomputer 2 set in the normal mode.

As described above, according to the emulation device 50, the address required for emulation is maintained without losing any of the general-purpose IO ports P00 to P63, that is, while maintaining the same function as the microcomputer 2 set to the normal mode. A0 to A15, data D0 to D15, read signal R
Internal bus signals such as D and write signal WR can be obtained. Therefore, emulation of the microcomputer 2 can be easily performed by connecting an ICE or the like.

As described above, according to the microcomputer 2 of the present embodiment, the bus extension mode for enabling input / output of internal bus signals such as addresses and data from a part of the external terminal TGi for the general-purpose IO port, The internal bus signal can be input / output via an external terminal TGi different from the bus expansion mode, and the operation can be set to the IO expansion mode in which the operation of internal circuits other than the general-purpose IO ports lost in the bus expansion mode is prohibited. The same microcomputers 2a and 2b
By setting one to the bus extension mode and the other to the IO extension mode and connecting the internal bus signals input and output by the two microcomputers 2a and 2b to each other, it is possible to create an external circuit by discrete components or the like. The emulation device 50 having the same function as the microcomputer 2 set to the normal mode can be easily configured.

The microcomputer 2a set in the IO expansion mode replaces the general-purpose IO port lost by the microcomputer 2a set in the bus expansion mode with a general-purpose I / O port having the same configuration as this.
Because the O port compensates, no matter how sophisticated the general-purpose IO port becomes, the external circuit does not increase at the time of emulation, and the microcomputer 2 set in the normal mode is actually used. You can achieve exactly the same operation as when it is incorporated into the system,
Emulation with high reliability can be performed.

Further, in this embodiment, when executing control on the IO circuit 12, an IO selection signal CSIO for specifying the IO circuit 12 is output via the external terminal TGi in the bus extension mode. In the IO extension mode, input is performed via the external terminal TGi, so that the number of addresses to be input to the microcomputer 2b set in the IO extension mode is reduced (in this embodiment, only lower addresses A0 to A4 are used). Can be entered).

That is, since the IO selection signal CSIO is created by decoding the upper addresses A5 to A15, if the IO selection signal CSIO is input, the upper address A
There is no need to input 5-A15. In this embodiment, when the microcomputer 2 is set to the bus expansion mode and the external memory mode, the microcomputer 6
And the RAM 8 is separated from the address bus 14 and the data bus 16, so that the external terminal TGi
External RO by an internal bus signal output through
M52 and RAM 54 can be used. Therefore, at the stage of program development where the program is not determined, the external ROM 52 or RAM 54 composed of an external EPROM or Flash memory which can be easily rewritten can be used, and the time spent for program development and debugging by emulation can be used. And costs can be reduced.

The chip select signals CSXX, CSY output from the microcomputer 2a set in the bus extension mode
Y and CSZZ can be used when connecting a plurality of ROMs and RAMs. When a new function is added to the microcomputer 2, the function is realized by an external circuit for the time being, and the chip select signals CSXX and CSY are provided.
The microcomputer 2a set in the bus extension mode can control the external circuit by assigning Y and CSZZ, and the external circuit can be verified by the emulation device 50 to which the external circuit is added. The system development can be advanced, and the external circuit can be incorporated in the microcomputer 2 during that time, so that efficient system development can be performed.

In this embodiment, the external terminals TG1 to TG64 for general-purpose IO ports are used as a port group for inputting / outputting signals of the internal bus during emulation. However, the present invention is not limited to this. TS1-TS
n or the like may be used.

[Brief description of the drawings]

FIG. 1 shows a microcomputer (microcomputer) of an embodiment.
2 is a block diagram illustrating a schematic internal configuration of FIG.

FIG. 2 is a diagram illustrating a selection signal generator 12 included in an IO circuit 12.
It is a circuit diagram of a.

FIG. 3 is a circuit diagram of an individual circuit Ci included in the IO circuit 12.

FIG. 4 is a circuit diagram of an individual circuit Ci constituting the IO circuit 12;

FIG. 5 is a list showing assignment of external terminals TGi for each operation mode.

FIG. 6 is a circuit diagram illustrating a configuration of an emulation device 50 configured using the microcomputer 2 of the embodiment.

FIG. 7 is an explanatory diagram showing a relationship between the external terminal TGi and the general-purpose IO ports P00 to P63 in the microcomputer 2 operating in the normal mode and the microcomputers 2a and 2b constituting the emulation device 50.

[Explanation of symbols]

2, 2a, 2b: microcomputer 4: CPU
6 ROM 8 RAM 10 Peripheral circuit 12 IO circuit
12a: signal selection unit 12a: selection signal generation unit 14: address bus
16 Data bus 18 Decoder 20 Mode signal generation circuit 22, 36, 40 Multiplexer (MUX) 24
... Decoder 30 ... Output buffer circuit 32 ... DR setting register 34 ... Output setting register 38,42 ... Tristate buffer 50 ... Emulation device 52 ... External ROM 54 ... External RAM 56 ... Connector L1, L2 ... Field effect transistor L3 ... N
AND circuit L4 NOR circuit L5 Inverting circuit L6 O
R circuit TGi (i = 1 to 64): external terminal for general-purpose IO port TM1, TM2: external terminal for mode setting BF1 to BF5: buffer circuit

Claims (6)

[Claims] 1. A single-chip micro-computer comprising a CPU, a memory, and a port group for inputting and outputting signals via external terminals, the CPU and the memory being interconnected via an internal bus for transmitting addresses, data, and various control signals. In the computer, a CPU disconnecting unit that disconnects the CPU from the internal bus, a memory disconnecting unit that disconnects the memory from the internal bus, and an external terminal via a first port group that is a part of the port group First switching means for inhibiting input / output of signals and enabling input / output of signals of the internal bus from the external terminal; and a second switching means which is a part of a port group different from the first port group.
Second switching means for prohibiting input / output of signals through the external terminals by the port group and enabling input / output of signals of the internal bus from the external terminals; CPU disconnection means and memory disconnection means A normal mode in which all of the first switching means and the second switching means are disabled, a bus extension mode in which only the first switching means is enabled, and a CPU separation means, a memory separation means, and a second mode. Mode setting means for setting any one of the IO extension modes to enable only the switching means. When the mode setting means sets the IO extension mode, the second switching means sets the external mode. A microcomputer configured to operate the first port group in accordance with a signal of the internal bus input / output via a terminal. 2. The microcomputer according to claim 1, wherein the first switching means and the second switching means enable the input / output via the external terminal via one of the internal bus signals. The first switching means outputs an IO selection signal used for selecting the port group when executing the control on the port group, and the second switching means outputs the IO selection signal.
A microcomputer which inputs an O selection signal. 3. The microcomputer according to claim 1, wherein said mode setting means can be set to an external memory mode for enabling said memory disconnecting means when said bus expansion mode is set. A microcomputer characterized in that: 4. The microcomputer according to claim 3, wherein said first switching means executes control of said memory as one of signals of said internal bus which can be input / output via said external terminal. A microcomputer which outputs a memory selection signal used for selecting the memory at times. 5. The microcomputer according to claim 1, wherein one of the microcomputers is set to the bus extension mode, and the other microcomputer is set to the IO extension mode. In addition, the signals of the internal bus, which can be input / output via the external terminals by the first switching means and the second switching means, are mutually input / output between the pair of microcomputers. An emulation device characterized by connecting terminals. 6. The microcomputer according to claim 3, wherein one of the microcomputers is set to the bus extension mode, and the other microcomputer is set to the IO extension mode and the external microcomputer. A memory mode is set, and signals between the external terminals are input and output via the external terminals by the first switching means and the second switching means. And an external memory controlled by a signal of the internal bus.