JPH10321820A - Memory cell array manufacturing method - Google Patents

Abstract

(57) Abstract: A method of manufacturing a memory cell having a buried bit line positioned in self-alignment is provided. A trench is formed on a semiconductor substrate, a transistor element is formed, a first insulating film is deposited, and the trench is filled to form an insulating plug.
After forming the insulating film 31, an opening is provided to expose one corner of the semiconductor substrate 12 and the insulating plug 21, the corner is etched to form a concave groove 34, and a doped polysilicon film 41 is deposited. Deposit the conductive film 42
34, a conductive plug 51 is formed by a recess etching process, a third insulating film 61 is deposited on the conductive plug 51 and the periphery thereof to form a buried bit line 17, and a source / drain region and doping are formed by an annealing process. A memory cell manufacturing method for forming interconnections by diffusing impurities in a formed polysilicon film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a memory cell array, and more particularly, to a method for manufacturing a memory cell array having a buried bit line. The transfer transistor in this buried bit line memory cell array
The present invention can be applied to a high-density (High-Density) memory cell array, while being able to perform self-aligned positioning on a stortor and without occupying extra space.

[0002]

2. Description of the Related Art Performance of semiconductor devices
And to reduce process costs.
One of the development directions of the semiconductor manufacturing process. These goals are being achieved in sub-micron or micro-miniaturized manufacturing processes. If smaller scale (Feature
In the case of developing to the manufacturing process of s), it is difficult to guarantee the quality of the capacitor in the device, the electric resistance becomes unstable, and the performance of the device decreases. However, if the scale can be reduced, the chip (chip) size is also reduced, so that the degree of integration is improved and the manufacturing cost of each chip is reduced.

[0003]

SUMMARY OF THE INVENTION Scale reduction is achieved by using a dynamic random access memory (Dynamic Random Access Memory).
Access Memory (DRAM) is very important in the device manufacturing process. In a single DRAM memory cell, usually all are stacked capacitors (Stacke
d Capacitor) structure, and the position of this stacked capacitor is the source (Sourc
e) or above the drain region. The bit line of the DRAM memory cell is wired along the insulating film by using a metal line, and a contact hole is provided in the insulating film to be interconnected with a source or a drain. The prior art method of reducing the bit line area of a DRAM memory cell utilizes the concept of buried bit lines, for example, in U.S. Pat. Nos. 5,250,457 and 5,36.
No. 4,808, discloses a method of forming a buried bit line in a transfer transistor. However, since the buried bit lines in these inventions have an increased bit line coupling on the silicon substrate, if the buried bit lines rely on the source / drain regions to realize insulation from the silicon substrate, If so, defects cannot be allowed to exist, and it is very difficult to control the yield in manufacturing.

Accordingly, in order to solve the above-mentioned problems, the present invention has as its main object to provide a method of manufacturing a memory cell array, and more particularly, to a method of manufacturing a memory cell array having buried bit lines. To provide.

[0005]

Means for Solving the Problems In order to solve the above problems and achieve the above object, a method of manufacturing a memory cell array according to the present invention comprises the following means. A plurality of trenches are formed on a semiconductor substrate, a first insulating film is deposited, and the plurality of trenches are filled to form a plurality of insulating plugs. Depositing a second insulating film on the semiconductor substrate and the insulating plug to form a first opening, partially exposing the semiconductor substrate, and exposing a corner of one of the plurality of insulating plugs; . A groove is formed by etching a corner of the insulating plug, and a doped first polysilicon film is deposited on the groove. A conductive film is formed and filled in the groove, and a recess etching process is performed to form a conductive plug. A third insulating film is deposited on the conductive plug and the periphery thereof to form a buried bit line. A transfer transistor having a gate and source / drain regions is formed on a semiconductor substrate. Perform the annealing process and
Impurities in the drain region and the doped first polysilicon film are diffused and interconnected. Depositing a fourth insulating film layer on each film layer and forming a second opening,
Exposing the source / drain regions. Forming a second polysilicon film around the periphery of the second opening to fill the second opening, forming a lower electrode to form a dielectric film, depositing a third polysilicon film to form an upper electrode, A stacked capacitor structure is formed by the electrode and the upper electrode.

[0006]

The present invention discloses a method of manufacturing a memory cell array by the above means, and has a structure in which a buried bit line is covered with a stacked capacitor structure. By embedding a buried bit line in a field oxide film, in a shallow insulated trench, or in another insulating oxide film, the problem that the area occupied by a conventional bit line can be solved. Further, such a buried bit line structure has a function of positioning the source / drain region in the adjacent transfer transistor in a self-alignment manner, and it is capable of out-diffusion of impurities in the bit line and the source / drain region. -diff
This can be realized by automatically connecting the source / drain region in the transfer transistor to the buried bit line by performing the connection. Therefore, by embedding the bit line in an insulating oxide film, a shallow trench (Shallow Trench) or a field oxide film (Field Oxide Region), the bit line does not occupy an extra space and the integration density of the device is improved. In addition, the bit line coupling can be reduced, and the element can be automatically separated from the silicon substrate by the field oxide film.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings. In FIG. 1, there are a plurality of shallow trenches 12, which are filled with an insulating material. Around the plurality of shallow trenches 12, regions where the semiconductor substrate 10 is exposed are distributed. A buried bit line 17 is shown in dashed lines in FIG. 1 and spans a plurality of shallow trenches 12. The polysilicon gate 13 intersects the buried bit line 17 at a right angle, and partially crosses the semiconductor substrate 10. Further, a second opening 14 is provided as a through hole, and a stacked capacitor 15 is formed therein.

FIG. 2 shows a preferred embodiment (manufacturing process) of the method for manufacturing a memory cell array according to the present invention. First, a semiconductor substrate 10 is prepared, and
00> cut along the crystal plane of single crystal silicon and form a thin oxide film (not shown). Then, a plurality of trenches 12 are formed on the semiconductor substrate 10 by anisotropic reactive ion etching (Reactive Ion Etch = RIE) using chlorine (Cl ₂ ) as an etching agent (Etchant). The depth of the plurality of trenches 12 is about 4
The design rules (Desi
gn Rules), the width and the interval of each trench 12 are determined. Next, low pressure chemical vapor deposition
ical Vapor Deposition = LPCVD) or Plasma Enhanced Chemical Vapor Deposit
A first insulating film 21a, for example, an oxide of silicon (both not shown) is deposited on the semiconductor substrate 10 at a temperature in the range of about 300 to 700 ° C. by ion = PECVD, and a plurality of trenches 12 are formed. At the same time, the first insulating film 21a is filled.
(Not shown) has a thickness of 2 /／ of the width of the plurality of trenches 12.
3 is assumed. And chemical mechanical polishing (Chemical Mechanica)
l Polishing = CMP) method or anisotropic reactive ion etching method using methane trifluoride (CHF ₃ ) as an etching agent and an extra first insulating film 2 other than the plurality of trenches 12
1a (not shown), and a plurality of insulating plugs 21 are removed.
To form

In FIG. 3, reduced pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, or thermal oxidation (Thermal Oxid
ation) method to form a second insulating film 31 having a thickness in the range of about 500 to 1000 °. On this second insulating film 31, a patterned photoresist film 32 is applied and formed. A first opening 33 is formed in the second insulating film 31 using methane trifluoride as an etching agent by anisotropic reactive ion etching using the photoresist film 32 as a mask,
Part of semiconductor substrate 10 and a plurality of insulating plugs 21
After exposing a corner of one of the insulating plugs 21, the insulating plug 21 is subsequently etched to form a groove 34 in the trench 12. The depth of the groove 34 is set to about 2500-3500 °. Range. And
The photoresist film 32 is removed.

Referring to FIG. 4, a thin first polysilicon film 41 is deposited on each of the above-mentioned film layers, and
An impurity such as arsenic (Arsine) or hydrogen phosphide (Phosphine) is added to the polysilicon film 41. In this method, the temperature is set in a range of about 550 to 650 ° C., and silane (Silane) is used as a reaction gas, and arsenic ions and phosphorus ions are simultaneously added, and formed by a low pressure chemical vapor deposition method. The thickness of the doped first polysilicon film 41 is in the range of about 250-350 °. Next, the temperature is set in the range of about 600 to 800 ° C., and the first polysilicon film 41 is formed by a low pressure chemical vapor deposition method using tungsten hexafluoride (Tungsten Hexafluoride) as a reaction gas.
A conductive film 42 is deposited thereon, and its thickness is about 1500 to 25
The range is 00 °. If the conductive film 42 is made of tungsten, a thin titanium nitride (Titanium Nitride) film is first deposited to form a first polysilicon as a barrier film (Barrier Layer not shown) before the conductive film 42 is formed. The film 41 is prevented from being destroyed. Conductive film 42
The material is Tungsten Silicid
e) may be formed by a low pressure chemical vapor deposition method using tungsten hexafluoride and silane as reaction gases.

Referring to FIG. 5, an etch back step is performed on each of the above-described film layers. The first polysilicon film 41 and the conductive film 42 are formed by anisotropic reactive ion etching using chlorine as an etching agent. Etching is performed, and a conductive plug 51 is formed by digging down from the surface of the semiconductor substrate 10 to a range of about 1000 to 2000 ° by a recess etching step so as to leave the conductive film 42 in the concave groove 34. The thickness of the conductive plug 51 is in the range of about 1500 to 2500 °
Is on the corner of the insulating plug 21.

In FIG. 6, after the second insulating film 31 is removed, a third insulating film is formed on the semiconductor substrate 10 at a temperature of about 300 to 700 ° C. by a reduced pressure chemical vapor deposition method or a plasma chemical vapor deposition method. A film 61 is deposited and its thickness is
The range is 0 to 3000 °. Then, the third insulating film 61
Is performed, but the conductive plug 51 is formed as the buried bit line 17 (FIG. 1) while methane trifluoride is used as an etching agent and the third insulating film 61 above and around the conductive plug 51 is left. I do.

First, in FIG. 7 (b), this figure is a sectional view taken along the line BB 'in FIG. 1, and a thermal oxidation method is applied on the semiconductor substrate 10 at a temperature in the range of about 850-950.degree. Thinner gate insulation layer (Gate Insulator Layer) 7
1, for example, growing silicon dioxide. The thickness of the gate insulating film 71 is in the range of about 50 to 200 degrees. Then, a gate 13, for example, a polysilicon film is formed on the gate insulating film 71 by a reduced pressure chemical vapor deposition method at a temperature in a range of about 550 to 650 ° C. The thickness of the gate 13 is about 20
The range is from 00 to 4000 °. Next, N-type ions, for example, arsenic ions or phosphorus ions are implanted into the gate 13 by ion implantation (Ion Implantation).
The energy is in the range of about 25 to 100 KeV, and the dose is in the range of about 1E14 to 1E16 atoms / cm ² . In addition, N-type ions, for example, arsenic ions or phosphorus ions are mixed, and a Situ Doping Procedure is performed in an atmosphere filled with silane.
Can also be implemented. The gate 13 is usually used as a word line (Word Line), and is arranged at right angles to the buried bit line 17 (see FIG. 1). Then, N-type ions, for example, arsenic ions or phosphorus ions are further implanted into the semiconductor substrate 10 on the side of the gate 13 by ion implantation to form a lightly doped source / drain region 73. 3
0 to 75 KeV, and the dose is about 1E12 to 1E12.
The range is E14 atoms / cm ² . Next, an oxide film 74a (not shown) having a thickness of about 2000 to 3000 ° on the gate 13 by a reduced pressure chemical vapor deposition method or a plasma chemical vapor deposition method at a temperature of about 300 to 700 ° C. Is deposited. Then, a wall spacer 74 is formed on the side of the gate 13 using methane trifluoride as an etching agent by anisotropic reactive ion etching. Further, N-type ions, for example, arsenic ions or phosphorus ions are implanted into the semiconductor substrate 10 on the side of the gate 13 by an ion implantation method to form heavily doped source / drain regions 75. ~
The range is 100 KeV, and the dose is about 1E14 to 1E.
The range is 16 atoms / cm ² .

FIG. 7A is a cross-sectional view taken along the line AA 'in FIG. 1, and the semiconductor substrate 10 has a lightly doped source / source.
Drain region 73 and heavily doped source /
Although the drain region 75 and the gate insulating film 71 are formed, these respective film layers are not covered with the third insulating film 61. Then, annealing for a short time (Rapid Th
ermal Anneal) step, but at a temperature of about 950.
And an operating time of about 10-60 seconds. Thereby, the impurities in the heavily doped source / drain regions 75 and the lightly doped source / drain regions 73 and the doped first polysilicon film 41 begin to be energized and diffuse to form an interconnect. Can be. Therefore,
Since the doped first polysilicon film 41, the lightly doped source / drain region 73 and the heavily doped source / drain region 75 are positioned in a self-alignment manner, the buried bit line 51 and the lightly doped source / drain region 75 are positioned. Both the drain region 73 and the heavily doped source / drain region 75 will be positioned in self alignment. Thus, since the positioning step by the subsequent photolithography step can be omitted, it is not necessary to worry that the positioning control by the exposure of the photolithography is difficult.

Referring to FIG. 8, a fourth insulating film 81 is deposited on each of the above-mentioned film layers, and a second opening 14 is formed to form a lightly doped source / drain region 73 and a heavily doped source / drain region. The surface of the region 75 is exposed. The formation of the second opening 14 is performed by a process in which methane trifluoride is used as an etching agent by anisotropic reactive ion etching and the temperature is in the range of about 300 to 500 ° C. Then, a second polysilicon film 83a (not shown) is formed on the periphery of the second opening 14 by a reduced pressure chemical vapor deposition method at a temperature in the range of about 550 to 650 ° C.
000-8000 °. The second polysilicon film 83a (not shown) fills the second opening 14 and implants N-type ions, for example, arsenic ions or phosphorus ions by ion implantation, to reduce the energy amount to about 25 to
75 KeV range, dose about 1E16-5E16a
toms / cm ² . Alternatively, in-situ doping can be performed in an atmosphere filled with silane gas and mixed N-type ions, for example, arsenic ions or phosphorus ions. Then, the second polysilicon film 83a (not shown) is patterned by photolithography and anisotropic reactive ion etching using chlorine as an etching agent to form a lower electrode 83 for a capacitor.

In FIG. 9, a dielectric film 9 is formed on the lower electrode 83.
1, the dielectric film 91 can be formed by a sputtering method, and a material having a high dielectric constant (High Dielectric Constant), for example, an oxide of tantalum, preferably, tantalum pentoxide (Ta2O
By using 5), the thickness is about 200 to 30
The range is 0 °. Further, as the dielectric film 91, a silicon oxide / silicon nitride / silicon oxide (Oxidized / Silicon Nitride / Sil) having a thickness of about 40 to 80 ° by a deposition method.
icon Oxide = ONO) film can also be adopted. The method is to form a silicon oxide film having a thickness of about 10 to 50 ° and a silicon nitride film having a thickness of about 10 to 20 °. Therefore, a silicon oxide film is formed on a silicon nitride film by a thermal oxidation method (both are not shown). Next, a third polysilicon film 92a is formed on the dielectric film 91.
(Not shown), but the method involves raising the temperature to about 55
The temperature is in the range of 0 to 650 ° C., and it is formed by low pressure chemical vapor deposition. The thickness of third polysilicon film 92a (not shown) is in the range of about 2000-3000 °. Then, ions are doped into the third polysilicon film 92a (not shown). In this method, in-situ doping is performed in an atmosphere of a silane gas and a mixed hydrogen phosphide gas. Further, the third polysilicon film 92a (not shown) is patterned by photolithography and anisotropic reactive ion etching using chlorine as an etching agent to form an upper electrode 92 for a capacitor. The lower electrode 83, the dielectric film 91, and the upper electrode 92 form a stacked capacitor 15 structure.

As described above, the present invention has been disclosed by the preferred embodiments. However, as will be easily understood by those skilled in the art, appropriate changes and modifications can be made within the technical idea of the present invention. Therefore, the scope of patent protection shall be determined based on the claims and the equivalent area.

[0018]

With the above structure, the method of manufacturing a memory cell array according to the present invention improves the device integration density by burying a buried bit line in a trench without occupying an extra space for the bit line. Can be done. In addition, since such a buried bit line structure can be positioned in the source / drain region in the transfer transistor in a self-alignment manner, a troublesome photolithography step can be omitted, and the cost can be reduced. Therefore, the method for manufacturing a memory cell array according to the present invention has high industrial utility value.

[Brief description of the drawings]

FIG. 1 is a plan view showing a memory cell array according to a preferred embodiment of the present invention.

FIG. 2 is an explanatory sectional view showing a memory cell array manufacturing process according to a preferred embodiment of the present invention;

FIG. 3 is an explanatory cross-sectional view showing a memory cell array manufacturing process.

FIG. 4 is an explanatory cross-sectional view showing a memory cell array manufacturing process.

FIG. 5 is also an explanatory sectional view showing a memory cell array manufacturing process.

FIG. 6 is also an explanatory sectional view showing a memory cell array manufacturing process.

FIG. 7 shows a memory cell array manufacturing process
Explanatory sectional view (a) shown along line A ', and BB'
It is explanatory sectional drawing (b) shown along the line.

FIG. 8 is an explanatory sectional view showing a manufacturing process of a stacked capacitor in the manufacturing process of the memory cell array according to the preferred embodiment of the present invention;

FIG. 9 is an explanatory cross-sectional view showing a manufacturing process of the stacked capacitor.

[Explanation of symbols]

 Reference Signs List 10 semiconductor substrate 12 trench 13 gate 14 second opening 15 stacked capacitor 17 buried bit line 21 insulating plug 31 second insulating film 32 photoresist film 33 first opening 34 concave groove 41 first polysilicon film 42 conductive film 51 conductive plug 61 Third insulating film 71 Gate insulating film 73 Lightly doped source / drain region 75 Highly doped source / drain region 81 Fourth insulating film 83 Lower electrode 91 Dielectric film 92 Upper electrode

Claims (40)

[Claims] (A) forming a plurality of trenches on a semiconductor substrate; (b) forming a first insulating film on the semiconductor substrate to fill the plurality of trenches; c) removing the first insulating film on the semiconductor substrate and forming a plurality of insulating plugs while leaving the plurality of filled trenches; and (d) on the semiconductor substrate and the insulating plug. (E) forming a first opening in the second insulating film to partially expose the semiconductor substrate and to insulate one of the plurality of insulating plugs; Exposing a corner of the plug; (f) removing the first insulating film below the corner of the insulating plug to form a concave groove; and (g) forming the second insulating film and partially Exposed to the semiconductor Forming a substrate and the first polysilicon film doped on said groove,
(H) forming a conductive film on the doped first polysilicon film and filling the conductive film into the concave groove; (i) the conductive film and the doped first polysilicon film and Removing a portion of the semiconductor substrate to form a conductive plug, leaving the doped first polysilicon film in the groove;
(J) forming a bit line by performing a recess etching process on the conductive plug; and (k) forming a third insulating film on the conductive plug and a peripheral edge thereof and burying the bit line; (L) forming a gate insulating film on the semiconductor substrate and forming a gate on the gate insulating film; and (m) lightly doped source / drain regions on the semiconductor substrate beside the gate. Forming and distributing the lightly doped source / drain regions in a region between the third insulating film and the plurality of trenches;
(N) forming a wall spacer on the side of the gate; and (o) forming a heavily doped source / drain region on the semiconductor substrate on the side of the wall spacer, wherein the lightly doped region is formed. Forming a transfer transistor with the source / drain regions and the heavily doped source / drain regions and the gate; and performing (p) an annealing step to perform the heavily doped source / drain regions and the thin film. Diffusing the impurities in the doped source / drain regions and the first polysilicon film to make mutual contact with each other; (q)
Depositing a fourth insulating film layer on each of said film layers; and (r) forming a second opening in said fourth insulating film layer to form said lightly doped source / drain regions and said darkened source / drain regions. Exposing a surface of the doped source / drain region; and (s) forming a second polysilicon film around a periphery of the second opening and filling the second opening to form a lower electrode. (T) forming a dielectric film on the lower electrode; and (u) depositing a third polysilicon film on the dielectric film to form an upper electrode, and forming the upper electrode by the lower electrode and the upper electrode. Forming a stacked capacitor structure. 2. The method for forming a plurality of trenches in the step (a) is an anisotropic reactive ion etching method.
2. The method for manufacturing a memory cell array according to claim 1, wherein the etching agent is chlorine. 3. The method according to claim 1, wherein the plurality of trenches have a depth in the range of about 4000 to 6000 °. 4. The method of forming the first insulating film in the step (b), wherein the temperature is in a range of about 300 to 700 ° C., and the first insulating film is formed by a chemical vapor deposition method.
The manufacturing method of the memory cell array according to the above. 5. The method according to claim 1, wherein the first insulating film is a silicon oxide. 6. The method according to claim 1, wherein the thickness of the first insulating film is about 2/3 of the width of the plurality of trenches. 7. The memory cell array manufacturing method according to claim 1, wherein the method of forming the concave groove in the step (f) is an anisotropic reactive ion etching method, wherein methane trifluoride is used as an etching agent. Method. 8. The groove has a depth of about 2500-3.
2. The method according to claim 1, wherein the angle is in the range of 500 [deg.]. 9. The method of forming a doped first polysilicon film in the step (g), comprising:
2. The method according to claim 1, wherein the temperature is in the range of 0 to 650 [deg.] C., and silane is used as a reaction gas, and at the same time, arsenic ions and phosphorus ions are doped to form the memory cell array by low pressure chemical vapor deposition. 10. The method according to claim 1, wherein said doped first polysilicon film has a thickness in the range of about 250-350 °. 11. The method for forming a conductive film in the step (h), wherein the temperature is in a range of about 600 to 800 ° C.,
2. The method for manufacturing a memory cell array according to claim 1, wherein the film is formed by low pressure chemical vapor deposition using tungsten hexafluoride as a reaction gas. 12. The method according to claim 11, wherein the conductive film is made of tungsten. 13. The conductive film has a thickness of about 2500.
The method according to claim 11, wherein the angle is in the range of ~ 3500 °. 14. The method of forming a conductive film in the step (h), wherein the temperature is in a range of about 600 to 800 ° C.
Using tungsten hexafluoride and silane as reaction gases
2. The method according to claim 1, wherein the film is formed by a low pressure chemical vapor deposition method.
The manufacturing method of the memory cell array according to the above. 15. The method according to claim 14, wherein the conductive film is made of silicide of tungsten. 16. The conductive film has a thickness of about 1500
The method according to claim 14, wherein the angle is in the range of ２2500 °. 17. The recess etching step of the step (j), wherein the thickness of the conductive film is about 1500 to 25 by using an etching agent as chlorine by anisotropic reactive ion etching.
2. The method according to claim 1, wherein the bit line is formed in a range of about 00 [deg.] And the formed bit line is located about 2000 [deg.] Below the surface of the trench. 18. The method for forming the third insulating film in the step (k), wherein the temperature is in a range of about 300 to 700 ° C., and the third insulating film is formed by a chemical vapor deposition method.
The manufacturing method of the memory cell array according to the above. 19. The method according to claim 1, wherein the third insulating film is a silicon oxide. 20. The semiconductor device according to claim 10, wherein the third insulating film has a thickness of about 15
2. The method for manufacturing a memory cell array according to claim 1, wherein the angle is in the range of 00 to 2500 [deg.]. 21. The gate insulating film is made of silicon oxide, has a thickness in the range of about 50 to 200 °, is formed at a temperature in the range of about 850 to 950 ° C., and is formed by a thermal oxidation method. 2. The method for manufacturing a memory cell array according to claim 1, wherein said memory cell array is formed. 22. The lightly doped source / drain region of step (m) is for implanting N-type ions, and has an energy amount of about 30 to 75K.
The range of eV and the dose amount are about 1E12 to 1E14 atom.
^2. The method for manufacturing a memory cell array according to claim 1, wherein the range is s / cm ² . 23. The heavily doped source / drain region of step (o) is for implanting N-type ions and has an energy amount of about 50-100.
KeV range, dose about 1E14 to 1E16ato
^2. The method for manufacturing a memory cell array according to claim 1, wherein the range is in the range of ms / cm ² . 24. The method according to claim 1, wherein the annealing temperature in the step (p) is in a range of about 950 to 1050 ° C., and an execution time is in a range of about 10 to 60 seconds. 25. The dielectric film of the step (t),
The thickness is in the range of about 40 to 80 °, and the forming method is such that first, a silicon oxide film having a thickness of about 10 to 50 ° is formed, and then a silicon nitride film having a thickness of about 10 to 20 ° is formed. 2. The method according to claim 1, further comprising forming a silicon oxide film on the silicon nitride film by a thermal oxidation step after forming the silicon oxide film. 26. The dielectric film of the step (t),
An oxide of tantalum, the thickness of which is about 200 to 300
2. The method for manufacturing a memory cell array according to claim 1, wherein the range of Å is set by a sputtering method. 27. (a) forming a plurality of trenches on a semiconductor substrate and filling the plurality of trenches with a first insulating film; and (b) one of the plurality of trenches. Forming a groove at a corner of the surface; (c) depositing a doped polysilicon film in the groove; (d) depositing a conductive film on the doped polysilicon film; Filling the groove with a film; and (e) etching back the conductive film to form a conductive plug in the groove, and then performing a recess etching process on the conductive plug. Forming a bit line by etching a semiconductor substrate; and (f) forming a second insulating film on the bit line and its periphery to bury the bit line;
(G) forming source / drain regions on the semiconductor substrate and distributing the source / drain regions in a region between the plurality of trenches; and (h) performing an annealing process to perform doping. Diffusing the impurities in the polysilicon film to make mutual contact with the source / drain regions to make the buried bit lines self-aligned with the source / drain regions. 28. The method of forming a plurality of trenches in the step (a) is an anisotropic reactive ion etching method, wherein the plurality of trenches have a depth of about 400.
28. The method for manufacturing a memory cell array according to claim 27, wherein the angle is in a range of 0 to 6000 degrees. 29. The method for forming the first insulating film in the step (a), wherein the temperature is in a range of about 300 to 700 ° C., and the first insulating film is formed by a chemical vapor deposition method.
8. The method for manufacturing a memory cell array according to 7. 30. The method according to claim 27, wherein the first insulating film has a thickness of about 2/3 of a width of the plurality of trenches. 31. The method of forming the concave groove in the step (b) is an anisotropic reactive ion etching method, wherein methane trifluoride is used as an etching agent.
8. The method for manufacturing a memory cell array according to 7. 32. The groove has a depth of about 2500 to
28. The method for manufacturing a memory cell array according to claim 27, wherein the range is 3500 degrees. 33. The method of forming a doped first polysilicon film in the step (c), comprising:
The temperature is in the range of 50 to 650 ° C., silane is used as a reaction gas, and arsenic ions and phosphorus ions are doped at the same time. 250-350Å
28. The method for manufacturing a memory cell array according to claim 27, wherein: 34. The conductive film of the step (d),
Tungsten is used as a material, the formation method is a method in which the temperature is in the range of about 600 to 800 ° C., and tungsten hexafluoride is used as a reaction gas by a low pressure chemical vapor deposition method, Approximately 25 film thickness
28. The method for manufacturing a memory cell array according to claim 27, wherein the angle is in the range of 00 to 3500 °. 35. The conductive film of the step (d),
Tungsten is used as a material, and the forming method is a method in which the temperature is in a range of about 600 to 800 ° C., and tungsten hexafluoride and silane are used as reaction gases by a low pressure chemical vapor deposition method, and 28. The method of claim 27, wherein the conductive film has a thickness in the range of about 2500-3500 degrees. 36. The method according to claim 27, wherein the bit line in the step (e) has a thickness in a range of about 1500 to 2500 degrees. 37. The recess etching step of the step (e), wherein the bit line is positioned below the trench surface by about 1000 to 2000 ° by using an etching agent as chlorine by an anisotropic reactive ion etching method. The method for manufacturing a memory cell array according to claim 27, wherein 38. The second insulating film in the step (f),
A silicon oxide, the method of forming the second insulating film having a temperature in the range of about 300 to 700 ° C., and the second insulating film having a thickness of about 20 to 20 ° C.
28. The method for manufacturing a memory cell array according to claim 27, wherein the temperature is in the range of 00 to 3000 degrees. 39. The source / drain region in the step (g) is formed by an ion implantation method, and an ion to be implanted has an implantation energy amount of about 50 to 100 KeV.
And the dose amount is about 1E14 to 1E16 atom.
28. The method for manufacturing a memory cell array according to claim 27, wherein the N-type ions are in the range of s / cm < ² >. 40. The memory cell array according to claim 27, wherein the annealing step in the step (h) has a temperature in a range of about 950 to 1050 ° C. and an execution time in a range of about 10 to 60 seconds. Production method.