JPH10322216A - decoder - Google Patents

Abstract

(57) [Summary] [Problem] To provide input data having a header including information indicating a data format of a data portion, even if the data formats of the data portion are different from each other, Even if the data format is based on an advanced encoding technique, a decoder capable of reliably decoding the data portion with a simple configuration is obtained. A rewritable hardware decoder for decoding a data portion of input data provided with a header including information indicating a data format of a data portion, and a decoding algorithm of the decoder based on information indicating a format of the data portion. And control means 5 for rewriting the decoding algorithm according to the data format of the data part of the input data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a decoder suitable for application to a DAB (Digital Audio Broadcasting) receiver.

[0002]

2. Description of the Related Art The configuration of a DAB receiver will be described below with reference to FIG. A reception signal from the reception antenna 21 is supplied to an RF (high-frequency) amplifier / frequency converter / IF (intermediate frequency) amplifier 22, and is respectively subjected to high-frequency amplification, frequency conversion, and then intermediate-frequency amplification.
Baseband OFDM (Orthogonal Freqency Divisi)
(onMutiplex: orthogonal frequency division multiplexing) A modulated signal is obtained, and this OFDM modulated signal is supplied to an A / D converter 23 and converted into digital data. The digital data is supplied to a digital I / Q demodulator 24. And demodulated,
Real part data and imaginary part data are obtained.

[0003] Time series real part data and imaginary part data from the digital I / Q demodulator 24 are supplied to a fast Fourier transform circuit (FFT circuit) 25 and converted into frequency series real part data and imaginary part data. Is done. FFT circuit 2
5 are supplied to the Viterbi decoder 2 and Viterbi-decoded, and then supplied to the source decoder 27 and the decoder 28.

The real part data and the imaginary part data from the digital I / Q demodulator 24 are supplied to a synchronization generation circuit 26, from which a time synchronization signal is obtained. This time synchronizing signal is supplied to the fast Fourier transform circuit 25 to control the timing of the fast Fourier transform, and is also supplied to the Viterbi decoder 2 to control the synchronization.

[0005] A digital audio signal (a digital video signal is also possible) is obtained from the source decoder 27, and the digital audio signal is supplied to a D / A converter (not shown), converted into an analog audio signal, and converted into an analog audio signal. The signal is provided to the speaker through a low frequency amplifier.

From the decoder 28, data on music such as music title, artist name, lyrics, etc.
Data such as news, traffic information, and still images are output.

Next, the DAB signal will be described. DA
As the B signal, signals of modes 1, 2, 3, and 4 are known at present. In the DAB signal, T is used as a basic cycle.
(= 1 / 2.048MHz = 0.00048828mse
c) is stipulated. Here, the DAB signal of mode 1 is shown in FIG. 9 as a representative. In FIG. 9, the basic period T
And the time. One frame of the DAB signal in mode 1 is 196608 T (= 96 msec), one null symbol (symbol number l = 0) having a duration of 2656 T (= 1.297 msec), and both subsequent durations are 2552 T ( = 1.246 msec) (symbol number l = 1 to 76).

The symbols of symbol numbers l = 1 to 76 are
The duration of the first part is 504T (= 24
6 .mu.sec) and an effective symbol having a duration of 2048 T (= 1 msec). The effective symbol of each symbol having the symbol number 1 = 1 to 76 includes k = 1536 multicarriers having different frequencies. The carrier indicated by 0 is the carrier of the center frequency (the period of the carrier is T), the carrier indicated by 1536/2 (= 766) is the carrier of the highest frequency, and -1536/2 (= -7).
The carrier indicated by 66) is the carrier of the lowest frequency. The data amount of one symbol is 1536 waves, and the data amount is 1536 × 2 bits, 48 CU (capacity unit) × 64 bits.

The entirety of the symbols with symbol numbers 1 = 1 to 76 is called an OFDM (orthogonal frequency division multiplex) symbol.

For example, taking the case of mode 1 as an example, a null symbol with symbol number l = 0 and a symbol with I = 1 are called TFPR symbols (time frequency phase reference symbols), respectively, and these two symbols are , Is called a synchronization channel (synchronization channel). The symbol numbers l = 2 to 4 are called FIC {fast (high-speed) information channel}, and FIC
The whole is divided into 12 FIBs (fast information blocks). Remaining symbol number l = 5-7
6 is 4 CIFs (Common Interleaved Frame)
Is divided into what is called.

The duration of each symbol of the DAB signal differs depending on the mode. The duration of each symbol in mode 2 is 1/4 of the duration of each symbol in mode 1,
The duration of each symbol in mode 3 is 1/8 of the duration of each symbol in mode 1, and the duration of each symbol in mode 4 is 1/2 of the duration of each symbol in mode 1.

That is, in the mode 1, the duration of the symbol excluding the null symbol is 2552T (=
1.246 msec), but in mode 2, 638T
(= 2552T / 4) ｛= 312 μsec (= 1.246)
msec / 4)｝, 319T (= 2552T) in mode 3
/ 8) ｛= 156 μsec (= 1.246 msec /
8)｝, 1276T (= 2552T / 2) in mode 4
{= 623 μsec (= 1.246 msec / 2)}.

The duration τ / n of an effective symbol in a symbol excluding a null symbol is 2048 T (= 1 msec) in mode 1 as described above, and 512 T in mode 2 as described above.
(= 2048T / 4) ｛= 250 μsec (= 1 msec /
4)｝, 256T (= 2048T / 8) in mode 3
｛= 125 μsec (= 1 msec / 8)｝, 1024T (= 2048/2) ｛= 500 μsec (1 m in mode 4)
sec / 2)｝.

Further, in the mode 1, the guard interval time within the symbol excluding the null symbol is 504T (=
246 μsec), 126 T (= 504 T /
4) {= 61.5 μsec (= 246 μsec / 4)}, 63T (= 504T / 8)} = 30.75 μ in mode 3
sec (= 246 μsec / 8)｝, 252T in mode 4
(= 504T / 2) ｛= 123 μsec (= 246 μsec)
/ 2)｝.

FIG. 10 shows a summary of the structure of the frame shown in FIG. 9, and FIG. 10 will be described briefly. DA
The transmission frame (transmission frame) of B is
SYNCC (synchronization channel)
FIC (Fast Information Channel)
MSC (Main Service Channel). The MSC is time interleaved and the FIC is not time interleaved.

The FIC is composed of a plurality of FIBs (fast information blocks). MSC
Means multiple CIFs (Common Interleaved Frames)
Consists of

[0017] The FIC includes a code indicating a program type called a program type, and is used for quick reception by a DAB receiver.

The MSC contains various audios and various data.

Next, the structure of the FIB (fast information block) shown in FIG. 10 will be described with reference to FIG. One FIB consists of 256 bits, of which 30 bytes (= 240 bits) are assigned to a FIB data field and the remaining 16 bits are assigned to a CRC (cyclic redundancy check) code for the FIB data field.

[0020] The FIB data field is
(Fast Information Group) v, ......
..,...,...,..., And is composed of a valid data field of 1 byte or more, in this case, 29 bytes, an end marker (having a header field but not having a FIG data field), and padding.

FIG. 3 is composed of an FIG type consisting of 3 bits b7... B5, a length (data length) consisting of 5 bits b4... B0, and an FIG data field.

The FIG type is from FIG0 to FIG7, and FIG0 (FIG type is "000") represents multiplex configuration, reconfiguration, time, date, and basic service information. FIG. 1 (FIG type is “001”) indicates display and other information definition labels. FIG2 (FIG type is "010"), FIG3 (FIG type is "011")
And FIG. 4 (FIG type is “100”) are reserved. FIG5 (FIG type is "101") represents a high-speed information data channel. FIG 6 (FIG type is “110”) indicates control and management information on the scrambled service configuration. FIG7
(FIG type is "111") represents in-house.

Next, the extension (extension type) of FIG types 0, 1, and 5 will be described. FIG type 0 extension 0 (FIG0 / 0) ensemble information FIG type 0 extension 1 (FIG0 / 1) Subchannel configuration FIG type 0 extension 2 (FIG0 / 2) Definition of basic services and service components FIG type 0 extension 3 (FIG0) / 3) Definition of service components in packet mode FIG type 0 extension 4 (FIG0 / 4) Service component with restricted access in FIG or stream mode FIG type 0 extension 5 (FIG0 / 5) Service component language FIG type 0 extension 6 (FIG0 / 6) Service linking information Fig type 0 extension 7 (FIG0 / 7) Paging, TMC (traffic message channel: traffic information channel), EWS (emergency alert system information), etc. External data service component information FIG type 0 extension 9 (FIG 0/9) Local time offset (LTO) FIG type 0 extension 10 (FIG 0/10) Date and time (UTC) FIG type 0 extension 11 (FIG 0/11) Region Definition Fig type 0 extension 12 (FIG0 / 12) Program type review FIG type 0 extension 16 (FIG0 / 16) Program number FIG type 0 extension 17 (FIG0 / 17) Program type FIG type 0 extension 18 (FIG0 / 18) Announcement Mention FIG type 0 extension 19 (FIG0 / 19) Announcement switching FIG type 0 extension 20 (FIG0 / 20) Service trigger FIG type 0 extension 21 (FIG0 / 21) Frequency information (FI) FIG type 0 extension 22 (FIG0 / 22) Transmitter ID information (TII) FIG type 0 extension 23 (FIG0 / 23) Local service area FIG type 0 extension 24 (FIG0 / 24) Other ensemble services FIG type 0 extension 25 (FIG0 / 25) Announcement support (other ensemble) FIG type 0 extension 26 (FIG0 / 26) Announcement switching (other ensemble) FIG type 0 extension 27 (FIG0 / 27) FM announcement support FIG type 0 extension 28 (FIG0 / 28) FM announcement switching FIG type 0 extension 29 (FIG0 / 29) Satellite handover FIG type 0 extension 30 (FIG0 / 30) Satellite database FIG type 0 extension 31 (FIG0 / 31) IG Redirection FIG Type 1 Extension 0 (FIG0 / 0) Ensemble Label FIG Type 1 Extension 1 (FIG0 / 1) Program Service Label FIG Type 1 Extension 2 (FIG0 / 2) Program Type Download FIG Type 1 Extension 3 (FIG0 / 3) Area label Fig type 1 extension 5 (FIG 0/5) Data service label FIG type 5 extension 0 (FIG 0/0) Paging FIG type 5 extension 1 (FIG 0/1) Traffic information FIG type 5 extension 2 (FIG 0/1) Emergency alert

Next, format information indicating the format of the data portion of the input data (encoded data) will be described with reference to FIG. FIG type 0 extension 2 (FIG0 / 2) and FIG type 0 extension 7 (FI
G0 / 7) includes format information,
Format information (FI) is included in a predetermined position in an MSC (main service channel), and data (pointer) indicating the position of the format information in the MSC is included in FIG type 0 extension 1 (FIG0 / 1). In this case, the MOT (multimedia object
Transfer protocol). The latter is adopted when encoded data to which header information is added in advance is directly added to a DAB signal (when format information in MSC is included as footer information at the end of data). There is also).

When extracting the format information in the MSC from the position data contained in FIG.
Extraction is possible even when C has not been detimed yet.

FIG. 13 shows format information when MOT is used. In FIG. 13, 15-bit data b14 of the content type and the content sub-type...
The type of format is represented by b0. still,
Descriptions of various coding methods such as MPEG and JEPEG in FIG. 13 are omitted.

Next, a conventional configuration of the source decoder 27 shown in FIG. 8 will be described with reference to FIG. Reference numeral 2 denotes a Viterbi decoder described with reference to FIG. 8, which includes a memory 3, and which is provided with an header provided from the fast Fourier transform circuit 25 of FIG. The data is supplied, the header information (FIC) is separated, MSC error correction (Viterbi decoding), detime interleaving (performed using the memory 3), and division of a multiplexed program are performed. And a data section (MSC), and the header information and the data section are stored in the memory 6 of the microcomputer 5 described below.

Reference numeral 5 denotes a microcomputer which receives the header information from the Viterbi decoder 2, analyzes the header information, and determines the data format of the data portion of the input data supplied to the input terminal 1. The memory 6 stores information indicating a decoding algorithm corresponding to the header analysis information analyzed by the microcomputer 5. In the case of a DAB signal, the data portion of the input data is an MPEG (moving picture expert group) compressed signal (a compressed signal of another compressed code is also possible).

The data section from the Viterbi decoder 2 is supplied to a plurality of, here two, hardware decoders 8 and 9. The hardware decoders 8 and 9 decode a plurality of data portions of the encoded data provided with the header supplied to the Viterbi decoder 2, in this case, two different decoding algorithms corresponding to different formats. I do. The hardware decoders 8 and 9 are specifically MPEG decoders of different types.

The microcomputer 5 obtains a decoding algorithm corresponding to the header analysis information from the memory 6, selects a hardware decoder of the decoding algorithm, supplies a control signal, sets the operation state, and sets a hardware decoder. A control signal is supplied to a switching circuit 10 for switching between the decoded data of 8 and 9 and the switching circuit 10 is switched to one of the hardware decoders 8 and 9 which is in an operating state to convert the decoded data. Output to the output terminal 7.

The microcomputer 5 obtains a decoding algorithm corresponding to the header analysis information from the memory 6, selects both the hardware decoders 8 and 9 of the decoding algorithm, supplies a control signal, and supplies an operation state. At the same time, a control signal may be supplied to the switching circuit 10 for switching to output the respective decoded data from the hardware decoders 8 and 9 to the output terminals 7 and 7 '.

The decoded data from the output terminal 7 is
If D / A conversion is performed by the D / A converter, an analog audio signal (an analog video signal is also possible) can be obtained.

[0033]

In the conventional decoder,
Since a number of hardware decoders corresponding to the number of possible formats of the data part of the encoded data provided with the header information supplied to the Viterbi decoder 2 are required, the larger the number of formats, the more correspondingly The configuration of the decoder is complicated.

Instead of providing a plurality of hardware decoders, it is conceivable to construct a decoder with a microprocessor and a software program and prepare software corresponding to the number of input data formats. If encoded input data is input, there is a possibility that software cannot handle the input data.

In view of the above, the present invention relates to input data having a header including information indicating the data format of a data portion, and even if the data formats of the data portion are different from each other, Even if the data format of the data section is based on an advanced encoding technology, the data section can be converted with a simple configuration,
It is intended to propose a decoder that can reliably decode.

[0036]

A decoder according to the present invention includes a rewritable hardware decoder for decoding a data portion of input data having a header including information indicating a data format of the data portion, and a data of a header of the input data. Control means for rewriting the decoding algorithm of the rewritable hardware decoder to a decoding algorithm corresponding to the data format of the data part of the input data based on the information indicating the format of the section.

According to the present invention, it is possible to rewrite the data portion of the input data provided with the header including the information indicating the data format of the data portion, based on the information indicating the format of the data portion of the header of the input data. The decoding algorithm of the hardware decoder is rewritten by the control means to a decoding algorithm corresponding to the data format of the data part of the input data.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A decoder according to an embodiment of the present invention will be described below with reference to FIG.
Parts corresponding to 4 will be described with the same reference numerals.
The embodiments described below are applied to the source decoder 27 of the DAB receiver described with reference to FIG.

The embodiment shown in FIG. 1 will be described. 2 is FIG.
The Viterbi decoder described in the above, including the memory 3,
The encoded data having the header including the information indicating the data format of the data part is supplied from the fast Fourier transform circuit 25 of FIG. 8 via the input terminal 1, and the header information (FIC) is divided and the error of the MSC is corrected. Correction (Viterbi decoding), detime interleaving (performed using the memory 3) and division of a multiplex program are performed, and header information (FIC) and a data part (MSC) are output.
These header information and data portion are stored in the memory 6 of the microcomputer 5 described below.

When the header information (FIC) includes format information, the microcomputer 5 detects the format information from the header information (FIC) supplied from the Viterbi decoder 2 to the microcomputer 5. , The header information (FIC) includes position data (pointer) indicating the position in the MSC (main service channel) of the format information (M
In the case of (OT), format information in the MSC is detected in the Viterbi decoder 2 based on the position data, and the format information is supplied to the microcomputer 5 together with header information (FIC).

Reference numeral 5 denotes a microcomputer which receives the header information from the Viterbi decoder 2 and analyzes the header information or determines the format of the input data supplied to the input terminal 1 from the format information. The memory 6 stores information (circuit data) indicating a decoding algorithm corresponding to the header analysis information analyzed by the microcomputer 5.

The data section from the Viterbi decoder 2 is supplied to a rewritable hardware decoder 4. The microcomputer 5 obtains a decoding algorithm corresponding to the header analysis information (format information) from the memory 6, supplies the decoding algorithm to the hardware decoder 4, and writes the decoding algorithm in the decoder 4. When the decoder 4 is ready to decode, the microcomputer 5 supplies a control signal to the decoder 4 to perform a decoding operation to cause the Viterbi decoder 2 to decode the data portion, and obtains the decoded data. Is output to the output terminal 7. The decoder 4 is composed of, for example, a decompression decoder (for example, an MPEG decoder) that decompresses the data portion of the input data that has been compressed and encoded. Further, the decoder 4 may be constituted by, for example, a decryption decoder for decrypting the data portion of the input data which has been encrypted and encoded, but is not limited thereto.

Although not shown, the decoded data obtained at the output terminal 7 is subjected to D / A conversion by a D / A converter to obtain an analog audio signal (an analog video signal is also possible).

Next, the operation of rewriting the decoding algorithm of the hardware decoder 4 will be described with reference to FIG. In step ST-1, when the encoded data (input data) having the header is supplied from the input terminal 1 to the Viterbi decoder 2 in step ST-1, the microcomputer 5 receives the header information (MSC) received from the Viterbi decoder 2 for the input data. (Including format information).

The microcomputer 5 executes step ST
-2, based on the analysis result (format of the data part of the input data) of the header information in step ST-1,
It is determined whether the data part obtained from the Viterbi decoder 2 can be decoded by the current decoder algorithm set in the hardware decoder 4. If the determination result of step ST-2 by the microcomputer 5 is YES,
That is, when it is determined that decoding is possible, the microcomputer 5 does not rewrite the decoding algorithm of the decoder 4 (step ST-6), and proceeds to step S6.
Proceeding to T-5, a control signal is supplied to the decoder 4,
The decoding of the data part from the Viterbi decoder 2 is executed.

Step S by microcomputer 5
If the determination result in T-2 is NO, that is, if it is determined that the decoding of the data portion from the Viterbi decoder 2 is impossible with the current decoding algorithm of the decoder 4, the microcomputer 5 proceeds to step ST-3. Then, by supplying the header analysis information (data format of the data section) to the memory 6, the memory 6 is searched for circuit data indicating a decoding algorithm to be set in the decoder 4. The microcomputer 5 executes Step ST-4.
Then, the circuit data obtained from the memory 6 is supplied to the decoder 4, and the decoding algorithm of the decoder 4 is rewritten according to the circuit data.

When the rewriting of the decoding algorithm of the decoder 4 is completed, the microcomputer 5 supplies a control signal to the decoder 4 in step ST-5,
The data section from the Viterbi decoder 2 is decoded. Upon completion of the process in the step ST-5, a step S
Return to T-1.

As described above, since the rewriting of the decoding algorithm of the decoder 4 requires a certain time, it is impossible to decode the data portion during the rewriting time. Therefore, in the case of the DAB signal, as shown in FIG. 3, of the encoder data provided with the header supplied to the Viterbi decoder 2, the portion excluding the header, that is, the data portion includes
Since the time interleave is applied, it takes time for the Viterbi decoder 2 to de-interleave the portion excluding the header, that is, the data portion. Assuming that this time is T 'and the time required for rewriting the decoding algorithm in the decoder 4 is t, if t <T', then despite the rewriting of the decoding algorithm of the decoder 4, the decoder 4 The data section from the Viterbi decoder 2 can be decoded without interruption.

Next, the embodiment of FIG. 4 will be described. Multiplexer 1 for switching data section from Viterbi decoder 2
2A, two decoder sections (the same as the rewritable hardware decoder 4 in FIG. 1) 12B and 12 to which the data section switched by the multiplexer 12A is supplied.
A programmable device 12 comprising C and output switching means 12D for switching decoded data from the decoder sections 12B and 12C is provided instead of the rewritable decoder 4 of the decoder of FIG. According to this embodiment, during the decoding of one of the decoder units 12A and 12B, the decoding algorithm of the other decoder is rewritten to a decoding algorithm corresponding to the format of the data part of the input data to be input, and Let them alternate. In this way, even if T '<t, if t is not so long, the Viterbi decoder 2
Can be decoded without interruption.

When t is a relatively long time,
In the embodiment shown in FIG.
If a predetermined number or more is provided, the data portion from the Viterbi decoder 2 can be decoded without interruption.

Next, the embodiment of FIG. 5 will be described. A circuit information data receiving unit 4A is provided in the rewritable decoder 4 of the decoder of FIG. Although not shown, a transmission means for transmitting new decoding circuit data corresponding to a format of new input data having a header is provided. When the information (circuit data) indicating the new decoding algorithm corresponding to the format of the new input data supplied to the Viterbi decoder 2 is not stored in the memory 6, the circuit information data receiving unit 4A of the decoder 4 is previously stored.
Receives new circuit information data from the transmission means, supplies the received circuit information data to the microcomputer 5, and writes the circuit information data to the memory 6. The microcomputer 5 supplies the new circuit information data written in the memory 6 to the decoder 4,
The decoder algorithm is rewritten to a decoder algorithm based on the new circuit information data.

It is to be noted that new circuit information data corresponding to new input data having a header
When new input data having a header is supplied to the Viterbi decoder 2, the microcomputer 5 supplies the new circuit information data written in the memory 6 to the decoder 4, and The algorithm may be rewritten to a decoder algorithm based on the new circuit information data.

Therefore, according to the data decoding of this embodiment, the new information (circuit data) indicating the decoding algorithm corresponding to the data format of the data part of the new input data is not stored in the memory 6. Even so, the decoding algorithm of the decoder 4 can be rewritten to a decoding algorithm corresponding to the format of the data part of the new input data, and the data part from the Viterbi decoder 2 can be decoded.

Next, the operation of rewriting the decoding algorithm of the hardware decoder 4 of the decoder of the embodiment of FIG. 5 will be described with reference to FIG. In step ST-1, when encoded data (input data) having a header is supplied from the input terminal 1 to the Viterbi decoder 2, the microcomputer 5 receives the header information (data) of the input data received from the Viterbi decoder 2. (Including information indicating the format of the copy).

The microcomputer 5 executes step ST
In -2, it is determined from the analysis result of the header information in step ST-1 whether the data format of the data part of the input data is information indicating a new data format, and NO, that is, not new If it is determined that the information indicates the data format, the process proceeds to step ST-
At 6, the normal decoding operation shown in FIG. 2 is performed.

If the determination in step ST-2 is YES, that is, if it is determined that the format of the data portion of the input data is a new data format, the microcomputer 5 determines in step ST-3 that the circuit The information data receiving section 4A receives circuit information data indicating a new data format from the transmission means, and the microcomputer 5 takes in the circuit information data.

The microcomputer 5 executes step ST
At -4, the circuit information (circuit data) of the decoder 4 is taken into the memory 6. Then, in step ST-5, the microcomputer 5 adds a new data format to the header analysis routine, and then returns to step ST-1.

Next, the embodiment shown in FIG. 7 will be described. This embodiment is the same as the embodiment shown in FIG.
2 is partially modified. In other words, if there is room in the programmable device 12, circuit means having another function can be provided. In this case, the multiplexer 12A in FIG. 4 is omitted, and the data section from the Viterbi decoder 2 is replaced with the decoder section 1
Supply directly to 2B, 12C. Output switching means 12D
The decoded data is supplied to an output terminal 7.

Circuit means 12E having another function is provided. In the circuit means 12E, for example, compression processing of a digital audio signal (a digital video signal is also possible) is performed, and the processed data is output to the output terminal 14. Also, a part or most of the above-mentioned functions of the Viterbi decoder 2 can be performed by the circuit means 12E. For example, it is possible for the Viterbi decoder 2 to perform only the error correction processing and cause the circuit means 12E to perform the remaining functions.

The present invention can be applied to a case where the data portion of the header of the input data is encrypted.

[0061]

According to the first aspect of the present invention, a rewritable hardware decoder for decoding a data portion of input data provided with a header including information indicating a data format of the data portion, and a data portion of a header of the input data Control means for rewriting the decoding algorithm of the rewritable hardware decoder to a decoding algorithm corresponding to the data format of the data portion of the input data based on the information indicating the format of the data portion. Even if the input data includes a header including the input data and the data format of the data portion is different from each other, or the data format of the data portion is based on the advanced encoding technology, Can be reliably decoded with a simple configuration It can be obtained a decoder can Rukoto.

According to the second aspect of the present invention, in the decoder of the first aspect of the present invention, the decoding algorithm already set in the hardware decoder based on the information indicating the format of the data portion of the header of the input data, Determining means for determining whether the decoding algorithm is the same as the decoding algorithm corresponding to the data format of the data part of the input data is provided. When it is determined that the decoding algorithm is different from the decoding algorithm corresponding to the data format of the decoding unit, the decoding unit which is already set in the hardware decoder is controlled by the control unit based on the information indicating the format of the data unit in the header of the input data. The algorithm is used in the data section of the input data. Since the decoding algorithm is rewritten to a decoding algorithm corresponding to the format, in addition to the effect of the first aspect of the invention, when the format of the data portion of the continuous input data is the same, the decoding algorithm already set in the hardware decoder is used. A new decoder algorithm eliminates the need for rewriting, so that even if a relatively long time is required to rewrite the decoding algorithm, obtain a decoder that can decode the data portion of the input data without interruption Can be.

According to the third invention, in the decoder of the first invention, a plurality of rewritable hardware decoders are provided, and among the plurality of rewritable hardware decoders, a decoder being decoded is used. The decoding algorithm of the remaining decoders is rewritten according to the data format of the data portion of the input data to be input, and a plurality of rewritable hardware decoders are switched to be used for decoding the data portion of the input data. Therefore, in addition to the effect of the first aspect of the present invention, T ′ is the time required for the Viterbi decoder 2 to remove the header, that is, the time required for detime interleaving of the data part, and t is When the time required for rewriting the algorithm of t is t, T ′ <t
Thus, it is possible to obtain a decoder that can decode the data portion without interruption even when t is a considerably long time.

According to the fourth aspect of the present invention, the decoder according to the first aspect of the present invention is provided with receiving means for externally receiving information indicating the data format of the data portion of the input data. In addition to the effect of the above, even when information indicating a decoding algorithm corresponding to the data format of the data portion of the input data is not prepared,
The decoding algorithm of the decoder can be rewritten to a decoding algorithm corresponding to the format of the data part of the input data.

According to the fifth aspect of the present invention, in the decoder according to the fourth aspect of the present invention, storage means for storing information indicating a decoding algorithm corresponding to the data format of the data portion of the input data is provided. When the information indicating the decoding algorithm corresponding to the data format of the data part of the input data is not stored, the receiving means receives the information indicating the data format of the data part of the input data from outside, and based on the information, Since the decoding algorithm of the rewritable hardware decoder is rewritten, in addition to the effect of the fourth aspect of the present invention, when the information indicating the decoding algorithm corresponding to the format of the data part of the input data is not present in the storage means. Even if there is a decoding function that can decode the data part of the input data. It is possible to obtain.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart for explaining a rewriting operation of the hardware decoder of the embodiment in FIG. 1;

FIG. 3 is an explanatory diagram of a rewriting time of a hardware decoder.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing still another embodiment of the present invention.

FIG. 6 is a flowchart for taking in a new data format in the embodiment of FIG. 5;

FIG. 7 is a block diagram showing still another embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a DAB receiver.

FIG. 9 is a diagram showing the configuration of a DAB mode 1 frame.

FIG. 10 is a diagram showing an outline of a configuration of a frame shown in FIG. 9;

FIG. 11 is a diagram showing a configuration of an FIB.

FIG. 12 is an explanatory diagram of format information.

FIG. 13 is a table showing format information when MOT is used.

FIG. 14 is a block diagram showing a configuration of a conventional decoder.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal to which the encoded data provided with the header is supplied, 2 ... Viterbi decoder, 3 ... Memory, 4 ... Rewritable hardware decoder, 5 ... Microcomputer, 6 ... Memory, 7 ... Decode data output terminal

Claims (5)

[Claims] 1. A rewritable hardware decoder for decoding a data portion of input data provided with a header including information indicating a data format of a data portion, based on information indicating a format of a data portion of the header of the input data. Control means for rewriting a decoding algorithm of the rewritable hardware decoder to a decoding algorithm corresponding to a data format of a data part of the input data. 2. The decoder according to claim 1, wherein, based on information indicating a format of a data part of the header of the input data, a decoding algorithm already set in the hardware decoder determines the decoding algorithm of the input data. Determining means for determining whether or not the decoding algorithm is the same as the decoding algorithm according to the data format of the data portion, and the determining means determines that the decoding algorithm already set in the hardware decoder is the data of the input data; When it is determined that the decoding algorithm is different from the decoding algorithm corresponding to the data format of the input data, the setting is already set in the hardware decoder based on information indicating the format of the data portion of the header of the input data under the control of the control means. The above decoding algorithm is Decoder being characterized in that the rewritten to decode algorithm in accordance with the data format of the data portion of the input data. 3. The decoder according to claim 1, further comprising a plurality of said rewritable hardware decoders, wherein said plurality of rewritable hardware decoders are provided.
The decoding algorithm of the remaining decoders other than the decoder being decoded is rewritten according to the data format of the data portion of the input data for which input is scheduled, and the plurality of rewritable hardware decoders are switched to change the input data. Decoding characterized in that it is used for decoding the data part. 4. The decoder according to claim 1, further comprising: receiving means for externally receiving information indicating a data format of a data portion of the input data. 5. The decoder according to claim 4, further comprising: storage means for storing information indicating a decoding algorithm corresponding to a data format of a data part of the input data, wherein the storage means stores When the information indicating the decoding algorithm corresponding to the data format is not stored, the receiving means receives information indicating the data format of the data part of the input data from outside, and performs the rewriting based on the information. A decoder characterized in that a decoding algorithm of a possible hardware decoder is rewritten.